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[/] [hive/] [trunk/] [v04.05/] [alu_top.v] - Blame information for rev 4

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/*
--------------------------------------------------------------------------------
 
Module : alu_top.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor ALU top level.
 
Instantiates:
- (2x) pipe.v
- (1x) alu_logical.v
  - (4x) pipe.v
- (1x) alu_add_sub.v
  - (4x) pipe.v
- (1x) alu_mult_shift.v
  - (3x) pipe.v
  - (1x) alu_multiply.v
    - (1x) pipe.v (debug mode only)
- (1x) alu_mux.v
  - (4x) pipe.v
 
Notes:
- I/O registered.
- Multi-stage pipeline w/ 5 mid registers.
 
--------------------------------------------------------------------------------
*/
 
module alu_top
        #(
        parameter       integer                                                 DATA_W                  = 32,           // data width
        parameter       integer                                                 ADDR_W                  = 16,           // address width
        parameter       integer                                                 LG_SEL_W                        = 4             // operation width
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire                                                            sgn_i,                                          // 1=signed
        input                   wire                                                            ext_i,                                          // 1=extended result
        input                   wire                                                            hgh_i,                                          // 1=high
        input                   wire    [LG_SEL_W-1:0]                   lg_sel_i,                                       // logic operation (see lg_sel_encode.h)
        input                   wire                                                            add_i,                                          // 1=add
        input                   wire                                                            sub_i,                                          // 1=subtract
        input                   wire                                                            mul_i,                                          // 1=multiply
        input                   wire                                                            shl_i,                                          // 1=shift left
        input                   wire                                                            pow_i,                                          // 1=power of 2
        input                   wire                                                            rtn_i,                                          // 1=return pc
        input                   wire                                                            dm_rd_i,                                                // 1=read
        input                   wire                                                            rg_rd_i,                                                // 1=read
        // data I/O
        input                   wire    [DATA_W-1:0]                     a_i,                                                    // operand
        input                   wire    [DATA_W-1:0]                     b_i,                                                    // operand
        input                   wire    [DATA_W/2-1:0]                   dm_rd_data_4_i,                 // dmem read data
        input                   wire    [DATA_W/2-1:0]                   rg_rd_data_4_i,                 // regs read data
        input                   wire    [ADDR_W-1:0]                     pc_3_i,                                         // program counter
        output          wire    [DATA_W-1:0]                     result_6_o,                                     // result
        // flags
        output          wire                                                            flg_nz_2_o,                                     //      a != 0
        output          wire                                                            flg_lz_2_o,                                     //      a < 0
        output          wire                                                            flg_ne_2_o,                                     //      a != b
        output          wire                                                            flg_lt_2_o                                      //      a < b
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        wire                                                                                            rg_rd_1, dm_rd_1, rtn_1, pow_1, shl_1, mul_1, sub_1, add_1, hgh_1, ext_1, sgn_1;
        wire                                    [LG_SEL_W-1:0]                   lg_sel_1;
        wire                                    [DATA_W-1:0]                     a_1, b_1;
        wire                                    [DATA_W-1:0]                     res_lg_2, res_as_2, res_ms_5;
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // input ctrl regs
        pipe
        #(
        .DEPTH                          ( 1 ),
        .WIDTH                          ( 11+LG_SEL_W ),
        .RESET_VAL                      ( 0 )
        )
        in_regs_ctrl
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .data_i                         ( { rg_rd_i, dm_rd_i, rtn_i, pow_i, shl_i, mul_i, sub_i, add_i, hgh_i, ext_i, sgn_i, lg_sel_i } ),
        .data_o                         ( { rg_rd_1, dm_rd_1, rtn_1, pow_1, shl_1, mul_1, sub_1, add_1, hgh_1, ext_1, sgn_1, lg_sel_1 } )
        );
 
 
        // input data regs
        pipe
        #(
        .DEPTH                          ( 1 ),
        .WIDTH                          ( DATA_W+DATA_W ),
        .RESET_VAL                      ( 0 )
        )
        in_regs_data
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .data_i                         ( { b_i, a_i } ),
        .data_o                         ( { b_1, a_1 } )
        );
 
 
        // logical unit
        alu_logical
        #(
        .REGS_IN                                ( 0 ),
        .REGS_MID                       ( 1 ),
        .REGS_OUT                       ( 0 ),
        .REGS_FLG                       ( 1 ),
        .DATA_W                         ( DATA_W ),
        .LG_SEL_W                       ( LG_SEL_W )
        )
        alu_logical
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .lg_sel_i                       ( lg_sel_1 ),
        .a_i                                    ( a_1 ),
        .b_i                                    ( b_1 ),
        .result_o                       ( res_lg_2 ),
        .flg_nz_o                       ( flg_nz_2_o ),
        .flg_lz_o                       ( flg_lz_2_o )
        );
 
 
        // add & subtract unit
        alu_add_sub
        #(
        .REGS_IN                                ( 0 ),
        .REGS_MID                       ( 1 ),
        .REGS_OUT                       ( 0 ),
        .REGS_FLG                       ( 1 ),
        .DATA_W                         ( DATA_W )
        )
        alu_add_sub
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .sgn_i                          ( sgn_1 ),
        .ext_i                          ( ext_1 ),
        .sub_i                          ( sub_1 ),
        .a_i                                    ( a_1 ),
        .b_i                                    ( b_1 ),
        .result_o                       ( res_as_2 ),
        .flg_ne_o                       ( flg_ne_2_o ),
        .flg_lt_o                       ( flg_lt_2_o )
        );
 
 
        // multiply & shift unit
        alu_mult_shift
        #(
        .REGS_IN                                ( 0 ),
        .REGS_OUT                       ( 0 ),
        .DATA_W                         ( DATA_W ),
        .DEBUG_MODE                     ( 0 )
        )
        alu_mult_shift
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .sgn_i                          ( sgn_1 ),
        .ext_i                          ( ext_1 ),
        .shl_i                          ( shl_1 ),
        .pow_i                          ( pow_1 ),
        .a_i                                    ( a_1 ),
        .b_i                                    ( b_1 ),
        .result_o                       ( res_ms_5 )
        );
 
 
        // multiplexer
        alu_mux
        #(
        .DATA_W                         ( DATA_W ),
        .ADDR_W                         ( ADDR_W )
        )
        alu_mux
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .sgn_1_i                                ( sgn_1 ),
        .hgh_1_i                                ( hgh_1 ),
        .as_1_i                         ( add_1 | sub_1 ),
        .ms_1_i                         ( mul_1 | shl_1 | pow_1 ),
        .rtn_1_i                                ( rtn_1 ),
        .dm_rd_1_i                      ( dm_rd_1 ),
        .rg_rd_1_i                      ( rg_rd_1 ),
        .res_lg_2_i                     ( res_lg_2 ),
        .res_as_2_i                     ( res_as_2 ),
        .pc_3_i                         ( pc_3_i ),
        .dm_rd_data_4_i ( dm_rd_data_4_i ),
        .rg_rd_data_4_i ( rg_rd_data_4_i ),
        .res_ms_5_i                     ( res_ms_5 ),
        .data_6_o                       ( result_6_o )
        );
 
 
endmodule

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[/] [hive/] [trunk/] [v04.05/] [alu_top.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : alu_top.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Processor ALU top level.`
10
11			`Instantiates:`
12			`- (2x) pipe.v`
13			`- (1x) alu_logical.v`
14			`- (4x) pipe.v`
15			`- (1x) alu_add_sub.v`
16			`- (4x) pipe.v`
17			`- (1x) alu_mult_shift.v`
18			`- (3x) pipe.v`
19			`- (1x) alu_multiply.v`
20			`- (1x) pipe.v (debug mode only)`
21			`- (1x) alu_mux.v`
22			`- (4x) pipe.v`
23
24			`Notes:`
25			`- I/O registered.`
26			`- Multi-stage pipeline w/ 5 mid registers.`
27
28			`--------------------------------------------------------------------------------`
29			`*/`
30
31			`module alu_top`
32			`#(`
33			`parameter integer DATA_W = 32, // data width`
34			`parameter integer ADDR_W = 16, // address width`
35			`parameter integer LG_SEL_W = 4 // operation width`
36			`)`
37			`(`
38			`// clocks & resets`
39			`input wire clk_i, // clock`
40			`input wire rst_i, // async. reset, active high`
41			`// control I/O`
42			`input wire sgn_i, // 1=signed`
43			`input wire ext_i, // 1=extended result`
44			`input wire hgh_i, // 1=high`
45			`input wire [LG_SEL_W-1:0] lg_sel_i, // logic operation (see lg_sel_encode.h)`
46			`input wire add_i, // 1=add`
47			`input wire sub_i, // 1=subtract`
48			`input wire mul_i, // 1=multiply`
49			`input wire shl_i, // 1=shift left`
50			`input wire pow_i, // 1=power of 2`
51			`input wire rtn_i, // 1=return pc`
52			`input wire dm_rd_i, // 1=read`
53			`input wire rg_rd_i, // 1=read`
54			`// data I/O`
55			`input wire [DATA_W-1:0] a_i, // operand`
56			`input wire [DATA_W-1:0] b_i, // operand`
57			`input wire [DATA_W/2-1:0] dm_rd_data_4_i, // dmem read data`
58			`input wire [DATA_W/2-1:0] rg_rd_data_4_i, // regs read data`
59			`input wire [ADDR_W-1:0] pc_3_i, // program counter`
60			`output wire [DATA_W-1:0] result_6_o, // result`
61			`// flags`
62			`output wire flg_nz_2_o, // a != 0`
63			`output wire flg_lz_2_o, // a < 0`
64			`output wire flg_ne_2_o, // a != b`
65			`output wire flg_lt_2_o // a < b`
66			`);`
67
68
69			`/*`
70			`----------------------`
71			`-- internal signals --`
72			`----------------------`
73			`*/`
74			`wire rg_rd_1, dm_rd_1, rtn_1, pow_1, shl_1, mul_1, sub_1, add_1, hgh_1, ext_1, sgn_1;`
75			`wire [LG_SEL_W-1:0] lg_sel_1;`
76			`wire [DATA_W-1:0] a_1, b_1;`
77			`wire [DATA_W-1:0] res_lg_2, res_as_2, res_ms_5;`
78
79
80			`/*`
81			`================`
82			`== code start ==`
83			`================`
84			`*/`
85
86
87			`// input ctrl regs`
88			`pipe`
89			`#(`
90			`.DEPTH ( 1 ),`
91			`.WIDTH ( 11+LG_SEL_W ),`
92			`.RESET_VAL ( 0 )`
93			`)`
94			`in_regs_ctrl`
95			`(`
96			`.clk_i ( clk_i ),`
97			`.rst_i ( rst_i ),`
98			`.data_i ( { rg_rd_i, dm_rd_i, rtn_i, pow_i, shl_i, mul_i, sub_i, add_i, hgh_i, ext_i, sgn_i, lg_sel_i } ),`
99			`.data_o ( { rg_rd_1, dm_rd_1, rtn_1, pow_1, shl_1, mul_1, sub_1, add_1, hgh_1, ext_1, sgn_1, lg_sel_1 } )`
100			`);`
101
102
103			`// input data regs`
104			`pipe`
105			`#(`
106			`.DEPTH ( 1 ),`
107			`.WIDTH ( DATA_W+DATA_W ),`
108			`.RESET_VAL ( 0 )`
109			`)`
110			`in_regs_data`
111			`(`
112			`.clk_i ( clk_i ),`
113			`.rst_i ( rst_i ),`
114			`.data_i ( { b_i, a_i } ),`
115			`.data_o ( { b_1, a_1 } )`
116			`);`
117
118
119			`// logical unit`
120			`alu_logical`
121			`#(`
122			`.REGS_IN ( 0 ),`
123			`.REGS_MID ( 1 ),`
124			`.REGS_OUT ( 0 ),`
125			`.REGS_FLG ( 1 ),`
126			`.DATA_W ( DATA_W ),`
127			`.LG_SEL_W ( LG_SEL_W )`
128			`)`
129			`alu_logical`
130			`(`
131			`.clk_i ( clk_i ),`
132			`.rst_i ( rst_i ),`
133			`.lg_sel_i ( lg_sel_1 ),`
134			`.a_i ( a_1 ),`
135			`.b_i ( b_1 ),`
136			`.result_o ( res_lg_2 ),`
137			`.flg_nz_o ( flg_nz_2_o ),`
138			`.flg_lz_o ( flg_lz_2_o )`
139			`);`
140
141
142			`// add & subtract unit`
143			`alu_add_sub`
144			`#(`
145			`.REGS_IN ( 0 ),`
146			`.REGS_MID ( 1 ),`
147			`.REGS_OUT ( 0 ),`
148			`.REGS_FLG ( 1 ),`
149			`.DATA_W ( DATA_W )`
150			`)`
151			`alu_add_sub`
152			`(`
153			`.clk_i ( clk_i ),`
154			`.rst_i ( rst_i ),`
155			`.sgn_i ( sgn_1 ),`
156			`.ext_i ( ext_1 ),`
157			`.sub_i ( sub_1 ),`
158			`.a_i ( a_1 ),`
159			`.b_i ( b_1 ),`
160			`.result_o ( res_as_2 ),`
161			`.flg_ne_o ( flg_ne_2_o ),`
162			`.flg_lt_o ( flg_lt_2_o )`
163			`);`
164
165
166			`// multiply & shift unit`
167			`alu_mult_shift`
168			`#(`
169			`.REGS_IN ( 0 ),`
170			`.REGS_OUT ( 0 ),`
171			`.DATA_W ( DATA_W ),`
172			`.DEBUG_MODE ( 0 )`
173			`)`
174			`alu_mult_shift`
175			`(`
176			`.clk_i ( clk_i ),`
177			`.rst_i ( rst_i ),`
178			`.sgn_i ( sgn_1 ),`
179			`.ext_i ( ext_1 ),`
180			`.shl_i ( shl_1 ),`
181			`.pow_i ( pow_1 ),`
182			`.a_i ( a_1 ),`
183			`.b_i ( b_1 ),`
184			`.result_o ( res_ms_5 )`
185			`);`
186
187
188			`// multiplexer`
189			`alu_mux`
190			`#(`
191			`.DATA_W ( DATA_W ),`
192			`.ADDR_W ( ADDR_W )`
193			`)`
194			`alu_mux`
195			`(`
196			`.clk_i ( clk_i ),`
197			`.rst_i ( rst_i ),`
198			`.sgn_1_i ( sgn_1 ),`
199			`.hgh_1_i ( hgh_1 ),`
200			`.as_1_i ( add_1 \| sub_1 ),`
201			`.ms_1_i ( mul_1 \| shl_1 \| pow_1 ),`
202			`.rtn_1_i ( rtn_1 ),`
203			`.dm_rd_1_i ( dm_rd_1 ),`
204			`.rg_rd_1_i ( rg_rd_1 ),`
205			`.res_lg_2_i ( res_lg_2 ),`
206			`.res_as_2_i ( res_as_2 ),`
207			`.pc_3_i ( pc_3_i ),`
208			`.dm_rd_data_4_i ( dm_rd_data_4_i ),`
209			`.rg_rd_data_4_i ( rg_rd_data_4_i ),`
210			`.res_ms_5_i ( res_ms_5 ),`
211			`.data_6_o ( result_6_o )`
212			`);`
213
214
215			`endmodule`