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[/] [hive/] [trunk/] [v04.05/] [boot_code/] [boot_code_v_io.h] - Blame information for rev 4

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1 4 ericw 
/*
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--------------------------------------------------------------------------------
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Module : boot_code.h
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--------------------------------------------------------------------------------
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Function:
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- Boot code for a processor core.
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Instantiates:
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- Nothing.
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Notes:
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- For testing (@ core.v):
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  CLR_BASE              = 'h0;
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  CLR_SPAN              = 2;  // gives 4 instructions
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  INTR_BASE             = 'h20;  // 'd32
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  INTR_SPAN             = 2;  // gives 4 instructions
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--------------------------------------------------------------------------------
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*/
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        /*
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        --------------------
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        -- external stuff --
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        --------------------
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        */
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        `include "op_encode.h"
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        `include "reg_set_addr.h"
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        `include "boot_code_defs.h"
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        /*
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        ----------------------------------------
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        -- initialize: fill with default data --
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        ----------------------------------------
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        */
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        integer i;
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        initial begin
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/*      // fill with nop (some compilers need this)
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        for ( i = 0; i < CAPACITY; i = i+1 ) begin
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                ram[i] = { `nop, `__, `__ };
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        end
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*/
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        /*
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        ---------------
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        -- boot code --
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        ---------------
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        */
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        // Thread 0 : test I/O functions
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        // All other threads : loop forever
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        ///////////////
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        // clr space //
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        ///////////////
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        // thread 0
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        i='h0;   ram[i] = { `lit_u,            `__, `s2 };  // s2='h0100
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        i=i+1;   ram[i] =                      16'h0100  ;  //
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        i=i+1;   ram[i] = { `gto,              `P2, `__ };  // goto, pop s2 (addr)
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        // thread 1
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        i='h4;   ram[i] = { `lit_u,            `__, `s2 };  // s2='h0200
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        i=i+1;   ram[i] =                      16'h0200  ;  //
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        i=i+1;   ram[i] = { `gto,              `P2, `__ };  // goto, pop s2 (addr)
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        // and the rest
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        i='h08;  ram[i] = { `jmp_ie,    -4'd1, `s0, `s0 };  // loop forever
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        i='h0c;  ram[i] = { `jmp_ie,    -4'd1, `s0, `s0 };  // loop forever
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        i='h10;  ram[i] = { `jmp_ie,    -4'd1, `s0, `s0 };  // loop forever
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        i='h14;  ram[i] = { `jmp_ie,    -4'd1, `s0, `s0 };  // loop forever
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        i='h18;  ram[i] = { `jmp_ie,    -4'd1, `s0, `s0 };  // loop forever
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        i='h1c;  ram[i] = { `jmp_ie,    -4'd1, `s0, `s0 };  // loop forever
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        ////////////////
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        // intr space //
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        ////////////////
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        ///////////////////////
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        // code & data space //
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        ///////////////////////
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        // test I/O functions, result in s0
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        // Correct functioning is s0 = 'd8 ('h8).
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        //
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        // s0 : final test result
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        // s1 : test value
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        // s2 : test value
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        // s3 : running test result, subroutine return address
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        //
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        // setup running test result:
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        i='h100; ram[i] = { `dat_is,          6'd0, `s3 };  // s3=0
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        // PGC
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        i=i+1;   ram[i] = { `pgc,              `__, `s1 };  // s1=PC
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        i=i+1;   ram[i] = { `lit_u,            `__, `s0 };  // s0='h0102
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        i=i+1;   ram[i] =                      16'h0102  ;  //
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        i=i+1;   ram[i] = { `jmp_ie,     4'd1, `P1, `P0 };  // (s0==s1) ? skip, pop both
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        i=i+1;   ram[i] = { `add_is,         -6'd1, `P3 };  // s3--
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        i=i+1;   ram[i] = { `add_is,          6'd1, `P3 };  // s3++
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        // setup test value:
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        i=i+1;   ram[i] = { `lit_u,            `__, `s1 };  // s1='h36c9,a53c
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        i=i+1;   ram[i] =                      16'ha53c  ;  //
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        i=i+1;   ram[i] = { `lit_h,            `__, `P1 };  //
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        i=i+1;   ram[i] =                      16'h36c9  ;  //
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        // MEM_IWH & MEM_IRH
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        i=i+1;   ram[i] = { `lit_u,            `__, `s2 };  // s2='h0a00
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        i=i+1;   ram[i] =                      16'h0a00  ;  //
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        i=i+1;   ram[i] = { `mem_iw,     4'd0, `s2, `s1 };  // (s2+offset)=s1
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        i=i+1;   ram[i] = { `mem_iwh,    4'd1, `s2, `s1 };  //
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        i=i+1;   ram[i] = { `mem_irs,    4'd0, `s2, `s0 };  // s0=(s2+offset)
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        i=i+1;   ram[i] = { `mem_irh,    4'd1, `P2, `P0 };  //
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        i=i+1;   ram[i] = { `jmp_ie,     4'd1, `s1, `P0 };  // (s0==s1) ? skip, pop s0
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        i=i+1;   ram[i] = { `add_is,         -6'd1, `P3 };  // s3--
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        i=i+1;   ram[i] = { `add_is,          6'd1, `P3 };  // s3++
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        // MEM_IRS (signed)
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        i=i+1;   ram[i] = { `lit_u,            `__, `s2 };  // s2='h0a00
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        i=i+1;   ram[i] =                      16'h0a10  ;  //
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        i=i+1;   ram[i] = { `mem_iw,     4'd0, `s2, `s1 };  // (s2+offset)=s1
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        i=i+1;   ram[i] = { `mem_irs,    4'd0, `P2, `s0 };  // s0=(s2+offset), pop s2
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        i=i+1;   ram[i] = { `shl_is,         6'd16, `s1 };  // s1<<=16
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        i=i+1;   ram[i] = { `shl_is,        -6'd16, `P1 };  // s1>>=16
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        i=i+1;   ram[i] = { `jmp_ie,     4'd1, `P1, `P0 };  // (s0==s1) ? skip, pop both
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        i=i+1;   ram[i] = { `add_is,         -6'd1, `P3 };  // s3--
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        i=i+1;   ram[i] = { `add_is,          6'd1, `P3 };  // s3++
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        // MEM_IRS (unsigned)
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        i=i+1;   ram[i] = { `lit_u,            `__, `s2 };  // s2='h0a00
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        i=i+1;   ram[i] =                      16'h0a20  ;  //
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        i=i+1;   ram[i] = { `mem_iwh,    4'd0, `s2, `s1 };  // (s2+offset)=s1
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        i=i+1;   ram[i] = { `mem_irs,    4'd0, `P2, `s0 };  // s0=(s2+offset), pop s2
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        i=i+1;   ram[i] = { `psu_i,        -6'd16, `s1 };  // s1>>=16
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        i=i+1;   ram[i] = { `jmp_ie,     4'd1, `P1, `P0 };  // (s0==s1) ? skip, pop both
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        i=i+1;   ram[i] = { `add_is,         -6'd1, `P3 };  // s3--
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        i=i+1;   ram[i] = { `add_is,          6'd1, `P3 };  // s3++
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        // REG_RS, REG_RH, REG_W & REG_WH (check manually for I/O loopback)
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        i=i+1;   ram[i] = { `dat_is,        `IO_LO, `s2 };  // s2=reg addr
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        i=i+1;   ram[i] = { `reg_rs,           `s2, `s1 };  // s1=(s2)
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        i=i+1;   ram[i] = { `reg_w,            `P2, `P1 };  // (s2)=s1, pop both
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        i=i+1;   ram[i] = { `dat_is,        `IO_HI, `s2 };  // s2=reg addr
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        i=i+1;   ram[i] = { `reg_rh,           `s2, `s1 };  // s1=(s2)
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        i=i+1;   ram[i] = { `reg_wh,           `P2, `P1 };  // (s2)=s1, pop s2
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        // LIT_S
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        i=i+1;   ram[i] = { `lit_s,            `__, `s0 };  // s0='ha53c
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        i=i+1;   ram[i] =                      16'ha53c  ;  //
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        i=i+1;   ram[i] = { `shl_is,         6'd16, `s1 };  // s1<<=16
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        i=i+1;   ram[i] = { `shl_is,        -6'd16, `P1 };  // s1>>=16, pop s1
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        i=i+1;   ram[i] = { `jmp_ie,     4'd1, `P1, `P0 };  // (s0==s1) ? skip, pop both
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        i=i+1;   ram[i] = { `add_is,         -6'd1, `P3 };  // s3--
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        i=i+1;   ram[i] = { `add_is,          6'd1, `P3 };  // s3++
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        // LIT_U
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        i=i+1;   ram[i] = { `lit_u,            `__, `s0 };  // s0='ha53c
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        i=i+1;   ram[i] =                      16'ha53c  ;  //
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        i=i+1;   ram[i] = { `shl_is,         6'd16, `s1 };  // s1<<=16
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        i=i+1;   ram[i] = { `psu_i,         -6'd16, `P1 };  // s1>>=16, pop s1
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        i=i+1;   ram[i] = { `jmp_ie,     4'd1, `P1, `P0 };  // (s0==s1) ? skip, pop both
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        i=i+1;   ram[i] = { `add_is,         -6'd1, `P3 };  // s3--
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        i=i+1;   ram[i] = { `add_is,          6'd1, `P3 };  // s3++
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        // check for no opcode errors
164 
        i=i+1;   ram[i] = { `lit_u,            `__, `s7 };  // s7='h0900
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        i=i+1;   ram[i] =                      16'h0900  ;  //
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        i=i+1;   ram[i] = { `gsb,              `P7, `s7 };  // gsb, pop s7 (addr)
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        i=i+1;   ram[i] = { `jmp_iz,          6'd1, `P4 };  // (s4==0) ? skip, pop s4
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        i=i+1;   ram[i] = { `add_is,         -6'd1, `P3 };  // s3--
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        i=i+1;   ram[i] = { `add_is,          6'd1, `P3 };  // s3++
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        // check for no stack errors
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        i=i+1;   ram[i] = { `lit_u,            `__, `s7 };  // s7='h0910
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        i=i+1;   ram[i] =                      16'h0910  ;  //
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        i=i+1;   ram[i] = { `gsb,              `P7, `s7 };  // gsb, pop s2 (addr)
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        i=i+1;   ram[i] = { `jmp_iz,          6'd1, `P4 };  // (s4==0) ? skip, pop s4
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        i=i+1;   ram[i] = { `add_is,         -6'd1, `P3 };  // s3--
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        i=i+1;   ram[i] = { `add_is,          6'd1, `P3 };  // s3++
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        // copy result to s0
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        i=i+1;   ram[i] = { `cpy,              `P3, `s0 };  // s0=s3, pop s3
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        // loop forever
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        i=i+1;   ram[i] = { `jmp_ie,    -4'd1, `s0, `s0 };  // loop forever
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        // end sub
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        // test UART
185 
        //
186 
        // s0 : TX value
187 
        // s1 :
188 
        // s2 : reg addr
189 
        // s3 :
190 
        // s4 : TX ready
191 
        //
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        //
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        i='h200; ram[i] = { `lit_u,            `__, `s0 };  // s0='h00a5
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        i=i+1;   ram[i] =                      16'h00a5  ;  //
195 
        i=i+1;   ram[i] = { `dat_is,      `UART_TX, `s2 };  // s2=reg addr
196 
        i=i+1;   ram[i] = { `reg_rs,           `s2, `s4 };  // s4=(s2)
197 
        i=i+1;   ram[i] = { `jmp_iz,          6'd1, `P4 };  // (s4==0) ? skip, pop s4
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        i=i+1;   ram[i] = { `reg_w,            `s2, `s0 };  // (s2)=s0
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        // loop forever
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        i=i+1;   ram[i] = { `jmp_ie,    -4'd1, `s0, `s0 };  // loop forever
201 
        // end sub
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204 
        /////////////////
205 
        // subroutines //
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        /////////////////
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209 
        // sub : read & clear opcode errors for this thread => s4, return to (s7)
210 
        // avoid the use of s1!
211 
        i='h900; ram[i] = { `dat_is,      `THRD_ID, `s6 };  // s6=reg addr
212 
        i=i+1;   ram[i] = { `reg_rs,           `P6, `s5 };  // s5=(s6), pop s6
213 
        i=i+1;   ram[i] = { `pow,              `P5, `s4 };  // s4=1<<s5, pop s5
214 
        i=i+1;   ram[i] = { `dat_is,        `OP_ER, `s6 };  // s6=reg addr
215 
        i=i+1;   ram[i] = { `reg_rs,           `s6, `s5 };  // s5=(s6)
216 
        i=i+1;   ram[i] = { `and,              `P5, `P4 };  // s4&=s5, pop s5
217 
        i=i+1;   ram[i] = { `reg_w,            `P6, `s4 };  // (s6)=s4, pop s6
218 
        i=i+1;   ram[i] = { `gto,              `P7, `__ };  // return to (s7), pop s7
219 
 
220 
 
221 
        // sub : read & clear stack errors for this thread => s4, return to (s7)
222 
        // avoid the use of s1!
223 
        i='h910; ram[i] = { `dat_is,      `THRD_ID, `s6 };  // s6=reg addr
224 
        i=i+1;   ram[i] = { `reg_rs,           `P6, `s5 };  // s5=(s6), pop s6
225 
        i=i+1;   ram[i] = { `pow,              `P5, `s4 };  // s4=1<<s5, pop s5
226 
        i=i+1;   ram[i] = { `cpy,              `s4, `s5 };  // s5=s4
227 
        i=i+1;   ram[i] = { `shl_is,          6'd8, `P5 };  // s5<<=8
228 
        i=i+1;   ram[i] = { `orr,              `P5, `P4 };  // s4|=s5, pop s5
229 
        i=i+1;   ram[i] = { `dat_is,       `STK_ER, `s6 };  // s6=reg addr
230 
        i=i+1;   ram[i] = { `reg_rs,           `s6, `s5 };  // s5=(s6)
231 
        i=i+1;   ram[i] = { `and,              `P5, `P4 };  // s4&=s5, pop s5
232 
        i=i+1;   ram[i] = { `reg_w,            `P6, `s4 };  // (s6)=s4, pop s6
233 
        i=i+1;   ram[i] = { `gto,              `P7, `__ };  // return to (s7), pop s7
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236 
        end

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