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[/] [hive/] [trunk/] [v04.05/] [control_ring.v] - Blame information for rev 4

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/*
--------------------------------------------------------------------------------
 
Module : control_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor control path.
 
Instantiates:
- (1x) thread_ring.v
- (2x) event_ctrl.v
- (1x) tst_decode.v
- (1x) op_decode.v
- (1x) pc_ring.v
 
Notes:
- 8 stage pipeline consisting of several storage rings.
 
--------------------------------------------------------------------------------
*/
 
module control_ring
        #(
        parameter       integer                                                 DATA_W                  = 32,           // data width
        parameter       integer                                                 ADDR_W                  = 16,           // address width
        parameter       integer                                                 THREADS                 = 8,            // threads
        parameter       integer                                                 THRD_W                  = 3,            // thread width
        parameter       integer                                                 STACKS                  = 8,            // number of stacks
        parameter       integer                                                 STK_W                           = 3,            // stack selector width
        parameter       integer                                                 IM_W                            = 6,            // immediate width
        parameter       integer                                                 MEM_DATA_W              = 16,           // opcode width
        parameter       integer                                                 LG_SEL_W                        = 4,            // logical operation width
        parameter       [ADDR_W-1:0]                                     CLR_BASE                        = 'h0,  // clear address base (concat)
        parameter       integer                                                 CLR_SPAN                        = 2,            // clear address span (2^n)
        parameter       [ADDR_W-1:0]                                     INTR_BASE               = 'h20, // interrupt address base (concat)
        parameter       integer                                                 INTR_SPAN               = 2             // interrupt address span (2^n)
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire    [THREADS-1:0]                    clr_req_i,                                      // clear request, active high
        output          wire    [THREADS-1:0]                    clr_ack_o,                                      // clear ack, active high until serviced
        input                   wire    [THREADS-1:0]                    intr_en_i,                                      // interrupt enable, active high
        input                   wire    [THREADS-1:0]                    intr_req_i,                                     // interrupt request, active high
        output          wire    [THREADS-1:0]                    intr_ack_o,                                     // interrupt ack, active high until serviced
        input                   wire    [MEM_DATA_W-1:0]         op_code_i,                                      // opcode
        output          wire                                                            op_code_er_o,                           // 1=illegal op code encountered
        // ALU I/O
        input                   wire    [ADDR_W-1:0]                     b_addr_i,                                       // b | im
        output          wire    [IM_W-1:0]                               im_o,                                                   // immediate
        output          wire    [STK_W-1:0]                              data_sel_a_o,                           // stack selector
        output          wire    [STK_W-1:0]                              data_sel_b_o,                           // stack selector
        output          wire    [STK_W-1:0]                              addr_sel_b_o,                           // b stack selector
        output          wire                                                            imda_o,                                         // 1=immediate data
        output          wire                                                            imad_o,                                         // 1=immediate address
        output          wire                                                            sgn_o,                                          // 1=signed
        output          wire                                                            ext_o,                                          // 1=extended
        output          wire                                                            hgh_o,                                          // 1=high
        output          wire    [LG_SEL_W-1:0]                   lg_sel_o,                                       // see decode in notes
        output          wire                                                            add_o,                                          // 1=add
        output          wire                                                            sub_o,                                          // 1=subtract
        output          wire                                                            mul_o,                                          // 1=multiply
        output          wire                                                            shl_o,                                          // 1=shift left
        output          wire                                                            pow_o,                                          // 1=power of 2
        output          wire                                                            rtn_o,                                          // 1=return pc
        output          wire                                                            lit_o,                                          // 1=literal data
        output          wire                                                            dm_rd_o,                                                // 1=read
        output          wire                                                            dm_wr_o,                                                // 1=write
        output          wire                                                            rg_rd_o,                                                // 1=read
        output          wire                                                            rg_wr_o,                                                // 1=write
        // stack I/O
        output          wire                                                            stk_clr_o,                                      // stacks clear
        output          wire    [STACKS-1:0]                     pop_o,                                          // stacks pop
        output          wire    [STACKS-1:0]                     push_o,                                         // stacks push
        // flags
        input                   wire                                                            flg_nz_2_i,                                     //      a != 0
        input                   wire                                                            flg_lz_2_i,                                     //      a < 0
        input                   wire                                                            flg_ne_2_i,                                     //      a != b
        input                   wire                                                            flg_lt_2_i,                                     //      a < b
        // threads
        output          wire    [THRD_W-1:0]                     thrd_0_o,
        output          wire    [THRD_W-1:0]                     thrd_2_o,
        output          wire    [THRD_W-1:0]                     thrd_3_o,
        output          wire    [THRD_W-1:0]                     thrd_6_o,
        // addresses
        output          wire    [ADDR_W-1:0]                     pc_1_o,
        output          wire    [ADDR_W-1:0]                     pc_3_o,
        output          wire    [ADDR_W-1:0]                     pc_4_o
        );
 
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        localparam                      integer                                 TST_W = 4;
        //
        wire                                                                                            pc_clr, cnd, zro, jmp, gto, intr, res_tst_3;
        wire                                                                                            stk_clr;
        wire                                    [STACKS-1:0]                     pop, push;
        wire                                    [TST_W-1:0]                              tst;
        wire                                                                                            thrd_clr, thrd_intr;
        wire                                    [THRD_W-1:0]                     thrd_4, thrd_5;
 
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // establish threads
        thread_ring
        #(
        .THREADS                        ( THREADS ),
        .THRD_W                 ( THRD_W )
        )
        thread_ring
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .thrd_0_o               ( thrd_0_o ),
        .thrd_1_o               (  ),
        .thrd_2_o               ( thrd_2_o ),
        .thrd_3_o               ( thrd_3_o ),
        .thrd_4_o               ( thrd_4 ),
        .thrd_5_o               ( thrd_5 ),
        .thrd_6_o               ( thrd_6_o ),
        .thrd_7_o               (  )
        );
 
 
        // handle external thread clear requests
        event_ctrl
        #(
        .REGS_REQ               ( 0 ),  // don't resync
        .EDGE_REQ               ( 1 ),  // edge sensitive
        .RESET_VAL              ( { THREADS{ 1'b1 } } ),  // clear threads @ power-up
        .THREADS                        ( THREADS ),
        .THRD_W                 ( THRD_W )
        )
        clr_event_ctrl
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .thrd_i                 ( thrd_5 ),
        .en_i                           ( { THREADS{ 1'b1 } } ),  // always enable
        .req_i                  ( clr_req_i ),
        .ack_o                  ( clr_ack_o ),
        .event_o                        ( thrd_clr )
        );
 
 
        // handle external thread interrupt requests
        event_ctrl
        #(
        .REGS_REQ               ( 2 ),  // resync
        .EDGE_REQ               ( 1 ),  // edge sensitive
        .RESET_VAL              ( 0 ),
        .THREADS                        ( THREADS ),
        .THRD_W                 ( THRD_W )
        )
        intr_event_ctrl
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .thrd_i                 ( thrd_5 ),
        .en_i                           ( intr_en_i ),
        .req_i                  ( intr_req_i ),
        .ack_o                  ( intr_ack_o ),
        .event_o                        ( thrd_intr )
        );
 
 
        // conditional jump etc. testing
        tst_decode
        #(
        .REGS_TST               ( 2 ),
        .REGS_OUT               ( 1 ),
        .TST_W                  ( TST_W )
        )
        tst_decode
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .flg_nz_i               ( flg_nz_2_i ),
        .flg_lz_i               ( flg_lz_2_i ),
        .flg_ne_i               ( flg_ne_2_i ),
        .flg_lt_i               ( flg_lt_2_i ),
        .cnd_i                  ( cnd ),
        .tst_i                  ( tst ),
        .result_o               ( res_tst_3 )
        );
 
 
        // op_code decoding
        op_decode
        #(
        .REGS_IN                        ( 0 ),
        .REGS_OUT               ( 1 ),
        .STACKS                 ( STACKS ),
        .STK_W                  ( STK_W ),
        .DATA_W                 ( DATA_W ),
        .IM_W                           ( IM_W ),
        .MEM_DATA_W             ( MEM_DATA_W ),
        .LG_SEL_W               ( LG_SEL_W ),
        .TST_W                  ( TST_W )
        )
        op_decode
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .thrd_clr_i             ( thrd_clr ),
        .thrd_intr_i    ( thrd_intr ),
        .op_code_i              ( op_code_i ),
        .op_code_er_o   ( op_code_er_o ),
        .im_o                           ( im_o ),
        .pc_clr_o               ( pc_clr ),
        .cnd_o                  ( cnd ),
        .lit_o                  ( lit_o ),
        .jmp_o                  ( jmp ),
        .gto_o                  ( gto ),
        .intr_o                 ( intr ),
        .tst_o                  ( tst ),
        .stk_clr_o              ( stk_clr_o ),
        .pop_o                  ( pop_o ),
        .push_o                 ( push_o ),
        .data_sel_a_o   ( data_sel_a_o ),
        .data_sel_b_o   ( data_sel_b_o ),
        .addr_sel_b_o   ( addr_sel_b_o ),
        .imda_o                 ( imda_o ),
        .imad_o                 ( imad_o ),
        .sgn_o                  ( sgn_o ),
        .ext_o                  ( ext_o ),
        .hgh_o                  ( hgh_o ),
        .lg_sel_o               ( lg_sel_o ),
        .add_o                  ( add_o ),
        .sub_o                  ( sub_o ),
        .mul_o                  ( mul_o ),
        .shl_o                  ( shl_o ),
        .pow_o                  ( pow_o ),
        .rtn_o                  ( rtn_o ),
        .dm_rd_o                        ( dm_rd_o ),
        .dm_wr_o                        ( dm_wr_o ),
        .rg_rd_o                        ( rg_rd_o ),
        .rg_wr_o                        ( rg_wr_o )
        );
 
 
        // pc generation & storage
        pc_ring
        #(
        .THREADS                                ( THREADS ),
        .THRD_W                         ( THRD_W ),
        .DATA_W                         ( DATA_W ),
        .ADDR_W                         ( ADDR_W ),
        .CLR_BASE                       ( CLR_BASE ),
        .CLR_SPAN                       ( CLR_SPAN ),
        .INTR_BASE                      ( INTR_BASE ),
        .INTR_SPAN                      ( INTR_SPAN )
        )
        pc_ring
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .thrd_0_i                       ( thrd_0_o ),
        .thrd_4_i                       ( thrd_4 ),
        .clr_i                          ( pc_clr ),
        .lit_i                          ( lit_o ),
        .jmp_i                          ( jmp ),
        .gto_i                          ( gto ),
        .intr_i                         ( intr ),
        .res_tst_3_i            ( res_tst_3 ),
        .b_addr_i                       ( b_addr_i ),
        .pc_0_o                         (  ),
        .pc_1_o                         ( pc_1_o ),
        .pc_2_o                         (  ),
        .pc_3_o                         ( pc_3_o ),
        .pc_4_o                         ( pc_4_o ),
        .pc_5_o                         (  ),
        .pc_6_o                         (  ),
        .pc_7_o                         (  )
        );
 
 
endmodule

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[/] [hive/] [trunk/] [v04.05/] [control_ring.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : control_ring.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Processor control path.`
10
11			`Instantiates:`
12			`- (1x) thread_ring.v`
13			`- (2x) event_ctrl.v`
14			`- (1x) tst_decode.v`
15			`- (1x) op_decode.v`
16			`- (1x) pc_ring.v`
17
18			`Notes:`
19			`- 8 stage pipeline consisting of several storage rings.`
20
21			`--------------------------------------------------------------------------------`
22			`*/`
23
24			`module control_ring`
25			`#(`
26			`parameter integer DATA_W = 32, // data width`
27			`parameter integer ADDR_W = 16, // address width`
28			`parameter integer THREADS = 8, // threads`
29			`parameter integer THRD_W = 3, // thread width`
30			`parameter integer STACKS = 8, // number of stacks`
31			`parameter integer STK_W = 3, // stack selector width`
32			`parameter integer IM_W = 6, // immediate width`
33			`parameter integer MEM_DATA_W = 16, // opcode width`
34			`parameter integer LG_SEL_W = 4, // logical operation width`
35			`parameter [ADDR_W-1:0] CLR_BASE = 'h0, // clear address base (concat)`
36			`parameter integer CLR_SPAN = 2, // clear address span (2^n)`
37			`parameter [ADDR_W-1:0] INTR_BASE = 'h20, // interrupt address base (concat)`
38			`parameter integer INTR_SPAN = 2 // interrupt address span (2^n)`
39			`)`
40			`(`
41			`// clocks & resets`
42			`input wire clk_i, // clock`
43			`input wire rst_i, // async. reset, active high`
44			`// control I/O`
45			`input wire [THREADS-1:0] clr_req_i, // clear request, active high`
46			`output wire [THREADS-1:0] clr_ack_o, // clear ack, active high until serviced`
47			`input wire [THREADS-1:0] intr_en_i, // interrupt enable, active high`
48			`input wire [THREADS-1:0] intr_req_i, // interrupt request, active high`
49			`output wire [THREADS-1:0] intr_ack_o, // interrupt ack, active high until serviced`
50			`input wire [MEM_DATA_W-1:0] op_code_i, // opcode`
51			`output wire op_code_er_o, // 1=illegal op code encountered`
52			`// ALU I/O`
53			`input wire [ADDR_W-1:0] b_addr_i, // b \| im`
54			`output wire [IM_W-1:0] im_o, // immediate`
55			`output wire [STK_W-1:0] data_sel_a_o, // stack selector`
56			`output wire [STK_W-1:0] data_sel_b_o, // stack selector`
57			`output wire [STK_W-1:0] addr_sel_b_o, // b stack selector`
58			`output wire imda_o, // 1=immediate data`
59			`output wire imad_o, // 1=immediate address`
60			`output wire sgn_o, // 1=signed`
61			`output wire ext_o, // 1=extended`
62			`output wire hgh_o, // 1=high`
63			`output wire [LG_SEL_W-1:0] lg_sel_o, // see decode in notes`
64			`output wire add_o, // 1=add`
65			`output wire sub_o, // 1=subtract`
66			`output wire mul_o, // 1=multiply`
67			`output wire shl_o, // 1=shift left`
68			`output wire pow_o, // 1=power of 2`
69			`output wire rtn_o, // 1=return pc`
70			`output wire lit_o, // 1=literal data`
71			`output wire dm_rd_o, // 1=read`
72			`output wire dm_wr_o, // 1=write`
73			`output wire rg_rd_o, // 1=read`
74			`output wire rg_wr_o, // 1=write`
75			`// stack I/O`
76			`output wire stk_clr_o, // stacks clear`
77			`output wire [STACKS-1:0] pop_o, // stacks pop`
78			`output wire [STACKS-1:0] push_o, // stacks push`
79			`// flags`
80			`input wire flg_nz_2_i, // a != 0`
81			`input wire flg_lz_2_i, // a < 0`
82			`input wire flg_ne_2_i, // a != b`
83			`input wire flg_lt_2_i, // a < b`
84			`// threads`
85			`output wire [THRD_W-1:0] thrd_0_o,`
86			`output wire [THRD_W-1:0] thrd_2_o,`
87			`output wire [THRD_W-1:0] thrd_3_o,`
88			`output wire [THRD_W-1:0] thrd_6_o,`
89			`// addresses`
90			`output wire [ADDR_W-1:0] pc_1_o,`
91			`output wire [ADDR_W-1:0] pc_3_o,`
92			`output wire [ADDR_W-1:0] pc_4_o`
93			`);`
94
95
96
97			`/*`
98			`----------------------`
99			`-- internal signals --`
100			`----------------------`
101			`*/`
102			`localparam integer TST_W = 4;`
103			`//`
104			`wire pc_clr, cnd, zro, jmp, gto, intr, res_tst_3;`
105			`wire stk_clr;`
106			`wire [STACKS-1:0] pop, push;`
107			`wire [TST_W-1:0] tst;`
108			`wire thrd_clr, thrd_intr;`
109			`wire [THRD_W-1:0] thrd_4, thrd_5;`
110
111
112
113			`/*`
114			`================`
115			`== code start ==`
116			`================`
117			`*/`
118
119
120			`// establish threads`
121			`thread_ring`
122			`#(`
123			`.THREADS ( THREADS ),`
124			`.THRD_W ( THRD_W )`
125			`)`
126			`thread_ring`
127			`(`
128			`.clk_i ( clk_i ),`
129			`.rst_i ( rst_i ),`
130			`.thrd_0_o ( thrd_0_o ),`
131			`.thrd_1_o ( ),`
132			`.thrd_2_o ( thrd_2_o ),`
133			`.thrd_3_o ( thrd_3_o ),`
134			`.thrd_4_o ( thrd_4 ),`
135			`.thrd_5_o ( thrd_5 ),`
136			`.thrd_6_o ( thrd_6_o ),`
137			`.thrd_7_o ( )`
138			`);`
139
140
141			`// handle external thread clear requests`
142			`event_ctrl`
143			`#(`
144			`.REGS_REQ ( 0 ), // don't resync`
145			`.EDGE_REQ ( 1 ), // edge sensitive`
146			`.RESET_VAL ( { THREADS{ 1'b1 } } ), // clear threads @ power-up`
147			`.THREADS ( THREADS ),`
148			`.THRD_W ( THRD_W )`
149			`)`
150			`clr_event_ctrl`
151			`(`
152			`.clk_i ( clk_i ),`
153			`.rst_i ( rst_i ),`
154			`.thrd_i ( thrd_5 ),`
155			`.en_i ( { THREADS{ 1'b1 } } ), // always enable`
156			`.req_i ( clr_req_i ),`
157			`.ack_o ( clr_ack_o ),`
158			`.event_o ( thrd_clr )`
159			`);`
160
161
162			`// handle external thread interrupt requests`
163			`event_ctrl`
164			`#(`
165			`.REGS_REQ ( 2 ), // resync`
166			`.EDGE_REQ ( 1 ), // edge sensitive`
167			`.RESET_VAL ( 0 ),`
168			`.THREADS ( THREADS ),`
169			`.THRD_W ( THRD_W )`
170			`)`
171			`intr_event_ctrl`
172			`(`
173			`.clk_i ( clk_i ),`
174			`.rst_i ( rst_i ),`
175			`.thrd_i ( thrd_5 ),`
176			`.en_i ( intr_en_i ),`
177			`.req_i ( intr_req_i ),`
178			`.ack_o ( intr_ack_o ),`
179			`.event_o ( thrd_intr )`
180			`);`
181
182
183			`// conditional jump etc. testing`
184			`tst_decode`
185			`#(`
186			`.REGS_TST ( 2 ),`
187			`.REGS_OUT ( 1 ),`
188			`.TST_W ( TST_W )`
189			`)`
190			`tst_decode`
191			`(`
192			`.clk_i ( clk_i ),`
193			`.rst_i ( rst_i ),`
194			`.flg_nz_i ( flg_nz_2_i ),`
195			`.flg_lz_i ( flg_lz_2_i ),`
196			`.flg_ne_i ( flg_ne_2_i ),`
197			`.flg_lt_i ( flg_lt_2_i ),`
198			`.cnd_i ( cnd ),`
199			`.tst_i ( tst ),`
200			`.result_o ( res_tst_3 )`
201			`);`
202
203
204			`// op_code decoding`
205			`op_decode`
206			`#(`
207			`.REGS_IN ( 0 ),`
208			`.REGS_OUT ( 1 ),`
209			`.STACKS ( STACKS ),`
210			`.STK_W ( STK_W ),`
211			`.DATA_W ( DATA_W ),`
212			`.IM_W ( IM_W ),`
213			`.MEM_DATA_W ( MEM_DATA_W ),`
214			`.LG_SEL_W ( LG_SEL_W ),`
215			`.TST_W ( TST_W )`
216			`)`
217			`op_decode`
218			`(`
219			`.clk_i ( clk_i ),`
220			`.rst_i ( rst_i ),`
221			`.thrd_clr_i ( thrd_clr ),`
222			`.thrd_intr_i ( thrd_intr ),`
223			`.op_code_i ( op_code_i ),`
224			`.op_code_er_o ( op_code_er_o ),`
225			`.im_o ( im_o ),`
226			`.pc_clr_o ( pc_clr ),`
227			`.cnd_o ( cnd ),`
228			`.lit_o ( lit_o ),`
229			`.jmp_o ( jmp ),`
230			`.gto_o ( gto ),`
231			`.intr_o ( intr ),`
232			`.tst_o ( tst ),`
233			`.stk_clr_o ( stk_clr_o ),`
234			`.pop_o ( pop_o ),`
235			`.push_o ( push_o ),`
236			`.data_sel_a_o ( data_sel_a_o ),`
237			`.data_sel_b_o ( data_sel_b_o ),`
238			`.addr_sel_b_o ( addr_sel_b_o ),`
239			`.imda_o ( imda_o ),`
240			`.imad_o ( imad_o ),`
241			`.sgn_o ( sgn_o ),`
242			`.ext_o ( ext_o ),`
243			`.hgh_o ( hgh_o ),`
244			`.lg_sel_o ( lg_sel_o ),`
245			`.add_o ( add_o ),`
246			`.sub_o ( sub_o ),`
247			`.mul_o ( mul_o ),`
248			`.shl_o ( shl_o ),`
249			`.pow_o ( pow_o ),`
250			`.rtn_o ( rtn_o ),`
251			`.dm_rd_o ( dm_rd_o ),`
252			`.dm_wr_o ( dm_wr_o ),`
253			`.rg_rd_o ( rg_rd_o ),`
254			`.rg_wr_o ( rg_wr_o )`
255			`);`
256
257
258			`// pc generation & storage`
259			`pc_ring`
260			`#(`
261			`.THREADS ( THREADS ),`
262			`.THRD_W ( THRD_W ),`
263			`.DATA_W ( DATA_W ),`
264			`.ADDR_W ( ADDR_W ),`
265			`.CLR_BASE ( CLR_BASE ),`
266			`.CLR_SPAN ( CLR_SPAN ),`
267			`.INTR_BASE ( INTR_BASE ),`
268			`.INTR_SPAN ( INTR_SPAN )`
269			`)`
270			`pc_ring`
271			`(`
272			`.clk_i ( clk_i ),`
273			`.rst_i ( rst_i ),`
274			`.thrd_0_i ( thrd_0_o ),`
275			`.thrd_4_i ( thrd_4 ),`
276			`.clr_i ( pc_clr ),`
277			`.lit_i ( lit_o ),`
278			`.jmp_i ( jmp ),`
279			`.gto_i ( gto ),`
280			`.intr_i ( intr ),`
281			`.res_tst_3_i ( res_tst_3 ),`
282			`.b_addr_i ( b_addr_i ),`
283			`.pc_0_o ( ),`
284			`.pc_1_o ( pc_1_o ),`
285			`.pc_2_o ( ),`
286			`.pc_3_o ( pc_3_o ),`
287			`.pc_4_o ( pc_4_o ),`
288			`.pc_5_o ( ),`
289			`.pc_6_o ( ),`
290			`.pc_7_o ( )`
291			`);`
292
293
294			`endmodule`