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[/] [hive/] [trunk/] [v04.05/] [data_ring.v] - Blame information for rev 4

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/*
--------------------------------------------------------------------------------
 
Module : data_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor data path & data stacks.
 
Instantiates:
- (1x) stacks_mux.v
- (1x) alu_top.v
- (1x) pointer_ring.v
- (8x) dq_ram_infer.v
 
Notes:
- 8 stage data pipeline beginning and ending on 8 BRAM based LIFOs.
 
--------------------------------------------------------------------------------
*/
 
module data_ring
        #(
        parameter       integer                                                 DATA_W                  = 32,           // data width
        parameter       integer                                                 ADDR_W                  = 16,           // address width
        parameter       integer                                                 THREADS                 = 8,            // threads
        parameter       integer                                                 THRD_W                  = 3,            // thread selector width
        parameter       integer                                                 STACKS                  = 8,            // stacks
        parameter       integer                                                 STK_W                           = 3,            // stack selector width
        parameter       integer                                                 PNTR_W                  = 5,            // stack pointer width
        parameter       integer                                                 IM_W                            = 6,            // immediate width
        parameter       integer                                                 LG_SEL_W                        = 4,            // operation width
        parameter       integer                                                 PROT_POP                        = 1,            // 1=error protection, 0=none
        parameter       integer                                                 PROT_PUSH               = 1             // 1=error protection, 0=none
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire    [STK_W-1:0]                              data_sel_a_i,                           // stack selector
        input                   wire    [STK_W-1:0]                              data_sel_b_i,                           // stack selector
        input                   wire    [STK_W-1:0]                              addr_sel_b_i,                           // stack selector
        input                   wire                                                            imda_i,                                         // 1=immediate data
        input                   wire                                                            imad_i,                                         // 1=immediate address
        input                   wire                                                            sgn_i,                                          // 1=signed
        input                   wire                                                            ext_i,                                          // 1=extended result
        input                   wire                                                            hgh_i,                                          // 1=high
        input                   wire    [LG_SEL_W-1:0]                   lg_sel_i,                                       // logic operation (see lg_sel_encode.h)
        input                   wire                                                            add_i,                                          // 1=add
        input                   wire                                                            sub_i,                                          // 1=subtract
        input                   wire                                                            mul_i,                                          // 1=multiply
        input                   wire                                                            shl_i,                                          // 1=shift left
        input                   wire                                                            pow_i,                                          // 1=power of 2
        input                   wire                                                            rtn_i,                                          // 1=return pc
        input                   wire                                                            dm_rd_i,                                                // 1=read
        input                   wire                                                            rg_rd_i,                                                // 1=read
        // stack I/O
        input                   wire                                                            stk_clr_i,                                      // stacks clear
        input                   wire    [STACKS-1:0]                     pop_i,                                          // stacks pop
        input                   wire    [STACKS-1:0]                     push_i,                                         // stacks push
        input                   wire    [THRD_W-1:0]                     thrd_6_i,                                       // thread
        // data I/O
        input                   wire    [IM_W-1:0]                               im_i,                                                   // immediate
        input                   wire    [DATA_W/2-1:0]                   dm_rd_data_4_i,                 // dmem read data
        input                   wire    [DATA_W/2-1:0]                   rg_rd_data_4_i,                 // regs read data
        input                   wire    [ADDR_W-1:0]                     pc_3_i,                                         // program counter
        output          wire    [DATA_W-1:0]                     a_data_o,                                       // a
        output          wire    [ADDR_W-1:0]                     b_addr_o,                                       // b 
        // flags
        output          wire                                                            flg_nz_2_o,                                     //      a != 0
        output          wire                                                            flg_lz_2_o,                                     //      a < 0
        output          wire                                                            flg_ne_2_o,                                     //      a != b
        output          wire                                                            flg_lt_2_o,                                     //      a < b
        // errors
        output          wire    [STACKS-1:0]                     pop_er_2_o,                                     // pop when empty, active high 
        output          wire    [STACKS-1:0]                     push_er_3_o                                     // push when full, active high
        );
 
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        wire                                    [DATA_W-1:0]                     b_data;
        wire                                    [DATA_W-1:0]                     pop_data0, pop_data1, pop_data2, pop_data3, pop_data4, pop_data5, pop_data6, pop_data7, push_data_6;
        wire                                    [PNTR_W-1:0]                     pntr0_6, pntr1_6, pntr2_6, pntr3_6, pntr4_6, pntr5_6, pntr6_6, pntr7_6;
        wire                                    [STACKS-1:0]                     stk_wr_6;
 
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
 
        // stacks output mux
        stacks_mux
        #(
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .IM_W                           ( IM_W ),
        .STK_W                  ( STK_W )
        )
        stacks_mux
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .data_sel_a_i   ( data_sel_a_i ),
        .data_sel_b_i   ( data_sel_b_i ),
        .addr_sel_b_i   ( addr_sel_b_i ),
        .imda_i                 ( imda_i ),
        .imad_i                 ( imad_i ),
        .pop_data0_i    ( pop_data0 ),
        .pop_data1_i    ( pop_data1 ),
        .pop_data2_i    ( pop_data2 ),
        .pop_data3_i    ( pop_data3 ),
        .pop_data4_i    ( pop_data4 ),
        .pop_data5_i    ( pop_data5 ),
        .pop_data6_i    ( pop_data6 ),
        .pop_data7_i    ( pop_data7 ),
        .im_i                           ( im_i ),
        .a_data_o               ( a_data_o ),
        .b_data_o               ( b_data ),
        .b_addr_o               ( b_addr_o )
        );
 
 
        // ALU
        alu_top
        #(
        .DATA_W                         ( DATA_W ),
        .ADDR_W                         ( ADDR_W ),
        .LG_SEL_W                       ( LG_SEL_W )
        )
        alu_top
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .sgn_i                          ( sgn_i ),
        .ext_i                          ( ext_i ),
        .hgh_i                          ( hgh_i ),
        .lg_sel_i                       ( lg_sel_i ),
        .add_i                          ( add_i ),
        .sub_i                          ( sub_i ),
        .mul_i                          ( mul_i ),
        .shl_i                          ( shl_i ),
        .pow_i                          ( pow_i ),
        .rtn_i                          ( rtn_i ),
        .dm_rd_i                                ( dm_rd_i ),
        .rg_rd_i                                ( rg_rd_i ),
        .a_i                                    ( a_data_o ),
        .b_i                                    ( b_data ),
        .dm_rd_data_4_i ( dm_rd_data_4_i ),
        .rg_rd_data_4_i ( rg_rd_data_4_i ),
        .pc_3_i                         ( pc_3_i ),
        .result_6_o                     ( push_data_6 ),
        .flg_nz_2_o                     ( flg_nz_2_o ),
        .flg_lz_2_o                     ( flg_lz_2_o ),
        .flg_ne_2_o                     ( flg_ne_2_o ),
        .flg_lt_2_o                     ( flg_lt_2_o )
        );
 
 
        // stack pointer generation & storage
        pointer_ring
        #(
        .THREADS                        ( THREADS ),
        .STACKS                 ( STACKS ),
        .PNTR_W                 ( PNTR_W ),
        .PROT_POP               ( PROT_POP ),
        .PROT_PUSH              ( PROT_PUSH )
        )
        pointer_ring
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .clr_i                  ( stk_clr_i ),
        .pop_i                  ( pop_i ),
        .push_i                 ( push_i ),
        .pntr0_6_o              ( pntr0_6 ),
        .pntr1_6_o              ( pntr1_6 ),
        .pntr2_6_o              ( pntr2_6 ),
        .pntr3_6_o              ( pntr3_6 ),
        .pntr4_6_o              ( pntr4_6 ),
        .pntr5_6_o              ( pntr5_6 ),
        .pntr6_6_o              ( pntr6_6 ),
        .pntr7_6_o              ( pntr7_6 ),
        .wr_6_o                 ( stk_wr_6 ),
        .pop_er_2_o             ( pop_er_2_o ),
        .push_er_3_o    ( push_er_3_o )
        );
 
 
        // LIFO stacks memory
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .MODE                   ( "RAW" )
        )
        stack0_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr0_6 } ),
        .wr_i                           ( stk_wr_6[0] ),
        .data_i                 ( push_data_6 ),
        .data_o                 ( pop_data0 )
        );
 
 
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .MODE                   ( "RAW" )
        )
        stack1_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr1_6 } ),
        .wr_i                           ( stk_wr_6[1] ),
        .data_i                 ( push_data_6 ),
        .data_o                 ( pop_data1 )
        );
 
 
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .MODE                   ( "RAW" )
        )
        stack2_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr2_6 } ),
        .wr_i                           ( stk_wr_6[2] ),
        .data_i                 ( push_data_6 ),
        .data_o                 ( pop_data2 )
        );
 
 
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .MODE                   ( "RAW" )
        )
        stack3_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr3_6 } ),
        .wr_i                           ( stk_wr_6[3] ),
        .data_i                 ( push_data_6 ),
        .data_o                 ( pop_data3 )
        );
 
 
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .MODE                   ( "RAW" )
        )
        stack4_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr4_6 } ),
        .wr_i                           ( stk_wr_6[4] ),
        .data_i                 ( push_data_6 ),
        .data_o                 ( pop_data4 )
        );
 
 
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .MODE                   ( "RAW" )
        )
        stack5_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr5_6 } ),
        .wr_i                           ( stk_wr_6[5] ),
        .data_i                 ( push_data_6 ),
        .data_o                 ( pop_data5 )
        );
 
 
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .MODE                   ( "RAW" )
        )
        stack6_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr6_6 } ),
        .wr_i                           ( stk_wr_6[6] ),
        .data_i                 ( push_data_6 ),
        .data_o                 ( pop_data6 )
        );
 
 
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .MODE                   ( "RAW" )
        )
        stack7_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr7_6 } ),
        .wr_i                           ( stk_wr_6[7] ),
        .data_i                 ( push_data_6 ),
        .data_o                 ( pop_data7 )
        );
 
 
endmodule

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[/] [hive/] [trunk/] [v04.05/] [data_ring.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : data_ring.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Processor data path & data stacks.`
10
11			`Instantiates:`
12			`- (1x) stacks_mux.v`
13			`- (1x) alu_top.v`
14			`- (1x) pointer_ring.v`
15			`- (8x) dq_ram_infer.v`
16
17			`Notes:`
18			`- 8 stage data pipeline beginning and ending on 8 BRAM based LIFOs.`
19
20			`--------------------------------------------------------------------------------`
21			`*/`
22
23			`module data_ring`
24			`#(`
25			`parameter integer DATA_W = 32, // data width`
26			`parameter integer ADDR_W = 16, // address width`
27			`parameter integer THREADS = 8, // threads`
28			`parameter integer THRD_W = 3, // thread selector width`
29			`parameter integer STACKS = 8, // stacks`
30			`parameter integer STK_W = 3, // stack selector width`
31			`parameter integer PNTR_W = 5, // stack pointer width`
32			`parameter integer IM_W = 6, // immediate width`
33			`parameter integer LG_SEL_W = 4, // operation width`
34			`parameter integer PROT_POP = 1, // 1=error protection, 0=none`
35			`parameter integer PROT_PUSH = 1 // 1=error protection, 0=none`
36			`)`
37			`(`
38			`// clocks & resets`
39			`input wire clk_i, // clock`
40			`input wire rst_i, // async. reset, active high`
41			`// control I/O`
42			`input wire [STK_W-1:0] data_sel_a_i, // stack selector`
43			`input wire [STK_W-1:0] data_sel_b_i, // stack selector`
44			`input wire [STK_W-1:0] addr_sel_b_i, // stack selector`
45			`input wire imda_i, // 1=immediate data`
46			`input wire imad_i, // 1=immediate address`
47			`input wire sgn_i, // 1=signed`
48			`input wire ext_i, // 1=extended result`
49			`input wire hgh_i, // 1=high`
50			`input wire [LG_SEL_W-1:0] lg_sel_i, // logic operation (see lg_sel_encode.h)`
51			`input wire add_i, // 1=add`
52			`input wire sub_i, // 1=subtract`
53			`input wire mul_i, // 1=multiply`
54			`input wire shl_i, // 1=shift left`
55			`input wire pow_i, // 1=power of 2`
56			`input wire rtn_i, // 1=return pc`
57			`input wire dm_rd_i, // 1=read`
58			`input wire rg_rd_i, // 1=read`
59			`// stack I/O`
60			`input wire stk_clr_i, // stacks clear`
61			`input wire [STACKS-1:0] pop_i, // stacks pop`
62			`input wire [STACKS-1:0] push_i, // stacks push`
63			`input wire [THRD_W-1:0] thrd_6_i, // thread`
64			`// data I/O`
65			`input wire [IM_W-1:0] im_i, // immediate`
66			`input wire [DATA_W/2-1:0] dm_rd_data_4_i, // dmem read data`
67			`input wire [DATA_W/2-1:0] rg_rd_data_4_i, // regs read data`
68			`input wire [ADDR_W-1:0] pc_3_i, // program counter`
69			`output wire [DATA_W-1:0] a_data_o, // a`
70			`output wire [ADDR_W-1:0] b_addr_o, // b`
71			`// flags`
72			`output wire flg_nz_2_o, // a != 0`
73			`output wire flg_lz_2_o, // a < 0`
74			`output wire flg_ne_2_o, // a != b`
75			`output wire flg_lt_2_o, // a < b`
76			`// errors`
77			`output wire [STACKS-1:0] pop_er_2_o, // pop when empty, active high`
78			`output wire [STACKS-1:0] push_er_3_o // push when full, active high`
79			`);`
80
81
82
83			`/*`
84			`----------------------`
85			`-- internal signals --`
86			`----------------------`
87			`*/`
88			`wire [DATA_W-1:0] b_data;`
89			`wire [DATA_W-1:0] pop_data0, pop_data1, pop_data2, pop_data3, pop_data4, pop_data5, pop_data6, pop_data7, push_data_6;`
90			`wire [PNTR_W-1:0] pntr0_6, pntr1_6, pntr2_6, pntr3_6, pntr4_6, pntr5_6, pntr6_6, pntr7_6;`
91			`wire [STACKS-1:0] stk_wr_6;`
92
93
94
95			`/*`
96			`================`
97			`== code start ==`
98			`================`
99			`*/`
100
101
102
103			`// stacks output mux`
104			`stacks_mux`
105			`#(`
106			`.DATA_W ( DATA_W ),`
107			`.ADDR_W ( ADDR_W ),`
108			`.IM_W ( IM_W ),`
109			`.STK_W ( STK_W )`
110			`)`
111			`stacks_mux`
112			`(`
113			`.clk_i ( clk_i ),`
114			`.rst_i ( rst_i ),`
115			`.data_sel_a_i ( data_sel_a_i ),`
116			`.data_sel_b_i ( data_sel_b_i ),`
117			`.addr_sel_b_i ( addr_sel_b_i ),`
118			`.imda_i ( imda_i ),`
119			`.imad_i ( imad_i ),`
120			`.pop_data0_i ( pop_data0 ),`
121			`.pop_data1_i ( pop_data1 ),`
122			`.pop_data2_i ( pop_data2 ),`
123			`.pop_data3_i ( pop_data3 ),`
124			`.pop_data4_i ( pop_data4 ),`
125			`.pop_data5_i ( pop_data5 ),`
126			`.pop_data6_i ( pop_data6 ),`
127			`.pop_data7_i ( pop_data7 ),`
128			`.im_i ( im_i ),`
129			`.a_data_o ( a_data_o ),`
130			`.b_data_o ( b_data ),`
131			`.b_addr_o ( b_addr_o )`
132			`);`
133
134
135			`// ALU`
136			`alu_top`
137			`#(`
138			`.DATA_W ( DATA_W ),`
139			`.ADDR_W ( ADDR_W ),`
140			`.LG_SEL_W ( LG_SEL_W )`
141			`)`
142			`alu_top`
143			`(`
144			`.clk_i ( clk_i ),`
145			`.rst_i ( rst_i ),`
146			`.sgn_i ( sgn_i ),`
147			`.ext_i ( ext_i ),`
148			`.hgh_i ( hgh_i ),`
149			`.lg_sel_i ( lg_sel_i ),`
150			`.add_i ( add_i ),`
151			`.sub_i ( sub_i ),`
152			`.mul_i ( mul_i ),`
153			`.shl_i ( shl_i ),`
154			`.pow_i ( pow_i ),`
155			`.rtn_i ( rtn_i ),`
156			`.dm_rd_i ( dm_rd_i ),`
157			`.rg_rd_i ( rg_rd_i ),`
158			`.a_i ( a_data_o ),`
159			`.b_i ( b_data ),`
160			`.dm_rd_data_4_i ( dm_rd_data_4_i ),`
161			`.rg_rd_data_4_i ( rg_rd_data_4_i ),`
162			`.pc_3_i ( pc_3_i ),`
163			`.result_6_o ( push_data_6 ),`
164			`.flg_nz_2_o ( flg_nz_2_o ),`
165			`.flg_lz_2_o ( flg_lz_2_o ),`
166			`.flg_ne_2_o ( flg_ne_2_o ),`
167			`.flg_lt_2_o ( flg_lt_2_o )`
168			`);`
169
170
171			`// stack pointer generation & storage`
172			`pointer_ring`
173			`#(`
174			`.THREADS ( THREADS ),`
175			`.STACKS ( STACKS ),`
176			`.PNTR_W ( PNTR_W ),`
177			`.PROT_POP ( PROT_POP ),`
178			`.PROT_PUSH ( PROT_PUSH )`
179			`)`
180			`pointer_ring`
181			`(`
182			`.clk_i ( clk_i ),`
183			`.rst_i ( rst_i ),`
184			`.clr_i ( stk_clr_i ),`
185			`.pop_i ( pop_i ),`
186			`.push_i ( push_i ),`
187			`.pntr0_6_o ( pntr0_6 ),`
188			`.pntr1_6_o ( pntr1_6 ),`
189			`.pntr2_6_o ( pntr2_6 ),`
190			`.pntr3_6_o ( pntr3_6 ),`
191			`.pntr4_6_o ( pntr4_6 ),`
192			`.pntr5_6_o ( pntr5_6 ),`
193			`.pntr6_6_o ( pntr6_6 ),`
194			`.pntr7_6_o ( pntr7_6 ),`
195			`.wr_6_o ( stk_wr_6 ),`
196			`.pop_er_2_o ( pop_er_2_o ),`
197			`.push_er_3_o ( push_er_3_o )`
198			`);`
199
200
201			`// LIFO stacks memory`
202			`dq_ram_infer`
203			`#(`
204			`.REG_OUT ( 1 ),`
205			`.DATA_W ( DATA_W ),`
206			`.ADDR_W ( THRD_W+PNTR_W ),`
207			`.MODE ( "RAW" )`
208			`)`
209			`stack0_dq_ram`
210			`(`
211			`.clk_i ( clk_i ),`
212			`.addr_i ( { thrd_6_i, pntr0_6 } ),`
213			`.wr_i ( stk_wr_6[0] ),`
214			`.data_i ( push_data_6 ),`
215			`.data_o ( pop_data0 )`
216			`);`
217
218
219			`dq_ram_infer`
220			`#(`
221			`.REG_OUT ( 1 ),`
222			`.DATA_W ( DATA_W ),`
223			`.ADDR_W ( THRD_W+PNTR_W ),`
224			`.MODE ( "RAW" )`
225			`)`
226			`stack1_dq_ram`
227			`(`
228			`.clk_i ( clk_i ),`
229			`.addr_i ( { thrd_6_i, pntr1_6 } ),`
230			`.wr_i ( stk_wr_6[1] ),`
231			`.data_i ( push_data_6 ),`
232			`.data_o ( pop_data1 )`
233			`);`
234
235
236			`dq_ram_infer`
237			`#(`
238			`.REG_OUT ( 1 ),`
239			`.DATA_W ( DATA_W ),`
240			`.ADDR_W ( THRD_W+PNTR_W ),`
241			`.MODE ( "RAW" )`
242			`)`
243			`stack2_dq_ram`
244			`(`
245			`.clk_i ( clk_i ),`
246			`.addr_i ( { thrd_6_i, pntr2_6 } ),`
247			`.wr_i ( stk_wr_6[2] ),`
248			`.data_i ( push_data_6 ),`
249			`.data_o ( pop_data2 )`
250			`);`
251
252
253			`dq_ram_infer`
254			`#(`
255			`.REG_OUT ( 1 ),`
256			`.DATA_W ( DATA_W ),`
257			`.ADDR_W ( THRD_W+PNTR_W ),`
258			`.MODE ( "RAW" )`
259			`)`
260			`stack3_dq_ram`
261			`(`
262			`.clk_i ( clk_i ),`
263			`.addr_i ( { thrd_6_i, pntr3_6 } ),`
264			`.wr_i ( stk_wr_6[3] ),`
265			`.data_i ( push_data_6 ),`
266			`.data_o ( pop_data3 )`
267			`);`
268
269
270			`dq_ram_infer`
271			`#(`
272			`.REG_OUT ( 1 ),`
273			`.DATA_W ( DATA_W ),`
274			`.ADDR_W ( THRD_W+PNTR_W ),`
275			`.MODE ( "RAW" )`
276			`)`
277			`stack4_dq_ram`
278			`(`
279			`.clk_i ( clk_i ),`
280			`.addr_i ( { thrd_6_i, pntr4_6 } ),`
281			`.wr_i ( stk_wr_6[4] ),`
282			`.data_i ( push_data_6 ),`
283			`.data_o ( pop_data4 )`
284			`);`
285
286
287			`dq_ram_infer`
288			`#(`
289			`.REG_OUT ( 1 ),`
290			`.DATA_W ( DATA_W ),`
291			`.ADDR_W ( THRD_W+PNTR_W ),`
292			`.MODE ( "RAW" )`
293			`)`
294			`stack5_dq_ram`
295			`(`
296			`.clk_i ( clk_i ),`
297			`.addr_i ( { thrd_6_i, pntr5_6 } ),`
298			`.wr_i ( stk_wr_6[5] ),`
299			`.data_i ( push_data_6 ),`
300			`.data_o ( pop_data5 )`
301			`);`
302
303
304			`dq_ram_infer`
305			`#(`
306			`.REG_OUT ( 1 ),`
307			`.DATA_W ( DATA_W ),`
308			`.ADDR_W ( THRD_W+PNTR_W ),`
309			`.MODE ( "RAW" )`
310			`)`
311			`stack6_dq_ram`
312			`(`
313			`.clk_i ( clk_i ),`
314			`.addr_i ( { thrd_6_i, pntr6_6 } ),`
315			`.wr_i ( stk_wr_6[6] ),`
316			`.data_i ( push_data_6 ),`
317			`.data_o ( pop_data6 )`
318			`);`
319
320
321			`dq_ram_infer`
322			`#(`
323			`.REG_OUT ( 1 ),`
324			`.DATA_W ( DATA_W ),`
325			`.ADDR_W ( THRD_W+PNTR_W ),`
326			`.MODE ( "RAW" )`
327			`)`
328			`stack7_dq_ram`
329			`(`
330			`.clk_i ( clk_i ),`
331			`.addr_i ( { thrd_6_i, pntr7_6 } ),`
332			`.wr_i ( stk_wr_6[7] ),`
333			`.data_i ( push_data_6 ),`
334			`.data_o ( pop_data7 )`
335			`);`
336
337
338			`endmodule`