Subversion Repositories hive

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2010 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II

# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition

# Date created = 09:56:16  September 30, 2013

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               hive_core_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone III"

set_global_assignment -name DEVICE EP3C5E144C8

set_global_assignment -name TOP_LEVEL_ENTITY hive_core

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:56:16  SEPTEMBER 30, 2013"

set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"

set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"

set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

set_global_assignment -name VECTOR_WAVEFORM_FILE hive_core.vwf

set_global_assignment -name SIMULATION_MODE FUNCTIONAL

set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE hive_core.vwf

set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

set_global_assignment -name MAX_RAM_BLOCKS_M4K 24

set_global_assignment -name SEED 2

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF

set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED

set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA

set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON

set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON

set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top