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[/] [hive/] [trunk/] [v04.05/] [reg_mem_shim.v] - Blame information for rev 4

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/*
--------------------------------------------------------------------------------
 
Module: reg_mem_shim.v
 
Function:
- Shim for internal register set and main memory r/w accesses.
 
Instantiates:
- (6x) pipe.v
 
Notes:
- I/O registered.
 
--------------------------------------------------------------------------------
*/
 
module reg_mem_shim
        #(
        parameter       integer                                                 DATA_W                  = 32,           // data width (bits)
        parameter       integer                                                 ADDR_W                  = 16,           // address width (bits)
        parameter       integer                                                 IM_W                            = 8             // immediate width
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire                                                            hgh_i,                                          // 1=high
        input                   wire                                                            lit_i,                                          // 1=literal data
        //
        input                   wire                                                            dm_wr_i,                                                // 1=write
        input                   wire                                                            rg_rd_i,                                                // 1=read
        input                   wire                                                            rg_wr_i,                                                // 1=write
        //
        output          wire                                                            dm_wr_o,                                                // 1=write
        output          wire                                                            rg_rd_o,                                                // 1=read
        output          wire                                                            rg_wr_o,                                                // 1=write
        // data I/O
        input                   wire    [DATA_W-1:0]                     a_data_i,                                       // operand
        output          wire    [DATA_W/2-1:0]                   wr_data_o,                                      // write data
        // address I/O
        input                   wire    [ADDR_W-1:0]                     b_addr_i,                                       // b
        input                   wire    [IM_W-1:0]                               im_i,                                                   // immediate
        input                   wire    [ADDR_W-1:0]                     pc_1_i,                                         // program counter
        output          wire    [ADDR_W-1:0]                     rg_addr_o,                                      // address
        output          wire    [ADDR_W-1:0]                     dm_addr_o                                       // address
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        wire                                                                                            hgh, lit, dm_wr, rg_rd, rg_wr;
        wire                                    [ADDR_W-1:0]                     b_addr, rg_addr, dm_addr;
        wire                                    [IM_W-1:0]                               im;
        wire                                    [DATA_W-1:0]                     a_data, wr_data;
 
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // input ctrl regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( 5 ),
        .RESET_VAL      ( 0 )
        )
        in_regs_ctrl
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { hgh_i, lit_i, dm_wr_i, rg_rd_i, rg_wr_i } ),
        .data_o         ( { hgh,   lit,   dm_wr,   rg_rd,   rg_wr   } )
        );
 
 
        // input addr regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( IM_W+ADDR_W ),
        .RESET_VAL      ( 0 )
        )
        in_regs_addr
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { im_i, b_addr_i } ),
        .data_o         ( { im,   b_addr   } )
        );
 
 
        // input data regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( DATA_W ),
        .RESET_VAL      ( 0 )
        )
        in_regs_data
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( a_data_i ),
        .data_o         ( a_data   )
        );
 
 
        // decode write data
        assign wr_data = ( hgh ) ? a_data[DATA_W-1:DATA_W/2] : a_data[DATA_W/2-1:0];
 
        // decode address
        assign rg_addr = b_addr;
        assign dm_addr = ( lit ) ? pc_1_i : b_addr + im;
 
 
        // output ctrl regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( 3 ),
        .RESET_VAL      ( 0 )
        )
        out_regs_ctrl
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { dm_wr,   rg_rd,   rg_wr   } ),
        .data_o         ( { dm_wr_o, rg_rd_o, rg_wr_o } )
        );
 
 
        // output addr regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( ADDR_W+ADDR_W ),
        .RESET_VAL      ( 0 )
        )
        out_regs_addr
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { rg_addr,   dm_addr   } ),
        .data_o         ( { rg_addr_o, dm_addr_o } )
        );
 
 
        // output data regs
        pipe
        #(
        .DEPTH          ( 1 ),
        .WIDTH          ( DATA_W/2 ),
        .RESET_VAL      ( 0 )
        )
        out_regs_data
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( wr_data   ),
        .data_o         ( wr_data_o )
        );
 
 
endmodule

Line No.	Rev	Author	Line
1	4	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module: reg_mem_shim.v`
5
6			`Function:`
7			`- Shim for internal register set and main memory r/w accesses.`
8
9			`Instantiates:`
10			`- (6x) pipe.v`
11
12			`Notes:`
13			`- I/O registered.`
14
15			`--------------------------------------------------------------------------------`
16			`*/`
17
18			`module reg_mem_shim`
19			`#(`
20			`parameter integer DATA_W = 32, // data width (bits)`
21			`parameter integer ADDR_W = 16, // address width (bits)`
22			`parameter integer IM_W = 8 // immediate width`
23			`)`
24			`(`
25			`// clocks & resets`
26			`input wire clk_i, // clock`
27			`input wire rst_i, // async. reset, active high`
28			`// control I/O`
29			`input wire hgh_i, // 1=high`
30			`input wire lit_i, // 1=literal data`
31			`//`
32			`input wire dm_wr_i, // 1=write`
33			`input wire rg_rd_i, // 1=read`
34			`input wire rg_wr_i, // 1=write`
35			`//`
36			`output wire dm_wr_o, // 1=write`
37			`output wire rg_rd_o, // 1=read`
38			`output wire rg_wr_o, // 1=write`
39			`// data I/O`
40			`input wire [DATA_W-1:0] a_data_i, // operand`
41			`output wire [DATA_W/2-1:0] wr_data_o, // write data`
42			`// address I/O`
43			`input wire [ADDR_W-1:0] b_addr_i, // b`
44			`input wire [IM_W-1:0] im_i, // immediate`
45			`input wire [ADDR_W-1:0] pc_1_i, // program counter`
46			`output wire [ADDR_W-1:0] rg_addr_o, // address`
47			`output wire [ADDR_W-1:0] dm_addr_o // address`
48			`);`
49
50
51			`/*`
52			`----------------------`
53			`-- internal signals --`
54			`----------------------`
55			`*/`
56			`wire hgh, lit, dm_wr, rg_rd, rg_wr;`
57			`wire [ADDR_W-1:0] b_addr, rg_addr, dm_addr;`
58			`wire [IM_W-1:0] im;`
59			`wire [DATA_W-1:0] a_data, wr_data;`
60
61
62
63			`/*`
64			`================`
65			`== code start ==`
66			`================`
67			`*/`
68
69
70			`// input ctrl regs`
71			`pipe`
72			`#(`
73			`.DEPTH ( 1 ),`
74			`.WIDTH ( 5 ),`
75			`.RESET_VAL ( 0 )`
76			`)`
77			`in_regs_ctrl`
78			`(`
79			`.clk_i ( clk_i ),`
80			`.rst_i ( rst_i ),`
81			`.data_i ( { hgh_i, lit_i, dm_wr_i, rg_rd_i, rg_wr_i } ),`
82			`.data_o ( { hgh, lit, dm_wr, rg_rd, rg_wr } )`
83			`);`
84
85
86			`// input addr regs`
87			`pipe`
88			`#(`
89			`.DEPTH ( 1 ),`
90			`.WIDTH ( IM_W+ADDR_W ),`
91			`.RESET_VAL ( 0 )`
92			`)`
93			`in_regs_addr`
94			`(`
95			`.clk_i ( clk_i ),`
96			`.rst_i ( rst_i ),`
97			`.data_i ( { im_i, b_addr_i } ),`
98			`.data_o ( { im, b_addr } )`
99			`);`
100
101
102			`// input data regs`
103			`pipe`
104			`#(`
105			`.DEPTH ( 1 ),`
106			`.WIDTH ( DATA_W ),`
107			`.RESET_VAL ( 0 )`
108			`)`
109			`in_regs_data`
110			`(`
111			`.clk_i ( clk_i ),`
112			`.rst_i ( rst_i ),`
113			`.data_i ( a_data_i ),`
114			`.data_o ( a_data )`
115			`);`
116
117
118			`// decode write data`
119			`assign wr_data = ( hgh ) ? a_data[DATA_W-1:DATA_W/2] : a_data[DATA_W/2-1:0];`
120
121			`// decode address`
122			`assign rg_addr = b_addr;`
123			`assign dm_addr = ( lit ) ? pc_1_i : b_addr + im;`
124
125
126			`// output ctrl regs`
127			`pipe`
128			`#(`
129			`.DEPTH ( 1 ),`
130			`.WIDTH ( 3 ),`
131			`.RESET_VAL ( 0 )`
132			`)`
133			`out_regs_ctrl`
134			`(`
135			`.clk_i ( clk_i ),`
136			`.rst_i ( rst_i ),`
137			`.data_i ( { dm_wr, rg_rd, rg_wr } ),`
138			`.data_o ( { dm_wr_o, rg_rd_o, rg_wr_o } )`
139			`);`
140
141
142			`// output addr regs`
143			`pipe`
144			`#(`
145			`.DEPTH ( 1 ),`
146			`.WIDTH ( ADDR_W+ADDR_W ),`
147			`.RESET_VAL ( 0 )`
148			`)`
149			`out_regs_addr`
150			`(`
151			`.clk_i ( clk_i ),`
152			`.rst_i ( rst_i ),`
153			`.data_i ( { rg_addr, dm_addr } ),`
154			`.data_o ( { rg_addr_o, dm_addr_o } )`
155			`);`
156
157
158			`// output data regs`
159			`pipe`
160			`#(`
161			`.DEPTH ( 1 ),`
162			`.WIDTH ( DATA_W/2 ),`
163			`.RESET_VAL ( 0 )`
164			`)`
165			`out_regs_data`
166			`(`
167			`.clk_i ( clk_i ),`
168			`.rst_i ( rst_i ),`
169			`.data_i ( wr_data ),`
170			`.data_o ( wr_data_o )`
171			`);`
172
173
174			`endmodule`

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[/] [hive/] [trunk/] [v04.05/] [reg_mem_shim.v] - Blame information for rev 4