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ericw |
/*
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--------------------------------------------------------------------------------
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Module: reg_set.v
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Function:
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- Internal register set for a processor.
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Instantiates:
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- (8x) reg_base.v
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- (2x) pipe.v
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Notes:
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- Processor bus IN/OUT optionally registered.
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Decode:
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- 0x0 : Core version register - ver_reg
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- 0x1 : Thread ID register - thrd_id_reg
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- 0x2 : Clear register - clr_reg
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- 0x3 : Interrupt enable register - intr_en_reg
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- 0x4 : Opcode error register - op_er_reg
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- 0x5 : Stack error register - stk_er_reg
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- 0x6 - 0x7 : UNUSED
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- 0x8 : I/O low register - io_lo_reg
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- 0x9 : I/O high register - io_hi_reg
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- 0xA - 0xB : UNUSED
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- 0xC : UART RX register - uart_rx_reg
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- 0xD : UART TX register - uart_tx_reg
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- 0xE - 0xF : UNUSED
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================================================================================
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- 0x0 : Core version register - ver_reg
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--------------------------------------------------------------------------------
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bit name description
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----- ---- -----------
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7-0 ver_min[7:0] minor version info
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15-8 ver_maj[7:0] major version info
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Notes:
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- Read-only.
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- Nibbles S/B BCD (0-9; no A-F) to be easily human readable,
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and to eliminate confusion between decimal and hex here.
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- Major version changes when op_code binary decode changes (incompatibilty).
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================================================================================
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- 0x1 : Thread ID register - thrd_id_reg
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--------------------------------------------------------------------------------
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bit name description
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----- ---- -----------
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2-0 thrd_id[2:0] thread ID
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15-3 - 0000000000000
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Notes:
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- Read-only.
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- Threads can read this to discover their thread ID.
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================================================================================
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- 0x2 : Clear register - clr_reg
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--------------------------------------------------------------------------------
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bit name description
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----- ---- -----------
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7-0 clr[7:0] 0=>1 clear thread; 1=>0 no effect;
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15-8 - 00000000
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Notes:
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- Read / write.
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- Per thread clearing.
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- All bits cleared on async reset.
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================================================================================
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- 0x3 : Interrupt enable register - intr_en_reg
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--------------------------------------------------------------------------------
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bit name description
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----- ---- -----------
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7-0 intr_en[7:0] 1=thread interrupt enable; 0=disable
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15-8 - 00000000
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Notes:
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- Read / write.
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- Per thread enabling of interrupts.
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- All bits cleared on async reset.
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================================================================================
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- 0x4 : Opcode error register - op_er_reg
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--------------------------------------------------------------------------------
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bit name description
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----- ---- -----------
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7-0 op_er[7:0] 1=opcode error; 0=OK
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15-8 - 00000000
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Notes:
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- Clear on write one.
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- Per thread opcode error reporting.
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================================================================================
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- 0x5 : Stack error register - stk_er_reg
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--------------------------------------------------------------------------------
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bit name description
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----- ---- -----------
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7-0 pop_er[7:0] 1=lifo pop when empty; 0=OK
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15-8 push_er[7:0] 1=lifo push when full; 0=OK
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Notes:
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- Clear on write one.
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- Per thread LIFO stack error reporting.
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================================================================================
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- 0x6 - 0x7 : UNUSED
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================================================================================
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- 0x8 : I/O low register - io_lo_reg
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--------------------------------------------------------------------------------
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bit name description
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----- ---- -----------
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15-0 io_lo[15:0] I/O data
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Notes:
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- Separate read / write.
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- Reads of io_lo_reg freeze data in io_hi_reg, so read io_lo_reg first then
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read io_hi_reg for contiguous wide (32 bit) data reads.
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- Writes function normally.
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================================================================================
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- 0x9 : I/O high register - io_hi_reg
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--------------------------------------------------------------------------------
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bit name description
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----- ---- -----------
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15-0 io_hi[15:0] I/O data
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Notes:
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- Separate read / write.
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- Reads of io_lo_reg freeze data in io_hi_reg, so read io_lo_reg first then
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read io_hi_reg for contiguous wide (32 bit) data reads.
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- Writes function normally.
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================================================================================
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- 0xA - 0xB : UNUSED
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================================================================================
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- 0xC : UART RX register - uart_rx_reg
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--------------------------------------------------------------------------------
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bit name description
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----- ---- -----------
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7-0 uart_rx_data[7:0] RX UART data
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8 rx_rdy 1=RX UART ready (has new data); 0=not ready
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15-9 - 0000000
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Notes:
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- Reads from this register pop data from the RX UART.
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- To avoid RX data loss, read soon after RX UART is ready.
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- UART ready bit will self clear after associated register operation.
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================================================================================
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- 0xD : UART TX register - uart_tx_reg
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--------------------------------------------------------------------------------
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bit name description
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----- ---- -----------
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7-0 uart_tx_data[7:0] TX UART data
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8 tx_rdy 1=TX UART ready (for new data); 0=not ready
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15-9 - 0000000
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Notes:
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- Writes to this register push data to the TX UART.
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- To avoid TX data loss, restrict writes to when TX UART is ready.
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- UART ready bit will self clear after associated register operation.
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================================================================================
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- 0xE - 0xF : UNUSED
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================================================================================
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*/
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module reg_set
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#(
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parameter integer REGS_IN = 1, // bus in register option
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parameter integer REGS_OUT = 1, // bus out register option
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parameter integer DATA_W = 16, // data width (bits)
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parameter integer ADDR_W = 4, // address width (bits)
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parameter integer THREADS = 8, // threads
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parameter integer THRD_W = 3, // thread selector width
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parameter integer STACKS = 8, // stacks
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parameter integer STK_W = 3, // stack selector width
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//
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parameter [DATA_W/2-1:0] VER_MAJ = 'h1, // core version
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parameter [DATA_W/2-1:0] VER_MIN = 'h0,
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//
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parameter integer UART_DATA_W = 8, // uart data width (bits)
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parameter integer CLK_HZ = 160000000, // master clk_i rate (Hz)
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parameter integer UART_BAUD_RATE = 115200 // uart baud rate (Hz)
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)
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(
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// clocks & resets
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input wire clk_i, // clock
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input wire rst_i, // async. reset, active high
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// bus interface
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input wire [ADDR_W-1:0] addr_i, // address
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input wire wr_i, // data write enable, active high
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input wire rd_i, // data read enable, active high
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input wire [DATA_W-1:0] data_i, // write data
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output wire [DATA_W-1:0] data_o, // read data
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// clear
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output wire [THREADS-1:0] clr_req_o, // clr request, active high
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// interrupt
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output wire [THREADS-1:0] intr_en_o, // interrupt enable, active high
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// errors
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input wire [THRD_W-1:0] thrd_0_i, // thread
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input wire op_code_er_i, // 1=illegal op code encountered
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input wire [THRD_W-1:0] thrd_2_i, // thread
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input wire [STACKS-1:0] pop_er_2_i, // pop when empty, active high
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input wire [THRD_W-1:0] thrd_3_i, // thread
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input wire [STACKS-1:0] push_er_3_i, // push when full, active high
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// I/O
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input wire [DATA_W-1:0] io_lo_i, // gpio linked to io_hi_i
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input wire [DATA_W-1:0] io_hi_i,
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output wire [DATA_W-1:0] io_lo_o, // unlinked gpio
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output wire [DATA_W-1:0] io_hi_o,
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// serial interface
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input wire uart_rx_i, // serial data
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output wire uart_tx_o // serial data
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);
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/*
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----------------------
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-- internal signals --
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----------------------
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*/
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`include "reg_set_addr.h"
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//
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wire [ADDR_W-1:0] addr;
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wire reg_en, wr, rd;
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wire [DATA_W-1:0] rd_data, wr_data, reg_rd_data;
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wire [DATA_W-1:0] ver_rd_data,
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thrd_id_rd_data,
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clr_rd_data,
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intr_en_rd_data,
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op_er_rd_data,
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stk_er_data,
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io_lo_rd_data,
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io_hi_rd_data,
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uart_rx_rd_data,
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uart_tx_rd_data;
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//
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wire io_lo_reg_rd;
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wire [THREADS-1:0] op_code_errors, push_errors, pop_errors;
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wire [UART_DATA_W-1:0] uart_tx_data, uart_rx_data;
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wire uart_tx_rdy, uart_rx_rdy;
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wire uart_tx_wr, uart_rx_rd;
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/*
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================
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== code start ==
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================
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*/
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// optional bus input regs
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pipe
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#(
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.DEPTH ( REGS_IN ),
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.WIDTH ( 2+ADDR_W+DATA_W ),
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.RESET_VAL ( 0 )
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)
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in_regs
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(
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.clk_i ( clk_i ),
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| 279 |
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.rst_i ( rst_i ),
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.data_i ( { wr_i, rd_i, addr_i, data_i } ),
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.data_o ( { wr, rd, addr, wr_data } )
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| 282 |
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);
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| 283 |
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// big ORing of read data
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assign rd_data =
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| 287 |
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ver_rd_data |
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| 288 |
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thrd_id_rd_data |
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| 289 |
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clr_rd_data |
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| 290 |
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intr_en_rd_data |
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| 291 |
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op_er_rd_data |
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| 292 |
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stk_er_data |
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| 293 |
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io_lo_rd_data |
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| 294 |
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io_hi_rd_data |
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| 295 |
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uart_rx_rd_data |
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uart_tx_rd_data;
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| 297 |
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| 298 |
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// optional output regs
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pipe
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| 301 |
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#(
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| 302 |
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.DEPTH ( REGS_OUT ),
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| 303 |
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.WIDTH ( DATA_W ),
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| 304 |
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.RESET_VAL ( 0 )
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| 305 |
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)
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| 306 |
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out_regs
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| 307 |
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(
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| 308 |
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.clk_i ( clk_i ),
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| 309 |
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.rst_i ( rst_i ),
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| 310 |
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.data_i ( rd_data ),
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| 311 |
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.data_o ( data_o )
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| 312 |
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);
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| 313 |
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| 314 |
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| 315 |
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| 316 |
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/*
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| 317 |
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-------------
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| 318 |
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-- ver_reg --
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| 319 |
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-------------
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| 320 |
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*/
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| 321 |
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| 322 |
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reg_base
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| 323 |
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#(
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| 324 |
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.DATA_W ( DATA_W ),
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| 325 |
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.ADDR_W ( ADDR_W ),
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| 326 |
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.ADDRESS ( VER_ADDR[ADDR_W-1:0] ),
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| 327 |
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.OUT_MODE ( "ZERO" ),
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| 328 |
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.READ_MODE ( "THRU" )
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| 329 |
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)
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| 330 |
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ver_reg
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| 331 |
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(
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| 332 |
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.clk_i ( clk_i ),
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| 333 |
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.rst_i ( rst_i ),
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| 334 |
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.addr_i ( addr ),
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| 335 |
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.wr_i ( wr ),
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| 336 |
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.rd_i ( rd ),
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| 337 |
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.wr_data_i ( wr_data ),
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| 338 |
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.rd_data_o ( ver_rd_data ),
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| 339 |
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.reg_data_i ( { VER_MAJ, VER_MIN } )
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| 340 |
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);
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| 341 |
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| 342 |
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| 343 |
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/*
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| 344 |
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-----------------
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| 345 |
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-- thrd_id_reg --
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| 346 |
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-----------------
|
| 347 |
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*/
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| 348 |
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| 349 |
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reg_base
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| 350 |
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#(
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| 351 |
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.DATA_W ( DATA_W ),
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| 352 |
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.ADDR_W ( ADDR_W ),
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| 353 |
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.ADDRESS ( THRD_ID_ADDR[ADDR_W-1:0] ),
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| 354 |
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.OUT_MODE ( "ZERO" ),
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| 355 |
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.READ_MODE ( "THRU" ),
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| 356 |
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.LIVE_MASK ( { THRD_W{ 1'b1 } } )
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| 357 |
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)
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| 358 |
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thrd_id_reg
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| 359 |
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(
|
| 360 |
|
|
.clk_i ( clk_i ),
|
| 361 |
|
|
.rst_i ( rst_i ),
|
| 362 |
|
|
.addr_i ( addr ),
|
| 363 |
|
|
.wr_i ( wr ),
|
| 364 |
|
|
.rd_i ( rd ),
|
| 365 |
|
|
.wr_data_i ( wr_data ),
|
| 366 |
|
|
.rd_data_o ( thrd_id_rd_data ),
|
| 367 |
|
|
.reg_data_i ( thrd_3_i )
|
| 368 |
|
|
);
|
| 369 |
|
|
|
| 370 |
|
|
|
| 371 |
|
|
/*
|
| 372 |
|
|
-------------
|
| 373 |
|
|
-- clr_reg --
|
| 374 |
|
|
-------------
|
| 375 |
|
|
*/
|
| 376 |
|
|
reg_base
|
| 377 |
|
|
#(
|
| 378 |
|
|
.DATA_W ( DATA_W ),
|
| 379 |
|
|
.ADDR_W ( ADDR_W ),
|
| 380 |
|
|
.ADDRESS ( CLR_ADDR[ADDR_W-1:0] ),
|
| 381 |
|
|
.OUT_MODE ( "LTCH" ),
|
| 382 |
|
|
.READ_MODE ( "LOOP" ),
|
| 383 |
|
|
.LIVE_MASK ( { THREADS{ 1'b1 } } )
|
| 384 |
|
|
)
|
| 385 |
|
|
clr_reg
|
| 386 |
|
|
(
|
| 387 |
|
|
.clk_i ( clk_i ),
|
| 388 |
|
|
.rst_i ( rst_i ),
|
| 389 |
|
|
.addr_i ( addr ),
|
| 390 |
|
|
.wr_i ( wr ),
|
| 391 |
|
|
.rd_i ( rd ),
|
| 392 |
|
|
.wr_data_i ( wr_data ),
|
| 393 |
|
|
.rd_data_o ( clr_rd_data ),
|
| 394 |
|
|
.reg_data_o ( clr_req_o )
|
| 395 |
|
|
);
|
| 396 |
|
|
|
| 397 |
|
|
|
| 398 |
|
|
/*
|
| 399 |
|
|
-----------------
|
| 400 |
|
|
-- intr_en_reg --
|
| 401 |
|
|
-----------------
|
| 402 |
|
|
*/
|
| 403 |
|
|
reg_base
|
| 404 |
|
|
#(
|
| 405 |
|
|
.DATA_W ( DATA_W ),
|
| 406 |
|
|
.ADDR_W ( ADDR_W ),
|
| 407 |
|
|
.ADDRESS ( INTR_EN_ADDR[ADDR_W-1:0] ),
|
| 408 |
|
|
.OUT_MODE ( "LTCH" ),
|
| 409 |
|
|
.READ_MODE ( "LOOP" ),
|
| 410 |
|
|
.LIVE_MASK ( { THREADS{ 1'b1 } } )
|
| 411 |
|
|
)
|
| 412 |
|
|
intr_en_reg
|
| 413 |
|
|
(
|
| 414 |
|
|
.clk_i ( clk_i ),
|
| 415 |
|
|
.rst_i ( rst_i ),
|
| 416 |
|
|
.addr_i ( addr ),
|
| 417 |
|
|
.wr_i ( wr ),
|
| 418 |
|
|
.rd_i ( rd ),
|
| 419 |
|
|
.wr_data_i ( wr_data ),
|
| 420 |
|
|
.rd_data_o ( intr_en_rd_data ),
|
| 421 |
|
|
.reg_data_o ( intr_en_o )
|
| 422 |
|
|
);
|
| 423 |
|
|
|
| 424 |
|
|
|
| 425 |
|
|
/*
|
| 426 |
|
|
---------------
|
| 427 |
|
|
-- op_er_reg --
|
| 428 |
|
|
---------------
|
| 429 |
|
|
*/
|
| 430 |
|
|
reg_base
|
| 431 |
|
|
#(
|
| 432 |
|
|
.DATA_W ( DATA_W ),
|
| 433 |
|
|
.ADDR_W ( ADDR_W ),
|
| 434 |
|
|
.ADDRESS ( OP_ER_ADDR[ADDR_W-1:0] ),
|
| 435 |
|
|
.OUT_MODE ( "ZERO" ),
|
| 436 |
|
|
.READ_MODE ( "COW1" ),
|
| 437 |
|
|
.LIVE_MASK ( { THREADS{ 1'b1 } } )
|
| 438 |
|
|
)
|
| 439 |
|
|
op_er_reg
|
| 440 |
|
|
(
|
| 441 |
|
|
.clk_i ( clk_i ),
|
| 442 |
|
|
.rst_i ( rst_i ),
|
| 443 |
|
|
.addr_i ( addr ),
|
| 444 |
|
|
.wr_i ( wr ),
|
| 445 |
|
|
.rd_i ( rd ),
|
| 446 |
|
|
.wr_data_i ( wr_data ),
|
| 447 |
|
|
.rd_data_o ( op_er_rd_data ),
|
| 448 |
|
|
.reg_data_i ( op_code_errors )
|
| 449 |
|
|
);
|
| 450 |
|
|
|
| 451 |
|
|
// decode errors
|
| 452 |
|
|
assign op_code_errors = op_code_er_i << thrd_0_i;
|
| 453 |
|
|
|
| 454 |
|
|
|
| 455 |
|
|
/*
|
| 456 |
|
|
----------------
|
| 457 |
|
|
-- stk_er_reg --
|
| 458 |
|
|
----------------
|
| 459 |
|
|
*/
|
| 460 |
|
|
reg_base
|
| 461 |
|
|
#(
|
| 462 |
|
|
.DATA_W ( DATA_W ),
|
| 463 |
|
|
.ADDR_W ( ADDR_W ),
|
| 464 |
|
|
.ADDRESS ( STK_ER_ADDR[ADDR_W-1:0] ),
|
| 465 |
|
|
.OUT_MODE ( "ZERO" ),
|
| 466 |
|
|
.READ_MODE ( "COW1" ),
|
| 467 |
|
|
.LIVE_MASK ( { (THREADS+THREADS){ 1'b1 } } )
|
| 468 |
|
|
)
|
| 469 |
|
|
stk_er_reg
|
| 470 |
|
|
(
|
| 471 |
|
|
.clk_i ( clk_i ),
|
| 472 |
|
|
.rst_i ( rst_i ),
|
| 473 |
|
|
.addr_i ( addr ),
|
| 474 |
|
|
.wr_i ( wr ),
|
| 475 |
|
|
.rd_i ( rd ),
|
| 476 |
|
|
.wr_data_i ( wr_data ),
|
| 477 |
|
|
.rd_data_o ( stk_er_data ),
|
| 478 |
|
|
.reg_data_i ( { push_errors, pop_errors } )
|
| 479 |
|
|
);
|
| 480 |
|
|
|
| 481 |
|
|
// decode errors
|
| 482 |
|
|
assign push_errors = |push_er_3_i << thrd_3_i;
|
| 483 |
|
|
assign pop_errors = |pop_er_2_i << thrd_2_i;
|
| 484 |
|
|
|
| 485 |
|
|
|
| 486 |
|
|
/*
|
| 487 |
|
|
---------------
|
| 488 |
|
|
-- io_lo_reg --
|
| 489 |
|
|
---------------
|
| 490 |
|
|
*/
|
| 491 |
|
|
reg_base
|
| 492 |
|
|
#(
|
| 493 |
|
|
.DATA_W ( DATA_W ),
|
| 494 |
|
|
.ADDR_W ( ADDR_W ),
|
| 495 |
|
|
.ADDRESS ( IO_LO_ADDR[ADDR_W-1:0] ),
|
| 496 |
|
|
.OUT_MODE ( "LTCH" ),
|
| 497 |
|
|
.READ_MODE ( "THRU" )
|
| 498 |
|
|
)
|
| 499 |
|
|
io_lo_reg
|
| 500 |
|
|
(
|
| 501 |
|
|
.clk_i ( clk_i ),
|
| 502 |
|
|
.rst_i ( rst_i ),
|
| 503 |
|
|
.addr_i ( addr ),
|
| 504 |
|
|
.wr_i ( wr ),
|
| 505 |
|
|
.rd_i ( rd ),
|
| 506 |
|
|
.wr_data_i ( wr_data ),
|
| 507 |
|
|
.rd_data_o ( io_lo_rd_data ),
|
| 508 |
|
|
.reg_rd_o ( io_lo_reg_rd ),
|
| 509 |
|
|
.reg_data_i ( io_lo_i ),
|
| 510 |
|
|
.reg_data_o ( io_lo_o )
|
| 511 |
|
|
);
|
| 512 |
|
|
|
| 513 |
|
|
|
| 514 |
|
|
/*
|
| 515 |
|
|
---------------
|
| 516 |
|
|
-- io_hi_reg --
|
| 517 |
|
|
---------------
|
| 518 |
|
|
*/
|
| 519 |
|
|
reg_base
|
| 520 |
|
|
#(
|
| 521 |
|
|
.DATA_W ( DATA_W ),
|
| 522 |
|
|
.ADDR_W ( ADDR_W ),
|
| 523 |
|
|
.ADDRESS ( IO_HI_ADDR[ADDR_W-1:0] ),
|
| 524 |
|
|
.OUT_MODE ( "LTCH" ),
|
| 525 |
|
|
.READ_MODE ( "DFFE" )
|
| 526 |
|
|
)
|
| 527 |
|
|
io_hi_reg
|
| 528 |
|
|
(
|
| 529 |
|
|
.clk_i ( clk_i ),
|
| 530 |
|
|
.rst_i ( rst_i ),
|
| 531 |
|
|
.addr_i ( addr ),
|
| 532 |
|
|
.wr_i ( wr ),
|
| 533 |
|
|
.rd_i ( rd ),
|
| 534 |
|
|
.wr_data_i ( wr_data ),
|
| 535 |
|
|
.rd_data_o ( io_hi_rd_data ),
|
| 536 |
|
|
.reg_en_i ( io_lo_reg_rd ), // enable on lo read
|
| 537 |
|
|
.reg_data_i ( io_hi_i ),
|
| 538 |
|
|
.reg_data_o ( io_hi_o )
|
| 539 |
|
|
);
|
| 540 |
|
|
|
| 541 |
|
|
|
| 542 |
|
|
/*
|
| 543 |
|
|
-----------------
|
| 544 |
|
|
-- uart_rx_reg --
|
| 545 |
|
|
-----------------
|
| 546 |
|
|
*/
|
| 547 |
|
|
reg_base
|
| 548 |
|
|
#(
|
| 549 |
|
|
.DATA_W ( DATA_W ),
|
| 550 |
|
|
.ADDR_W ( ADDR_W ),
|
| 551 |
|
|
.ADDRESS ( UART_RX_ADDR[ADDR_W-1:0] ),
|
| 552 |
|
|
.OUT_MODE ( "ZERO" ),
|
| 553 |
|
|
.READ_MODE ( "THRU" ),
|
| 554 |
|
|
.LIVE_MASK ( { 1+UART_DATA_W{ 1'b1 } } )
|
| 555 |
|
|
)
|
| 556 |
|
|
uart_rx_reg
|
| 557 |
|
|
(
|
| 558 |
|
|
.clk_i ( clk_i ),
|
| 559 |
|
|
.rst_i ( rst_i ),
|
| 560 |
|
|
.addr_i ( addr ),
|
| 561 |
|
|
.wr_i ( wr ),
|
| 562 |
|
|
.rd_i ( rd ),
|
| 563 |
|
|
.wr_data_i ( wr_data ),
|
| 564 |
|
|
.rd_data_o ( uart_rx_rd_data ),
|
| 565 |
|
|
.reg_rd_o ( uart_rx_rd ),
|
| 566 |
|
|
.reg_data_i ( { uart_rx_rdy, uart_rx_data } ),
|
| 567 |
|
|
.reg_data_o ( )
|
| 568 |
|
|
);
|
| 569 |
|
|
|
| 570 |
|
|
|
| 571 |
|
|
/*
|
| 572 |
|
|
-----------------
|
| 573 |
|
|
-- uart_tx_reg --
|
| 574 |
|
|
-----------------
|
| 575 |
|
|
*/
|
| 576 |
|
|
reg_base
|
| 577 |
|
|
#(
|
| 578 |
|
|
.DATA_W ( DATA_W ),
|
| 579 |
|
|
.ADDR_W ( ADDR_W ),
|
| 580 |
|
|
.ADDRESS ( UART_TX_ADDR[ADDR_W-1:0] ),
|
| 581 |
|
|
.OUT_MODE ( "THRU" ),
|
| 582 |
|
|
.READ_MODE ( "THRU" ),
|
| 583 |
|
|
.LIVE_MASK ( { 1+UART_DATA_W{ 1'b1 } } )
|
| 584 |
|
|
)
|
| 585 |
|
|
uart_tx_reg
|
| 586 |
|
|
(
|
| 587 |
|
|
.clk_i ( clk_i ),
|
| 588 |
|
|
.rst_i ( rst_i ),
|
| 589 |
|
|
.addr_i ( addr ),
|
| 590 |
|
|
.wr_i ( wr ),
|
| 591 |
|
|
.rd_i ( rd ),
|
| 592 |
|
|
.wr_data_i ( wr_data ),
|
| 593 |
|
|
.rd_data_o ( uart_tx_rd_data ),
|
| 594 |
|
|
.reg_wr_o ( uart_tx_wr ),
|
| 595 |
|
|
.reg_data_i ( { uart_tx_rdy, { UART_DATA_W{ 1'b0 } } } ),
|
| 596 |
|
|
.reg_data_o ( uart_tx_data )
|
| 597 |
|
|
);
|
| 598 |
|
|
|
| 599 |
|
|
|
| 600 |
|
|
uart_core
|
| 601 |
|
|
#(
|
| 602 |
|
|
.CLK_HZ ( CLK_HZ ),
|
| 603 |
|
|
.BAUD_RATE ( UART_BAUD_RATE ),
|
| 604 |
|
|
.DATA_W ( UART_DATA_W )
|
| 605 |
|
|
)
|
| 606 |
|
|
uart_core_inst
|
| 607 |
|
|
(
|
| 608 |
|
|
.clk_i ( clk_i ),
|
| 609 |
|
|
.rst_i ( rst_i ),
|
| 610 |
|
|
.tx_data_i ( uart_tx_data ),
|
| 611 |
|
|
.tx_rdy_o ( uart_tx_rdy ),
|
| 612 |
|
|
.tx_wr_i ( uart_tx_wr ),
|
| 613 |
|
|
.rx_data_o ( uart_rx_data ),
|
| 614 |
|
|
.rx_rdy_o ( uart_rx_rdy ),
|
| 615 |
|
|
.rx_rd_i ( uart_rx_rd ),
|
| 616 |
|
|
.tx_o ( uart_tx_o ),
|
| 617 |
|
|
.rx_i ( uart_rx_i ),
|
| 618 |
|
|
.loop_i ( 1'b0 ), // unused
|
| 619 |
|
|
.rx_error_o ( ), // unused
|
| 620 |
|
|
.rx_bad_buffer_o ( ), // unused
|
| 621 |
|
|
.baud_clk_o ( ) // unused
|
| 622 |
|
|
);
|
| 623 |
|
|
|
| 624 |
|
|
|
| 625 |
|
|
endmodule
|
