OpenCores
URL https://opencores.org/ocsvn/i2clcd/i2clcd/trunk

Subversion Repositories i2clcd

[/] [i2clcd/] [trunk/] [i2clcd/] [rtl/] [verilog/] [i2cgpio.v] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 siva12
// rtl program for i2c_gpio.v
2
 
3
`define         P0_P9_OP        4'b1010 //0x0A
4
//`define               P0_P3_OP        4'b1011 //0x0B
5
`define         P0_P3_OP        4'b0111 //0x07
6
`define         P4_P7_OP        4'b1110 //0xE0
7
//`define               P8_P9_OP        4'b1101 //0x0D
8
 
9
module i2c_gpio(clk, cs, sr_in, sda_out, sr_out, gpio);
10
 
11
   input clk,cs;
12
   input sr_in;
13
   output sda_out;
14
   output sr_out;
15
   output [7:0] gpio;
16
 
17
   reg [7:0]     sr;
18
   reg [7:0]     addrreg;
19
   reg          sda_out;
20
   reg          sr_out ;
21
   reg [7:0]     gpio;
22
   reg [7:0]     ram;
23
   wire [3:0]    addr;
24
   wire [3:0]    data;
25
 
26
   assign addr = sr[3:0];
27
   assign data = sr[7:4];
28
   always@(posedge clk)
29
     begin
30
        if (cs == 1'b0)
31
          begin
32
             sr_out <= sr[7];
33
             sr[7:1] <= sr[6:0];
34
             sr[0] <= sr_in;
35
          end
36
        begin
37
           if (addr[0] == 1'b0)               // low bit zero - start bit
38
             begin
39
                if(addr[3:0] == 4'h0E)         // 0xD is the address of the slave
40
                  begin
41
                     sda_out = 1'b1;          // high bit for Acknowledge to master
42
                     if(addr[3]== 1'b1)       // high bit for write
43
                       begin
44
                          case (addr[3:0])    // data[3:0] for data write
45
//                          `P0_P9_OP : gpio[7:4] <= {sr[0], sr[1], sr[2], sr[3], sr[4], sr[5], sr[6], sr[7]};
46
                            `P0_P3_OP : gpio[3:0] <= {data[0], data[1], data[2], data[3]};
47
                            `P4_P7_OP : gpio[3:0] <= {data[3], data[2], data[1], data[0]};
48
//                          `P8_P9_OP : gpio[9:8] <= {sr[0], sr[0]};
49
//                          default   : gpio[7:0] <= {sr[0], sr[0], sr[0], sr[0],
50
//                                                    sr[0], sr[0], sr[0], sr[0]};
51
                          endcase
52
                          sda_out = 1'b1;     // high bit for Acknowledge master
53
                       end
54
                     else
55
                       begin
56
                          sda_out = 1'bz;
57
                       end
58
                  end
59
             end
60
        end
61
     end
62
endmodule
63
 
64
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.