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eightycc |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: 650 accumulator register.
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//
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// Additional Comments: See US 2959351, Fig. 64.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module accumulator (
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input rst,
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input ap, bp, dp,
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eightycc |
input d1, d2, d10,
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input dxu, d0u,
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eightycc |
input wu, wl,
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input [0:6] adder_out,
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input acc_regen_gate, right_shift_gate, acc_ri_gate,
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zero_shift_count, man_acc_reset, reset_op_latch,
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input [0:3] early_idx, ontime_idx,
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output reg [0:6] early_out, ontime_out, ped_out
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);
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//-----------------------------------------------------------------------------
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// The accumulator occupies 22 locations of a 32x7bit RAM.
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//-----------------------------------------------------------------------------
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reg [0:6] digits [0:31];
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wire [0:4] acc_early_idx = {(d10? ~wu : wu), early_idx};
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wire [0:4] acc_ontime_idx = {wu, ontime_idx};
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//-----------------------------------------------------------------------------
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// A -- Read into early_out from RAM
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// Read into ontime_out
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//-----------------------------------------------------------------------------
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wire acc_reset = reset_op_latch | man_acc_reset
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eightycc |
| (zero_shift_count & wl & (d1 | d2));
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eightycc |
always @(posedge ap) begin
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if (rst) begin
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early_out <= `biq_blank;
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ontime_out <= `biq_blank;
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end else begin
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early_out <= reset_op_latch? `biq_0
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: digits[acc_early_idx];
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ontime_out <= (acc_reset | d0u | dxu)? `biq_0 : early_out;
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end
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end;
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//-----------------------------------------------------------------------------
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// B -- Read into ped_out
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//-----------------------------------------------------------------------------
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always @(posedge bp) begin
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if (rst) begin
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ped_out <= `biq_blank;
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end else begin
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ped_out <= right_shift_gate? early_out
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: acc_ri_gate? adder_out
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: acc_regen_gate? ontime_out
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: `biq_blank;
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end
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end;
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//-----------------------------------------------------------------------------
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// D -- Write ped_out into RAM
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//-----------------------------------------------------------------------------
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always @(posedge dp) begin
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digits[acc_ontime_idx] <= ped_out;
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end;
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endmodule
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