| 1 |
21 |
eightycc |
`timescale 1ns / 1ps
|
| 2 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
| 3 |
|
|
// IBM 650 Reconstruction in Verilog (i650)
|
| 4 |
|
|
//
|
| 5 |
|
|
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
|
| 6 |
|
|
// http:////www.opencores.org/project,i650
|
| 7 |
|
|
//
|
| 8 |
|
|
// Description: Adder input A.
|
| 9 |
|
|
//
|
| 10 |
|
|
// Additional Comments: See US 2959351, Fig. 66.
|
| 11 |
|
|
//
|
| 12 |
|
|
// Copyright (c) 2015 Robert Abeles
|
| 13 |
|
|
//
|
| 14 |
|
|
// This source file is free software; you can redistribute it
|
| 15 |
|
|
// and/or modify it under the terms of the GNU Lesser General
|
| 16 |
|
|
// Public License as published by the Free Software Foundation;
|
| 17 |
|
|
// either version 2.1 of the License, or (at your option) any
|
| 18 |
|
|
// later version.
|
| 19 |
|
|
//
|
| 20 |
|
|
// This source is distributed in the hope that it will be
|
| 21 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
| 22 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
| 23 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more
|
| 24 |
|
|
// details.
|
| 25 |
|
|
//
|
| 26 |
|
|
// You should have received a copy of the GNU Lesser General
|
| 27 |
|
|
// Public License along with this source; if not, download it
|
| 28 |
|
|
// from http://www.opencores.org/lgpl.shtml
|
| 29 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
| 30 |
|
|
`include "defines.v"
|
| 31 |
|
|
|
| 32 |
|
|
module add_in_a (
|
| 33 |
|
|
input [0:6] acc_early_out, acc_ontime_out, prog_step_early_out,
|
| 34 |
|
|
select_storage_out, addr_u,
|
| 35 |
|
|
input acc_true_add_gate, acc_compl_add_gate,
|
| 36 |
|
|
left_shift_gate, prog_step_add_gate, shift_num_gate,
|
| 37 |
|
|
select_stor_add_gate,
|
| 38 |
|
|
output [0:6] adder_entry_a
|
| 39 |
|
|
);
|
| 40 |
|
|
|
| 41 |
|
|
wire [0:6] acc_early_compl; // 9's complement
|
| 42 |
|
|
biq_9s_comp bc1 (acc_early_out, acc_early_compl);
|
| 43 |
|
|
wire [0:6] addr_u_compl;
|
| 44 |
|
|
biq_9s_comp bc2 (addr_u, addr_u_compl);
|
| 45 |
|
|
|
| 46 |
|
|
assign adder_entry_a = acc_true_add_gate? acc_early_out
|
| 47 |
|
|
: acc_compl_add_gate? acc_early_compl
|
| 48 |
|
|
: left_shift_gate? acc_ontime_out
|
| 49 |
|
|
: prog_step_add_gate? prog_step_early_out
|
| 50 |
|
|
: shift_num_gate? addr_u_compl
|
| 51 |
|
|
: select_stor_add_gate? select_storage_out
|
| 52 |
|
|
: `biq_blank;
|
| 53 |
|
|
|
| 54 |
|
|
endmodule
|
