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eightycc |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Storage output selection.
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//
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// Additional Comments: See US 2959351, Fig. 73.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module store_select (
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input d0, d1_dx,
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input addr_no_800x, addr_8000, addr_8001, addr_8002_8003,
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input addr_hot_8000,
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input [0:6] acc_ontime, dist_ontime, gs_out, console_switches,
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input acc_plus, acc_minus,
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output [0:6] selected_out
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);
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wire[0:6] acc_sign = acc_plus? `biq_9 : acc_minus? `biq_8 : `biq_blank;
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wire[0:6] acc_select = d1_dx? acc_ontime : d0? acc_sign : `biq_blank;
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assign selected_out = addr_no_800x? gs_out
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: (addr_8000 | addr_hot_8000)? console_switches
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: addr_8001? dist_ontime
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: addr_8002_8003? acc_select
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: `biq_blank;
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endmodule
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