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`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// IBM 650 Reconstruction in Verilog (i650)

// 

// This file is part of the IBM 650 Reconstruction in Verilog (i650) project

// http:////www.opencores.org/project,i650

//

// Description: Top level.

// 

// Additional Comments: See US 2959351, Fig. 53, 54 and 55. Additional index

//  counters provided to address general storage and register RAMs.

//

// Copyright (c) 2015 Robert Abeles

//

// This source file is free software; you can redistribute it

// and/or modify it under the terms of the GNU Lesser General

// Public License as published by the Free Software Foundation;

// either version 2.1 of the License, or (at your option) any

// later version.

//

// This source is distributed in the hope that it will be

// useful, but WITHOUT ANY WARRANTY; without even the implied

// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR

// PURPOSE.  See the GNU Lesser General Public License for more

// details.

//

// You should have received a copy of the GNU Lesser General

// Public License along with this source; if not, download it

// from http://www.opencores.org/lgpl.shtml

//////////////////////////////////////////////////////////////////////////////////

`include "defines.v"

module toplev (

      input clk,

      input rst,

           input [0:6] cmd_digit_in, io_buffer_in,

           input [0:5] command,

           output [0:6] cmd_digit_out,

           output busy, digit_ready, punch_card, read_card, card_digit_ready,

      output synch

  );

        wire ap, bp, cp, dp;

        wire dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,

                  d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,

                  dxl, dxu, d0l, d0u, d1l, d1u, d2l, d10u;

        wire w0, w1, w2, w3, w4, w5, w6, w7, w8, w9,

             wl, wu, ewl;

        wire s0, s1, s2, s3, s4, hp;

        wire [0:9] digit_idx;

        wire [0:3] early_idx, ontime_idx;

   assign synch = bp;

        timing tm (

    .clk(clk),

    .rst(rst),

    .ap(ap),

    .bp(bp),

    .cp(cp),

    .dp(dp),

    .dx(dx),

    .d0(d0),

    .d1(d1),

    .d2(d2),

    .d3(d3),

    .d4(d4),

    .d5(d5),

    .d6(d6),

    .d7(d7),

    .d8(d8),

    .d9(d9),

    .d10(d10),

    .d1_d5(d1_d5),

    .d5_dx(d5_dx),

    .d5_d10(d5_d10),

    .d1_dx(d1_dx),

    .d5_d9(d5_d9),

    .d10_d1_d5(d10_d1_d5),

    .dxl(dxl),

    .dxu(dxu),

    .d0l(d0l),

    .d0u(d0u),

    .d1l(d1l),

    .d1u(d1u),

    .d2l(d2l),

    .d10u(d10u),

    .w0(w0),

    .w1(w1),

    .w2(w2),

    .w3(w3),

    .w4(w4),

    .w5(w5),

    .w6(w6),

    .w7(w7),

    .w8(w8),

    .w9(w9),

    .wl(wl),

    .wu(wu),

    .ewl(ewl),

    .s0(s0),

    .s1(s1),

    .s2(s2),

    .s3(s3),

    .s4(s4),

    .hp(hp),

    .digit_idx(digit_idx),

    .early_idx(early_idx),

    .ontime_idx(ontime_idx)

   );

   //-----------------------------------------------------------------------------

   // General storage

   //-----------------------------------------------------------------------------

        wire [0:4] gs_out;

        wire gs_double_write, gs_no_write;

   //-----------------------------------------------------------------------------

   // Operator controls

   //-----------------------------------------------------------------------------

        wire [0:6] oc_data_out, oc_addr_out, oc_console_out;

        wire oc_console_to_addr;

        wire [0:14] oc_gs_ram_addr;

        wire oc_read_gs, oc_write_gs;

        wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;

        wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,

             oc_storage_control;

        wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,

        oc_hard_reset;

   //-----------------------------------------------------------------------------

   // Translators

   //-----------------------------------------------------------------------------

        wire tr_gs_write;

        wire [0:4] tr_gs_in;

        wire [0:6] tr_select_out;

        gen_store gs (

    .rst(oc_hard_reset),

    .ap(ap),

    .dp(dp),

    .write_gate(tr_gs_write),

    .addr_th(`biq_blank),

    .addr_h(`biq_blank),

    .addr_t(`biq_blank),

    .dynamic_addr(digit_idx),

    .gs_in(tr_gs_in),

    .console_ram_addr(oc_gs_ram_addr),

    .console_read_gs(oc_read_gs),

         .console_write_gs(oc_write_gs),

    .gs_out(gs_out),

    .double_write(gs_double_write),

    .no_write(gs_no_write)

    );

        operator_ctl oc (

    .rst(rst),

    .clk(clk),

    .ap(ap),

    .dp(dp),

    .dx(dx),

    .d0(d0),

    .d1(d1),

    .d2(d2),

    .d3(d3),

    .d4(d4),

    .d5(d5),

    .d6(d6),

    .d10(d10),

    .wu(wu),

    .hp(hp),

    .early_idx(early_idx),

    .ontime_idx(ontime_idx),

    .cmd_digit_in(cmd_digit_in),

    .io_buffer_in(io_buffer_in),

    .gs_in(tr_select_out),

    .command(command),

    .data_out(oc_data_out),

    .addr_out(oc_addr_out),

    .console_out(oc_console_out),

    .console_to_addr(oc_console_to_addr),

    .gs_ram_addr(oc_gs_ram_addr),

         .read_gs(oc_read_gs),

         .write_gs(oc_write_gs),

    .pgm_start(oc_pgm_start),

    .pgm_stop(oc_pgm_stop),

    .err_reset(oc_err_reset),

    .err_sense_reset(oc_err_sense_reset),

    .run_control(oc_run_control),

    .half_or_pgm_stop(oc_half_or_pgm_stop),

    .ri_storage(oc_ri_storage),

    .ro_storage(oc_ro_storage),

    .storage_control(oc_storage_control),

    .man_pgm_reset(oc_man_pgm_reset),

    .man_acc_reset(oc_man_acc_reset),

    .set_8000(oc_set_8000),

    .reset_8000(oc_reset_8000),

    .hard_reset(oc_hard_reset),

    .cmd_digit_out(cmd_digit_out),

    .busy(busy),

    .digit_ready(digit_ready),

    .punch_card(punch_card),

    .read_card(read_card),

    .card_digit_ready(card_digit_ready)

    );

         translators tr (

    .dist_early_out(`biq_blank),

    .bs_out(`biq_blank),

    .console_out(oc_console_out),

    .ri_gs(1'b0),

    .ri_bs(1'b0),

    .ri_console(oc_write_gs),

    .n800x(1'b1),

    .gs_out(gs_out),

    .gs_write(tr_gs_write),

    .gs_in(tr_gs_in),

    .select_out(tr_select_out)

    );

endmodule