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12 |
eightycc |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Top level.
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//
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// Additional Comments: See US 2959351, Fig. 53, 54 and 55. Additional index
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// counters provided to address general storage and register RAMs.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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| 28 |
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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| 33 |
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module toplev (
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input clk,
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| 35 |
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input rst,
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| 37 |
13 |
eightycc |
input [0:6] cmd_digit_in, io_buffer_in,
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| 38 |
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input [0:5] command,
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12 |
eightycc |
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| 40 |
15 |
eightycc |
output [0:6] cmd_digit_out, display_digit,
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| 41 |
13 |
eightycc |
output busy, digit_ready, punch_card, read_card, card_digit_ready,
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| 42 |
15 |
eightycc |
output digit_sync, word_upper,
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output [0:3] digit_ctr
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12 |
eightycc |
);
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| 45 |
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| 46 |
13 |
eightycc |
wire ap, bp, cp, dp;
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wire dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
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| 48 |
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d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,
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| 49 |
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dxl, dxu, d0l, d0u, d1l, d1u, d2l, d10u;
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| 50 |
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wire w0, w1, w2, w3, w4, w5, w6, w7, w8, w9,
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| 51 |
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wl, wu, ewl;
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| 52 |
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wire s0, s1, s2, s3, s4, hp;
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| 53 |
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wire [0:9] digit_idx;
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| 54 |
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wire [0:3] early_idx, ontime_idx;
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| 55 |
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| 56 |
15 |
eightycc |
assign digit_sync = bp;
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| 57 |
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assign digit_ctr = ontime_idx;
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| 58 |
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assign word_upper = wu;
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13 |
eightycc |
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| 60 |
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timing tm (
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| 61 |
12 |
eightycc |
.clk(clk),
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| 62 |
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.rst(rst),
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| 63 |
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.ap(ap),
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| 64 |
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.bp(bp),
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.cp(cp),
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| 66 |
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.dp(dp),
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| 67 |
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.dx(dx),
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| 68 |
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.d0(d0),
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| 69 |
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.d1(d1),
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| 70 |
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.d2(d2),
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| 71 |
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.d3(d3),
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| 72 |
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.d4(d4),
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| 73 |
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.d5(d5),
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.d6(d6),
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.d7(d7),
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.d8(d8),
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.d9(d9),
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.d10(d10),
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.d1_d5(d1_d5),
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.d5_dx(d5_dx),
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.d5_d10(d5_d10),
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.d1_dx(d1_dx),
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.d5_d9(d5_d9),
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.d10_d1_d5(d10_d1_d5),
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.dxl(dxl),
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.dxu(dxu),
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.d0l(d0l),
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.d0u(d0u),
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.d1l(d1l),
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.d1u(d1u),
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.d2l(d2l),
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.d10u(d10u),
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.w0(w0),
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.w1(w1),
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.w2(w2),
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.w3(w3),
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.w4(w4),
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.w5(w5),
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.w6(w6),
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.w7(w7),
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.w8(w8),
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.w9(w9),
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.wl(wl),
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.wu(wu),
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.ewl(ewl),
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.s0(s0),
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.s1(s1),
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.s2(s2),
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.s3(s3),
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| 110 |
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.s4(s4),
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.hp(hp),
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.digit_idx(digit_idx),
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.early_idx(early_idx),
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.ontime_idx(ontime_idx)
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);
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13 |
eightycc |
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12 |
eightycc |
//-----------------------------------------------------------------------------
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| 118 |
21 |
eightycc |
// Adder input muxes
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//-----------------------------------------------------------------------------
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wire [0:6] aa_entry_a, ab_entry_b;
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| 121 |
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| 122 |
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//-----------------------------------------------------------------------------
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| 123 |
15 |
eightycc |
// Accumulator
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| 124 |
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//-----------------------------------------------------------------------------
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| 125 |
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wire [0:6] ac_early_out, ac_ontime_out, ac_ped_out;
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| 126 |
20 |
eightycc |
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| 127 |
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//-----------------------------------------------------------------------------
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| 128 |
21 |
eightycc |
// Address register
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| 129 |
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//-----------------------------------------------------------------------------
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| 130 |
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wire [0:6] ar_addr_th, ar_addr_h, ar_addr_t, ar_addr_u;
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| 131 |
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wire ar_dynamic_addr_hit, ar_addr_no_800x, ar_addr_8000, ar_addr_8001,
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| 132 |
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ar_addr_8002, ar_addr_8003, ar_addr_8002_8003, ar_invalid_addr;
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| 133 |
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| 134 |
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//-----------------------------------------------------------------------------
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| 135 |
20 |
eightycc |
// Distributor
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| 136 |
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//-----------------------------------------------------------------------------
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| 137 |
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wire [0:6] ds_early_out, ds_ontime_out;
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| 138 |
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wire ds_back_sig;
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| 139 |
15 |
eightycc |
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| 140 |
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//-----------------------------------------------------------------------------
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| 141 |
18 |
eightycc |
// Register validity checking
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| 142 |
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//-----------------------------------------------------------------------------
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| 143 |
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wire ck_error_stop, ck_acc_check_light, ck_prog_check_light,
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| 144 |
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ck_dist_check_light;
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| 145 |
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| 146 |
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//-----------------------------------------------------------------------------
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| 147 |
12 |
eightycc |
// General storage
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| 148 |
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//-----------------------------------------------------------------------------
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| 149 |
13 |
eightycc |
wire [0:4] gs_out;
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| 150 |
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wire gs_double_write, gs_no_write;
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| 151 |
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| 152 |
12 |
eightycc |
//-----------------------------------------------------------------------------
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| 153 |
21 |
eightycc |
// Opcode register
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| 154 |
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//-----------------------------------------------------------------------------
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| 155 |
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wire [0:6] op_opreg_t, op_opreg_u;
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| 156 |
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wire op_ri_addr_reg;
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| 157 |
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| 158 |
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//-----------------------------------------------------------------------------
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| 159 |
12 |
eightycc |
// Operator controls
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| 160 |
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//-----------------------------------------------------------------------------
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| 161 |
15 |
eightycc |
wire [0:6] oc_data_out, oc_addr_out, oc_console_out, oc_display_digit;
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| 162 |
21 |
eightycc |
wire oc_console_to_addr, oc_acc_ri_console;
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| 163 |
13 |
eightycc |
wire [0:14] oc_gs_ram_addr;
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| 164 |
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wire oc_read_gs, oc_write_gs;
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| 165 |
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wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
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| 166 |
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wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
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| 167 |
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oc_storage_control;
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| 168 |
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wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
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| 169 |
12 |
eightycc |
oc_hard_reset;
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| 170 |
15 |
eightycc |
assign display_digit = oc_display_digit;
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| 171 |
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| 172 |
12 |
eightycc |
//-----------------------------------------------------------------------------
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| 173 |
20 |
eightycc |
// Program step register
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| 174 |
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//-----------------------------------------------------------------------------
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| 175 |
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wire [0:6] ps_early_out, ps_ontime_out, ps_ped_out;
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| 176 |
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wire ps_restart_sig;
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| 177 |
21 |
eightycc |
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| 178 |
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//-----------------------------------------------------------------------------
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| 179 |
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// Storage select
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| 180 |
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//-----------------------------------------------------------------------------
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| 181 |
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wire [0:6] ss_selected_out;
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| 182 |
20 |
eightycc |
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| 183 |
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//-----------------------------------------------------------------------------
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| 184 |
12 |
eightycc |
// Translators
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| 185 |
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//-----------------------------------------------------------------------------
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| 186 |
13 |
eightycc |
wire tr_gs_write;
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| 187 |
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wire [0:4] tr_gs_in;
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| 188 |
21 |
eightycc |
wire [0:6] tr_gs_out;
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| 189 |
12 |
eightycc |
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| 190 |
21 |
eightycc |
add_in_a aa (
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| 191 |
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.acc_early_out(ac_early_out),
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| 192 |
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.acc_ontime_out(ac_ontime_out),
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| 193 |
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.prog_step_early_out(ps_early_out),
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| 194 |
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.select_storage_out(ss_selected_out),
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| 195 |
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.addr_u(ar_addr_u),
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| 196 |
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.acc_true_add_gate(1'b0),
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| 197 |
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.acc_compl_add_gate(1'b0),
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| 198 |
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.left_shift_gate(1'b0),
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| 199 |
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.prog_step_add_gate(1'b0),
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| 200 |
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.shift_num_gate(1'b0),
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| 201 |
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.select_stor_add_gate(1'b0),
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| 202 |
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.adder_entry_a(aa_entry_a)
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| 203 |
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);
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| 204 |
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| 205 |
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add_in_b ab (
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| 206 |
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.dist_early_out(ds_early_out),
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| 207 |
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.dist_ontime_out(ds_ontime_out),
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| 208 |
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.special_int_entry(10'd0),
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| 209 |
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.ontime_dist_add_gate_tlu(1'b0),
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| 210 |
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.dist_compl_add_gate(1'b0),
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| 211 |
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.upper_lower_check(1'b0),
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| 212 |
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.dist_blank_gate(1'b0),
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| 213 |
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.early_dist_zero_entry(1'b0),
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| 214 |
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.dist_true_add_gate(1'b0),
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| 215 |
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.adder_entry_b(ab_entry_b)
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| 216 |
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);
|
| 217 |
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|
| 218 |
15 |
eightycc |
accumulator ac (
|
| 219 |
21 |
eightycc |
.rst(oc_hard_reset),
|
| 220 |
15 |
eightycc |
.ap(ap),
|
| 221 |
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.bp(bp),
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| 222 |
18 |
eightycc |
.dp(dp),
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| 223 |
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.dx(dx),
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| 224 |
15 |
eightycc |
.d1(d1),
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| 225 |
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.d2(d2),
|
| 226 |
21 |
eightycc |
.d10(d10),
|
| 227 |
15 |
eightycc |
.dxu(dxu),
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| 228 |
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.d0u(d0u),
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| 229 |
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.wu(wu),
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| 230 |
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.wl(wl),
|
| 231 |
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.adder_out(`biq_0),
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| 232 |
21 |
eightycc |
.console_out(oc_console_out),
|
| 233 |
15 |
eightycc |
.acc_regen_gate(1'b1),
|
| 234 |
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.right_shift_gate(1'b0),
|
| 235 |
21 |
eightycc |
.acc_ri_gate(1'b0),
|
| 236 |
|
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.acc_ri_console(oc_acc_ri_console),
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| 237 |
15 |
eightycc |
.zero_shift_count(1'b0),
|
| 238 |
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.man_acc_reset(oc_man_acc_reset),
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| 239 |
21 |
eightycc |
.reset_op(1'b0),
|
| 240 |
15 |
eightycc |
.early_idx(early_idx),
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| 241 |
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.ontime_idx(ontime_idx),
|
| 242 |
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.early_out(ac_early_out),
|
| 243 |
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.ontime_out(ac_ontime_out),
|
| 244 |
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.ped_out(ac_ped_out)
|
| 245 |
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);
|
| 246 |
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|
|
| 247 |
21 |
eightycc |
addr_reg ar (
|
| 248 |
18 |
eightycc |
.rst(rst),
|
| 249 |
21 |
eightycc |
.ap(ap),
|
| 250 |
18 |
eightycc |
.bp(bp),
|
| 251 |
21 |
eightycc |
.dx(dx),
|
| 252 |
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.d1(d1),
|
| 253 |
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.d2(d2),
|
| 254 |
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.d3(d3),
|
| 255 |
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.d4(d4),
|
| 256 |
|
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.d5(d5),
|
| 257 |
|
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.d6(d6),
|
| 258 |
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.d7(d7),
|
| 259 |
|
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.d8(d8),
|
| 260 |
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.d9(d9),
|
| 261 |
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.w0(w0),
|
| 262 |
|
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.w1(w1),
|
| 263 |
|
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.w2(w2),
|
| 264 |
|
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.w3(w3),
|
| 265 |
|
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.w4(w4),
|
| 266 |
|
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.w5(w5),
|
| 267 |
|
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.w6(w6),
|
| 268 |
|
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.w7(w7),
|
| 269 |
|
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.w8(w8),
|
| 270 |
|
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.w9(w9),
|
| 271 |
|
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.s0(s0),
|
| 272 |
|
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.s1(s1),
|
| 273 |
|
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.s2(s2),
|
| 274 |
|
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.s3(s3),
|
| 275 |
|
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.s4(s4),
|
| 276 |
|
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.error_reset(oc_err_reset),
|
| 277 |
|
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.restart_a(1'b0),
|
| 278 |
|
|
.set_8000(oc_set_8000),
|
| 279 |
|
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.reset_8000(oc_reset_8000),
|
| 280 |
|
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.tlu_band_change(1'b0),
|
| 281 |
|
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.double_write(gs_double_write),
|
| 282 |
|
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.no_write(gs_no_write),
|
| 283 |
|
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.bs_to_gs(1'b0),
|
| 284 |
|
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.ri_gs(1'b0),
|
| 285 |
|
|
.ps_reg_in(ps_ontime_out),
|
| 286 |
|
|
.console_in(oc_addr_out),
|
| 287 |
|
|
.ri_addr_reg(op_ri_addr_reg),
|
| 288 |
|
|
.console_to_addr_reg(oc_console_to_addr),
|
| 289 |
|
|
.addr_th(ar_addr_th),
|
| 290 |
|
|
.addr_h(ar_addr_h),
|
| 291 |
|
|
.addr_t(ar_addr_t),
|
| 292 |
|
|
.addr_u(ar_addr_u),
|
| 293 |
|
|
.dynamic_addr_hit(ar_dynamic_addr_hit),
|
| 294 |
|
|
.addr_no_800x(ar_addr_no_800x),
|
| 295 |
|
|
.addr_8000(ar_addr_8000),
|
| 296 |
|
|
.addr_8001(ar_addr_8001),
|
| 297 |
|
|
.addr_8002(ar_addr_8002),
|
| 298 |
|
|
.addr_8003(ar_addr_8003),
|
| 299 |
|
|
.addr_8002_8003(ar_addr_8002_8003),
|
| 300 |
|
|
.invalid_addr(ar_invalid_addr)
|
| 301 |
|
|
);
|
| 302 |
|
|
|
| 303 |
|
|
checking ck (
|
| 304 |
|
|
.rst(oc_hard_reset),
|
| 305 |
|
|
.bp(bp),
|
| 306 |
18 |
eightycc |
.d1_dx(d1_dx),
|
| 307 |
|
|
.acc_ontime(ac_ontime_out),
|
| 308 |
20 |
eightycc |
.prog_ontime(ps_ontime_out),
|
| 309 |
|
|
.dist_ontime(ds_ontime_out),
|
| 310 |
18 |
eightycc |
.error_reset(oc_err_reset),
|
| 311 |
|
|
.tlu_or_zero_check(1'b0),
|
| 312 |
|
|
.error_stop(ck_error_stop),
|
| 313 |
|
|
.acc_check_light(ck_acc_check_light),
|
| 314 |
|
|
.prog_check_light(ck_prog_check_light),
|
| 315 |
|
|
.dist_check_light(ck_dist_check_light)
|
| 316 |
|
|
);
|
| 317 |
|
|
|
| 318 |
20 |
eightycc |
distributor ds (
|
| 319 |
21 |
eightycc |
.rst(oc_hard_reset),
|
| 320 |
20 |
eightycc |
.ap(ap),
|
| 321 |
|
|
.cp(cp),
|
| 322 |
|
|
.dp(dp),
|
| 323 |
|
|
.dx(dx),
|
| 324 |
|
|
.d0(d0),
|
| 325 |
|
|
.d10(d10),
|
| 326 |
21 |
eightycc |
.selected_storage(ss_selected_out),
|
| 327 |
20 |
eightycc |
.ri_dist(1'd0),
|
| 328 |
|
|
.acc_ontime(ac_ontime_out),
|
| 329 |
|
|
.start_acc_dist_ri(1'd0),
|
| 330 |
|
|
.end_acc_dist_ri(1'd0),
|
| 331 |
|
|
.acc_dist_ri(1'd0),
|
| 332 |
|
|
.man_acc_reset(oc_man_acc_reset),
|
| 333 |
|
|
.early_idx(early_idx),
|
| 334 |
|
|
.ontime_idx(ontime_idx),
|
| 335 |
|
|
.ontime_out(ds_ontime_out),
|
| 336 |
|
|
.early_out(ds_early_out),
|
| 337 |
|
|
.dist_back_sig(ds_back_sig)
|
| 338 |
|
|
);
|
| 339 |
|
|
|
| 340 |
13 |
eightycc |
gen_store gs (
|
| 341 |
12 |
eightycc |
.rst(oc_hard_reset),
|
| 342 |
|
|
.ap(ap),
|
| 343 |
|
|
.dp(dp),
|
| 344 |
|
|
.write_gate(tr_gs_write),
|
| 345 |
21 |
eightycc |
.addr_th(ar_addr_th),
|
| 346 |
|
|
.addr_h(ar_addr_h),
|
| 347 |
|
|
.addr_t(ar_addr_t),
|
| 348 |
12 |
eightycc |
.dynamic_addr(digit_idx),
|
| 349 |
|
|
.gs_in(tr_gs_in),
|
| 350 |
|
|
.console_ram_addr(oc_gs_ram_addr),
|
| 351 |
|
|
.console_read_gs(oc_read_gs),
|
| 352 |
13 |
eightycc |
.console_write_gs(oc_write_gs),
|
| 353 |
12 |
eightycc |
.gs_out(gs_out),
|
| 354 |
|
|
.double_write(gs_double_write),
|
| 355 |
|
|
.no_write(gs_no_write)
|
| 356 |
|
|
);
|
| 357 |
|
|
|
| 358 |
13 |
eightycc |
operator_ctl oc (
|
| 359 |
12 |
eightycc |
.rst(rst),
|
| 360 |
|
|
.clk(clk),
|
| 361 |
|
|
.ap(ap),
|
| 362 |
|
|
.dp(dp),
|
| 363 |
|
|
.dx(dx),
|
| 364 |
|
|
.d0(d0),
|
| 365 |
|
|
.d1(d1),
|
| 366 |
|
|
.d2(d2),
|
| 367 |
|
|
.d3(d3),
|
| 368 |
|
|
.d4(d4),
|
| 369 |
|
|
.d5(d5),
|
| 370 |
16 |
eightycc |
.d6(d6),
|
| 371 |
|
|
.d9(d9),
|
| 372 |
12 |
eightycc |
.d10(d10),
|
| 373 |
16 |
eightycc |
.wu(wu),
|
| 374 |
|
|
.wl(wl),
|
| 375 |
12 |
eightycc |
.hp(hp),
|
| 376 |
|
|
.early_idx(early_idx),
|
| 377 |
|
|
.ontime_idx(ontime_idx),
|
| 378 |
|
|
.cmd_digit_in(cmd_digit_in),
|
| 379 |
|
|
.io_buffer_in(io_buffer_in),
|
| 380 |
21 |
eightycc |
.gs_in(tr_gs_out),
|
| 381 |
15 |
eightycc |
.acc_ontime(ac_ontime_out),
|
| 382 |
20 |
eightycc |
.dist_ontime(ds_ontime_out),
|
| 383 |
|
|
.prog_ontime(ps_ontime_out),
|
| 384 |
12 |
eightycc |
.command(command),
|
| 385 |
|
|
.data_out(oc_data_out),
|
| 386 |
|
|
.addr_out(oc_addr_out),
|
| 387 |
|
|
.console_out(oc_console_out),
|
| 388 |
15 |
eightycc |
.display_digit(oc_display_digit),
|
| 389 |
21 |
eightycc |
.console_to_addr(oc_console_to_addr),
|
| 390 |
|
|
.acc_ri_console(oc_acc_ri_console),
|
| 391 |
12 |
eightycc |
.gs_ram_addr(oc_gs_ram_addr),
|
| 392 |
13 |
eightycc |
.read_gs(oc_read_gs),
|
| 393 |
|
|
.write_gs(oc_write_gs),
|
| 394 |
12 |
eightycc |
.pgm_start(oc_pgm_start),
|
| 395 |
|
|
.pgm_stop(oc_pgm_stop),
|
| 396 |
|
|
.err_reset(oc_err_reset),
|
| 397 |
|
|
.err_sense_reset(oc_err_sense_reset),
|
| 398 |
|
|
.run_control(oc_run_control),
|
| 399 |
|
|
.half_or_pgm_stop(oc_half_or_pgm_stop),
|
| 400 |
|
|
.ri_storage(oc_ri_storage),
|
| 401 |
|
|
.ro_storage(oc_ro_storage),
|
| 402 |
|
|
.storage_control(oc_storage_control),
|
| 403 |
|
|
.man_pgm_reset(oc_man_pgm_reset),
|
| 404 |
|
|
.man_acc_reset(oc_man_acc_reset),
|
| 405 |
|
|
.set_8000(oc_set_8000),
|
| 406 |
|
|
.reset_8000(oc_reset_8000),
|
| 407 |
|
|
.hard_reset(oc_hard_reset),
|
| 408 |
|
|
.cmd_digit_out(cmd_digit_out),
|
| 409 |
|
|
.busy(busy),
|
| 410 |
|
|
.digit_ready(digit_ready),
|
| 411 |
|
|
.punch_card(punch_card),
|
| 412 |
|
|
.read_card(read_card),
|
| 413 |
|
|
.card_digit_ready(card_digit_ready)
|
| 414 |
|
|
);
|
| 415 |
|
|
|
| 416 |
21 |
eightycc |
op_reg op (
|
| 417 |
|
|
.rst(oc_hard_reset),
|
| 418 |
|
|
.cp(cp),
|
| 419 |
|
|
.d0(d0),
|
| 420 |
|
|
.d9(d9),
|
| 421 |
|
|
.d10(d10),
|
| 422 |
|
|
.d1_d5(d1_d5),
|
| 423 |
|
|
.d5_dx(d5_dx),
|
| 424 |
|
|
.restart_a(1'b0),
|
| 425 |
|
|
.restart_b(1'b0),
|
| 426 |
|
|
.d_alt(1'b0),
|
| 427 |
|
|
.i_alt(1'b0),
|
| 428 |
|
|
.tlu_band_change(1'b0),
|
| 429 |
|
|
.man_prog_reset(oc_man_pgm_reset),
|
| 430 |
|
|
.prog_step_ped(ps_ped_out),
|
| 431 |
|
|
.opreg_t(op_opreg_t),
|
| 432 |
|
|
.opreg_u(op_opreg_u),
|
| 433 |
|
|
.ri_addr_reg(op_ri_addr_reg)
|
| 434 |
|
|
);
|
| 435 |
|
|
|
| 436 |
20 |
eightycc |
prog_step ps (
|
| 437 |
21 |
eightycc |
.rst(oc_hard_reset),
|
| 438 |
20 |
eightycc |
.ap(ap),
|
| 439 |
|
|
.dp(dp),
|
| 440 |
|
|
.dx(dx),
|
| 441 |
|
|
.d0(d0),
|
| 442 |
|
|
.d10(d10),
|
| 443 |
|
|
.early_idx(early_idx),
|
| 444 |
|
|
.ontime_idx(ontime_idx),
|
| 445 |
|
|
.man_prog_reset(oc_man_pgm_reset),
|
| 446 |
|
|
.rips(1'b0),
|
| 447 |
|
|
.adder_out(7'b0),
|
| 448 |
|
|
.sel_store_out(7'b0),
|
| 449 |
|
|
.prog_ped_regen(1'b1),
|
| 450 |
|
|
.prog_add(1'b0),
|
| 451 |
|
|
.early_out(ps_early_out),
|
| 452 |
|
|
.ontime_out(ps_ontime_out),
|
| 453 |
|
|
.ped_out(ps_ped_out),
|
| 454 |
|
|
.prog_restart_sig(ps_restart_sig)
|
| 455 |
|
|
);
|
| 456 |
|
|
|
| 457 |
21 |
eightycc |
store_select ss (
|
| 458 |
|
|
.d0(d0),
|
| 459 |
|
|
.d1_dx(d1_dx),
|
| 460 |
|
|
.addr_no_800x(ar_addr_no_800x),
|
| 461 |
|
|
.addr_8000(ar_addr_8000),
|
| 462 |
|
|
.addr_8001(ar_addr_8001),
|
| 463 |
|
|
.addr_8002_8003(ar_addr_8002_8003),
|
| 464 |
|
|
.addr_hot_8000(1'b0),
|
| 465 |
|
|
.acc_ontime(ac_ontime_out),
|
| 466 |
|
|
.dist_ontime(ds_ontime_out),
|
| 467 |
|
|
.gs_out(tr_gs_out),
|
| 468 |
|
|
.console_switches(oc_data_out),
|
| 469 |
|
|
.acc_plus(1'b0),
|
| 470 |
|
|
.acc_minus(1'b0),
|
| 471 |
|
|
.selected_out(ss_selected_out)
|
| 472 |
|
|
);
|
| 473 |
|
|
|
| 474 |
13 |
eightycc |
translators tr (
|
| 475 |
12 |
eightycc |
.dist_early_out(`biq_blank),
|
| 476 |
|
|
.bs_out(`biq_blank),
|
| 477 |
|
|
.console_out(oc_console_out),
|
| 478 |
|
|
.ri_gs(1'b0),
|
| 479 |
|
|
.ri_bs(1'b0),
|
| 480 |
|
|
.ri_console(oc_write_gs),
|
| 481 |
21 |
eightycc |
.n800x(ar_addr_no_800x),
|
| 482 |
|
|
.console_read_gs(oc_read_gs),
|
| 483 |
12 |
eightycc |
.gs_out(gs_out),
|
| 484 |
|
|
.gs_write(tr_gs_write),
|
| 485 |
|
|
.gs_in(tr_gs_in),
|
| 486 |
21 |
eightycc |
.gs_biq_out(tr_gs_out)
|
| 487 |
12 |
eightycc |
);
|
| 488 |
|
|
|
| 489 |
|
|
endmodule
|
