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[/] [image_component_labeling_and_feature_extraction/] [trunk/] [SendFeatures.vhd] - Blame information for rev 2

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:14:03 11/05/2008 
-- Design Name: 
-- Module Name:    SendFeatures - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity SendFeatures is
    Port ( features : in  STD_LOGIC_VECTOR (34 downto 0);
           fsync         : in STD_LOGIC;
                          wstrobe : in  STD_LOGIC;
                          ready : out STD_LOGIC;
           clk : in  STD_LOGIC;
                          reset : in STD_LOGIC;
           RX_DATA : in  STD_LOGIC;
           RTS_IN : in  STD_LOGIC;
           DSR_OUT : out  STD_LOGIC;
           TX_DATA : out  STD_LOGIC;
           CTS_OUT : out  STD_LOGIC);
end SendFeatures;
 
architecture Behavioral of SendFeatures is
 
        signal transdata   : std_logic_vector(7 downto 0);       -- Data to be transmitted
        signal wr                       : std_logic;                                                    -- write strobe
        signal tbe                      : std_logic;                                                    -- transmitt buffer empty
 
        type state_type is (idle, sendB1_A, sendB1_B, sendB1_C, sendB2_A, sendB2_B, sendB2_C,
                                                        sendB3_A, sendB3_B, sendB3_C, sendB4_A, sendB4_B, sendB4_C, sendB5_A,
                                                        sendB5_B, sendB5_C); --state declaration
 
        signal state : state_type := idle;
        signal firstByteInFrame : std_logic := '0';
        signal data_vector : std_logic_vector(34 downto 0);
        signal recdata : std_logic_vector(7 downto 0);
 
begin
 
serial : entity work.UARTcomponent port map (
                        TXD => TX_DATA,                         -- Transmitted serial data output
                RXD => RX_DATA,                         -- Received serial data input
                CLK => clk,                                             -- Clock signal
                        DBIN    => transdata,              -- Input parallel data to be transmitted
                        DBOUT => recdata,                       -- Recevived parallel data output
                        RDA => open,                                    -- Read Data Available
                        TBE => tbe,                                        -- Transfer Buffer Emty
                        RD       => '0',
                        WR       => wr,
                        PE       => open,                                       -- Parity error         
                        FE       => open,                                       -- Frame error
                        OE       => open,                                       -- Overwrite error
                        RST => reset            );                      -- Reset signal
 
                        DSR_OUT <= '1';
                        CTS_OUT <= RTS_IN;
 
sendStates: process(clk,reset)
        -- This process 
 
begin
 
        if reset = '1' then
                state <= idle;
        elsif clk'event and clk = '1' then
                case state is
 
                        when idle => -- Waiting for the feature vector to be ready and the wstrobe
                                if fsync = '1' then
                                        firstByteInFrame <= '1'; -- The most significant bit is set for
                                end if;                                         -- the first byte in the first feature vector for all frames.
                                                                                   -- This bit is thus used for frame syncronization with the 
                                                                                        -- recieving unit on the serial RS232 link.
                                ready <= '1';
                                if wstrobe = '1' then
                                        state <= sendB1_A;
                                        data_vector <= features;
                                end if;
 
                        when sendB1_A => -- Send first byte for feature vector
                                ready <= '0';
                                if tbe = '1' then
                                        state <= sendB1_B;
                                end if;
                        when sendB1_B =>
                                        state <= sendB1_C;
                        when sendB1_C =>
                                if tbe = '1' then
                                        state <= sendB2_A;
                                        firstByteInFrame <= '0';
                                end if;
 
                        when sendB2_A => -- Send second byte for feature vector
                                ready <= '0';
                                if tbe = '1' then
                                        state <= sendB2_B;
                                end if;
                        when sendB2_B =>
                                        state <= sendB2_C;
                        when sendB2_C =>
                                if tbe = '1' then
                                        state <= sendB3_A;
                                end if;
 
                        when sendB3_A => -- Send third byte for feature vector
                                ready <= '0';
                                firstByteInFrame <= '0';
                                if tbe = '1' then
                                        state <= sendB3_B;
                                end if;
                        when sendB3_B =>
                                        state <= sendB3_C;
                        when sendB3_C =>
                                if tbe = '1' then
                                        state <= sendB4_A;
                                end if;
 
                        when sendB4_A => -- Send fourth byte for feature vector
                                ready <= '0';
                                firstByteInFrame <= '0';
                                if tbe = '1' then
                                        state <= sendB4_B;
                                end if;
                        when sendB4_B =>
                                        state <= sendB4_C;
                        when sendB4_C =>
                                if tbe = '1' then
                                        state <= sendB5_A;
                                end if;
 
                        when sendB5_A => -- Send fifth byte for feature vector
                                ready <= '0';
                                firstByteInFrame <= '0';
                                if tbe = '1' then
                                        state <= sendB5_B;
                                end if;
                        when sendB5_B =>
                                        state <= sendB5_C;
                        when sendB5_C =>
                                if tbe = '1' then
                                        state <= idle;
                                end if;
 
                end case;
 
 
        end if; -- of synchronous part
end process; -- sendStates
 
sendOut: process(state)
begin
        case state is
                when idle =>
                        wr <= '0';
                        transdata <= firstByteInFrame&data_vector(34 downto 28);
 
                when sendB1_A => --- Send first byte -----------------
                        transdata <= firstByteInFrame&data_vector(34 downto 28);
                        wr <= '0';
                when sendB1_B => -- Activate strobe 
                   transdata <= firstByteInFrame&data_vector(34 downto 28);
                        wr <= '1';
                when sendB1_C =>
                        transdata <= firstByteInFrame&data_vector(34 downto 28);
                        wr <= '0';
 
                when sendB2_A => --- Send second byte -----------------
                        transdata <= firstByteInFrame&data_vector(27 downto 21);
                        wr <= '0';
                when sendB2_B => -- Activate strobe 
                   transdata <= firstByteInFrame&data_vector(27 downto 21);
                        wr <= '1';
                when sendB2_C =>
                        transdata <= firstByteInFrame&data_vector(27 downto 21);
                        wr <= '0';
 
                when sendB3_A => --- Send third byte -----------------
                        transdata <= firstByteInFrame&data_vector(20 downto 14);
                        wr <= '0';
                when sendB3_B => -- Activate strobe 
                   transdata <= firstByteInFrame&data_vector(20 downto 14);
                        wr <= '1';
                when sendB3_C =>
                        transdata <= firstByteInFrame&data_vector(20 downto 14);
                        wr <= '0';
 
                when sendB4_A => --- Send fourth byte -----------------
                        transdata <= firstByteInFrame&data_vector(13 downto 7);
                        wr <= '0';
                when sendB4_B => -- Activate strobe 
                   transdata <= firstByteInFrame&data_vector(13 downto 7);
                        wr <= '1';
                when sendB4_C =>
                        transdata <= firstByteInFrame&data_vector(13 downto 7);
                        wr <= '0';
 
                when sendB5_A => --- Send fifth byte -----------------
                        transdata <= firstByteInFrame&data_vector(6 downto 0);
                        wr <= '0';
                when sendB5_B => -- Activate strobe 
                   transdata <= firstByteInFrame&data_vector(6 downto 0);
                        wr <= '1';
                when sendB5_C =>
                        transdata <= firstByteInFrame&data_vector(6 downto 0);
                        wr <= '0';
 
                when others =>
                        wr <= '0';
                        transdata <= firstByteInFrame&data_vector(34 downto 28);
        end case;
end process; -- sendOut
 
end Behavioral;
 

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Subversion Repositories image_component_labeling_and_feature_extraction

[/] [image_component_labeling_and_feature_extraction/] [trunk/] [SendFeatures.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	malikpearl	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 13:14:03 11/05/2008`
6			`-- Design Name:`
7			`-- Module Name: SendFeatures - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`---- Uncomment the following library declaration if instantiating`
26			`---- any Xilinx primitives in this code.`
27			`--library UNISIM;`
28			`--use UNISIM.VComponents.all;`
29
30			`entity SendFeatures is`
31			`Port ( features : in STD_LOGIC_VECTOR (34 downto 0);`
32			`fsync : in STD_LOGIC;`
33			`wstrobe : in STD_LOGIC;`
34			`ready : out STD_LOGIC;`
35			`clk : in STD_LOGIC;`
36			`reset : in STD_LOGIC;`
37			`RX_DATA : in STD_LOGIC;`
38			`RTS_IN : in STD_LOGIC;`
39			`DSR_OUT : out STD_LOGIC;`
40			`TX_DATA : out STD_LOGIC;`
41			`CTS_OUT : out STD_LOGIC);`
42			`end SendFeatures;`
43
44			`architecture Behavioral of SendFeatures is`
45
46			`signal transdata : std_logic_vector(7 downto 0); -- Data to be transmitted`
47			`signal wr : std_logic; -- write strobe`
48			`signal tbe : std_logic; -- transmitt buffer empty`
49
50			`type state_type is (idle, sendB1_A, sendB1_B, sendB1_C, sendB2_A, sendB2_B, sendB2_C,`
51			`sendB3_A, sendB3_B, sendB3_C, sendB4_A, sendB4_B, sendB4_C, sendB5_A,`
52			`sendB5_B, sendB5_C); --state declaration`
53
54			`signal state : state_type := idle;`
55			`signal firstByteInFrame : std_logic := '0';`
56			`signal data_vector : std_logic_vector(34 downto 0);`
57			`signal recdata : std_logic_vector(7 downto 0);`
58
59			`begin`
60
61			`serial : entity work.UARTcomponent port map (`
62			`TXD => TX_DATA, -- Transmitted serial data output`
63			`RXD => RX_DATA, -- Received serial data input`
64			`CLK => clk, -- Clock signal`
65			`DBIN => transdata, -- Input parallel data to be transmitted`
66			`DBOUT => recdata, -- Recevived parallel data output`
67			`RDA => open, -- Read Data Available`
68			`TBE => tbe, -- Transfer Buffer Emty`
69			`RD => '0',`
70			`WR => wr,`
71			`PE => open, -- Parity error`
72			`FE => open, -- Frame error`
73			`OE => open, -- Overwrite error`
74			`RST => reset ); -- Reset signal`
75
76			`DSR_OUT <= '1';`
77			`CTS_OUT <= RTS_IN;`
78
79			`sendStates: process(clk,reset)`
80			`-- This process`
81
82			`begin`
83
84			`if reset = '1' then`
85			`state <= idle;`
86			`elsif clk'event and clk = '1' then`
87			`case state is`
88
89			`when idle => -- Waiting for the feature vector to be ready and the wstrobe`
90			`if fsync = '1' then`
91			`firstByteInFrame <= '1'; -- The most significant bit is set for`
92			`end if; -- the first byte in the first feature vector for all frames.`
93			`-- This bit is thus used for frame syncronization with the`
94			`-- recieving unit on the serial RS232 link.`
95			`ready <= '1';`
96			`if wstrobe = '1' then`
97			`state <= sendB1_A;`
98			`data_vector <= features;`
99			`end if;`
100
101			`when sendB1_A => -- Send first byte for feature vector`
102			`ready <= '0';`
103			`if tbe = '1' then`
104			`state <= sendB1_B;`
105			`end if;`
106			`when sendB1_B =>`
107			`state <= sendB1_C;`
108			`when sendB1_C =>`
109			`if tbe = '1' then`
110			`state <= sendB2_A;`
111			`firstByteInFrame <= '0';`
112			`end if;`
113
114			`when sendB2_A => -- Send second byte for feature vector`
115			`ready <= '0';`
116			`if tbe = '1' then`
117			`state <= sendB2_B;`
118			`end if;`
119			`when sendB2_B =>`
120			`state <= sendB2_C;`
121			`when sendB2_C =>`
122			`if tbe = '1' then`
123			`state <= sendB3_A;`
124			`end if;`
125
126			`when sendB3_A => -- Send third byte for feature vector`
127			`ready <= '0';`
128			`firstByteInFrame <= '0';`
129			`if tbe = '1' then`
130			`state <= sendB3_B;`
131			`end if;`
132			`when sendB3_B =>`
133			`state <= sendB3_C;`
134			`when sendB3_C =>`
135			`if tbe = '1' then`
136			`state <= sendB4_A;`
137			`end if;`
138
139			`when sendB4_A => -- Send fourth byte for feature vector`
140			`ready <= '0';`
141			`firstByteInFrame <= '0';`
142			`if tbe = '1' then`
143			`state <= sendB4_B;`
144			`end if;`
145			`when sendB4_B =>`
146			`state <= sendB4_C;`
147			`when sendB4_C =>`
148			`if tbe = '1' then`
149			`state <= sendB5_A;`
150			`end if;`
151
152			`when sendB5_A => -- Send fifth byte for feature vector`
153			`ready <= '0';`
154			`firstByteInFrame <= '0';`
155			`if tbe = '1' then`
156			`state <= sendB5_B;`
157			`end if;`
158			`when sendB5_B =>`
159			`state <= sendB5_C;`
160			`when sendB5_C =>`
161			`if tbe = '1' then`
162			`state <= idle;`
163			`end if;`
164
165			`end case;`
166
167
168			`end if; -- of synchronous part`
169			`end process; -- sendStates`
170
171			`sendOut: process(state)`
172			`begin`
173			`case state is`
174			`when idle =>`
175			`wr <= '0';`
176			`transdata <= firstByteInFrame&data_vector(34 downto 28);`
177
178			`when sendB1_A => --- Send first byte -----------------`
179			`transdata <= firstByteInFrame&data_vector(34 downto 28);`
180			`wr <= '0';`
181			`when sendB1_B => -- Activate strobe`
182			`transdata <= firstByteInFrame&data_vector(34 downto 28);`
183			`wr <= '1';`
184			`when sendB1_C =>`
185			`transdata <= firstByteInFrame&data_vector(34 downto 28);`
186			`wr <= '0';`
187
188			`when sendB2_A => --- Send second byte -----------------`
189			`transdata <= firstByteInFrame&data_vector(27 downto 21);`
190			`wr <= '0';`
191			`when sendB2_B => -- Activate strobe`
192			`transdata <= firstByteInFrame&data_vector(27 downto 21);`
193			`wr <= '1';`
194			`when sendB2_C =>`
195			`transdata <= firstByteInFrame&data_vector(27 downto 21);`
196			`wr <= '0';`
197
198			`when sendB3_A => --- Send third byte -----------------`
199			`transdata <= firstByteInFrame&data_vector(20 downto 14);`
200			`wr <= '0';`
201			`when sendB3_B => -- Activate strobe`
202			`transdata <= firstByteInFrame&data_vector(20 downto 14);`
203			`wr <= '1';`
204			`when sendB3_C =>`
205			`transdata <= firstByteInFrame&data_vector(20 downto 14);`
206			`wr <= '0';`
207
208			`when sendB4_A => --- Send fourth byte -----------------`
209			`transdata <= firstByteInFrame&data_vector(13 downto 7);`
210			`wr <= '0';`
211			`when sendB4_B => -- Activate strobe`
212			`transdata <= firstByteInFrame&data_vector(13 downto 7);`
213			`wr <= '1';`
214			`when sendB4_C =>`
215			`transdata <= firstByteInFrame&data_vector(13 downto 7);`
216			`wr <= '0';`
217
218			`when sendB5_A => --- Send fifth byte -----------------`
219			`transdata <= firstByteInFrame&data_vector(6 downto 0);`
220			`wr <= '0';`
221			`when sendB5_B => -- Activate strobe`
222			`transdata <= firstByteInFrame&data_vector(6 downto 0);`
223			`wr <= '1';`
224			`when sendB5_C =>`
225			`transdata <= firstByteInFrame&data_vector(6 downto 0);`
226			`wr <= '0';`
227
228			`when others =>`
229			`wr <= '0';`
230			`transdata <= firstByteInFrame&data_vector(34 downto 28);`
231			`end case;`
232			`end process; -- sendOut`
233
234			`end Behavioral;`
235