| 1 |
34 |
Abraxas3d |
--k-bit x k-bit Booth multiplier.
|
| 2 |
|
|
|
| 3 |
|
|
entity booth_multiplier is
|
| 4 |
|
|
generic(k : POSITIVE := 7); --input number word length less one
|
| 5 |
|
|
port(multiplicand, multiplier : in BIT_VECTOR(k downto 0);
|
| 6 |
|
|
clock : in BIT; product : inout BIT_VECTOR((2*k + 1) downto 0));
|
| 7 |
|
|
end booth_multiplier;
|
| 8 |
|
|
|
| 9 |
|
|
architecture structural of booth_multiplier is
|
| 10 |
|
|
|
| 11 |
|
|
signal mdreg, adderout, carries, augend, tcbuffout : BIT_VECTOR(k downto 0);
|
| 12 |
|
|
signal mrreg : BIT_VECTOR((k + 1) downto 0);
|
| 13 |
|
|
signal adder_ovfl : BIT;
|
| 14 |
|
|
signal comp ,clr_mr ,load_mr ,shift_mr ,clr_md ,load_md ,clr_pp ,load_pp ,shift_pp : BIT;
|
| 15 |
|
|
signal boostate : NATURAL range 0 to 2*(k + 1);
|
| 16 |
|
|
|
| 17 |
|
|
begin
|
| 18 |
|
|
|
| 19 |
|
|
process --main clocked process containing all sequential elements
|
| 20 |
|
|
begin
|
| 21 |
|
|
wait until (clock'EVENT and clock = '1');
|
| 22 |
|
|
|
| 23 |
|
|
--register to hold multiplicand during multiplication
|
| 24 |
|
|
IF clr_md = '1' THEN
|
| 25 |
|
|
mdreg <= (OTHERS => '0');
|
| 26 |
|
|
ELSIF load_md = '1' THEN
|
| 27 |
|
|
mdreg <= multiplicand;
|
| 28 |
|
|
ELSE
|
| 29 |
|
|
mdreg <= mdreg;
|
| 30 |
|
|
END IF;
|
| 31 |
|
|
|
| 32 |
|
|
--register/shifter to product pair of bits used to control adder
|
| 33 |
|
|
IF clr_mr = '1' THEN
|
| 34 |
|
|
mrreg <= (OTHERS => '0');
|
| 35 |
|
|
ELSIF load_mr = '1' THEN
|
| 36 |
|
|
mrreg((k + 1) DOWNTO 1) <= multiplier;
|
| 37 |
|
|
mrreg(0) <= '0';
|
| 38 |
|
|
ELSIF shift_mr = '1' THEN
|
| 39 |
|
|
mrreg <= mrreg SRL 1;
|
| 40 |
|
|
ELSE
|
| 41 |
|
|
mrreg <= mrreg;
|
| 42 |
|
|
END IF;
|
| 43 |
|
|
|
| 44 |
|
|
--register/shifter accumulates partial product values
|
| 45 |
|
|
IF clr_pp = '1' THEN
|
| 46 |
|
|
product <= (OTHERS => '0');
|
| 47 |
|
|
ELSIF load_pp = '1' THEN
|
| 48 |
|
|
product((2*k + 1) DOWNTO (k + 1)) <= adderout; --add to top half
|
| 49 |
|
|
product(k DOWNTO 0) <= product(k DOWNTO 0); --refresh bootm half
|
| 50 |
|
|
ELSIF shift_pp = '1' THEN
|
| 51 |
|
|
product <= product SRA 1; --shift right with sign extend
|
| 52 |
|
|
ELSE
|
| 53 |
|
|
product <= product;
|
| 54 |
|
|
END IF;
|
| 55 |
|
|
|
| 56 |
|
|
END PROCESS;
|
| 57 |
|
|
|
| 58 |
|
|
--adder adds/subtracts partial product to multiplicand
|
| 59 |
|
|
augend <= product((2*k+1) DOWNTO (k+1));
|
| 60 |
|
|
addgen : FOR i IN adderout'RANGE
|
| 61 |
|
|
GENERATE
|
| 62 |
|
|
lsadder : IF i = 0 GENERATE
|
| 63 |
|
|
adderout(i) <= tcbuffout(i) XOR augend(i) XOR comp;
|
| 64 |
|
|
carries(i) <= (tcbuffout(i) AND augend(i)) OR
|
| 65 |
|
|
(tcbuffout(i) AND comp) OR
|
| 66 |
|
|
(comp AND augend(i));
|
| 67 |
|
|
END GENERATE;
|
| 68 |
|
|
otheradder : IF i /= 0 GENERATE
|
| 69 |
|
|
adderout(i) <= tcbuffout(i) XOR augend(i) XOR carries(i-1);
|
| 70 |
|
|
carries(i) <= (tcbuffout(i) AND augend(i)) OR
|
| 71 |
|
|
(tcbuffout(i) AND carries(i-1)) OR
|
| 72 |
|
|
(carries(i-1) AND augend(i));
|
| 73 |
|
|
END GENERATE;
|
| 74 |
|
|
END GENERATE;
|
| 75 |
|
|
--twos comp overflow bit
|
| 76 |
|
|
adder_ovfl <= carries(k-1) XOR carries(k);
|
| 77 |
|
|
|
| 78 |
|
|
--true/complement buffer to generate two's comp of mdreg
|
| 79 |
|
|
tcbuffout <= NOT mdreg WHEN (comp = '1') ELSE mdreg;
|
| 80 |
|
|
|
| 81 |
|
|
--booth multiplier state counter
|
| 82 |
|
|
PROCESS BEGIN
|
| 83 |
|
|
WAIT UNTIL (clock'EVENT AND clock = '1');
|
| 84 |
|
|
IF boostate < 2*(k + 1) THEN boostate <= boostate + 1;
|
| 85 |
|
|
ELSE boostate <= 0;
|
| 86 |
|
|
END IF;
|
| 87 |
|
|
END PROCESS;
|
| 88 |
|
|
|
| 89 |
|
|
--assign control signal values based on state
|
| 90 |
|
|
PROCESS(boostate)
|
| 91 |
|
|
BEGIN
|
| 92 |
|
|
--assign defaults, all registers refresh
|
| 93 |
|
|
comp <= '0';
|
| 94 |
|
|
clr_mr <= '0';
|
| 95 |
|
|
load_mr <= '0';
|
| 96 |
|
|
shift_mr <= '0';
|
| 97 |
|
|
clr_md <= '0';
|
| 98 |
|
|
load_md <= '0';
|
| 99 |
|
|
clr_pp <= '0';
|
| 100 |
|
|
load_pp <= '0';
|
| 101 |
|
|
shift_pp <= '0';
|
| 102 |
|
|
IF boostate = 0 THEN
|
| 103 |
|
|
load_mr <= '1';
|
| 104 |
|
|
load_md <= '1';
|
| 105 |
|
|
clr_pp <= '1';
|
| 106 |
|
|
ELSIF boostate MOD 2 = 0 THEN --boostate = 2,4,6,8 ....
|
| 107 |
|
|
shift_mr <= '1';
|
| 108 |
|
|
shift_pp <= '1';
|
| 109 |
|
|
ELSE --boostate = 1,3,5,7......
|
| 110 |
|
|
IF mrreg(0) = mrreg(1) THEN
|
| 111 |
|
|
NULL; --refresh pp
|
| 112 |
|
|
ELSE
|
| 113 |
|
|
load_pp <= '1'; --update product
|
| 114 |
|
|
END IF;
|
| 115 |
|
|
comp <= mrreg(1); --subract if mrreg(1 DOWNTO 0) ="10"
|
| 116 |
|
|
END IF;
|
| 117 |
|
|
END PROCESS;
|
| 118 |
|
|
|
| 119 |
|
|
END structural;
|
| 120 |
|
|
|
