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[/] [jt51/] [trunk/] [jt51/] [jt51_mmr.v] - Blame information for rev 2

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/*  This file is part of JT51.
 
    JT51 is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
 
    JT51 is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with JT51.  If not, see <http://www.gnu.org/licenses/>.
 
        Author: Jose Tejada Gomez. Twitter: @topapate
        Version: 1.0
        Date: 27-10-2016
        */
 
`timescale 1ns / 1ps
 
module jt51_mmr(
        input                   rst,
        input                   clk,            // P1
        input   [7:0]    d_in,
        input                   write,
        input                   a0,
        output  reg             busy,
 
        // CT
        output  reg             ct1,
        output  reg             ct2,
 
        // Noise
        output  reg                     ne,
        output  reg [4:0]        nfrq,
 
        // LFO
        output  reg     [7:0]    lfo_freq,
        output  reg     [1:0]    lfo_w,
        output  reg [6:0]        lfo_amd,
        output  reg [6:0]        lfo_pmd,
        output  reg                     lfo_rst,
        // Timers
        output  reg     [9:0]    value_A,
        output  reg     [7:0]    value_B,
        output  reg                     load_A,
        output  reg                     load_B,
        output  reg                     enable_irq_A,
        output  reg                     enable_irq_B,
        output  reg                     clr_flag_A,
        output  reg                     clr_flag_B,
        output  reg                     clr_run_A,
        output  reg                     clr_run_B,
        output  reg                     set_run_A,
        output  reg                     set_run_B,
        input                           flag_A,
 
        `ifdef TEST_SUPPORT
        // Test
        output  reg             test_eg,
        output  reg             test_op0,
        `endif
        // REG
        output  [1:0]    rl_out,
        output  [2:0]    fb_out,
        output  [2:0]    con_out,
        output  [6:0]    kc_out,
        output  [5:0]    kf_out,
        output  [2:0]    pms_out,
        output  [1:0]    ams_out,
        output  [2:0]    dt1_out,
        output  [3:0]    mul_out,
        output  [6:0]    tl_out,
        output  [1:0]    ks_out,
        output  [4:0]    ar_out,
        output                  amsen_out,
        output  [4:0]    d1r_out,
        output  [1:0]    dt2_out,
        output  [4:0]    d2r_out,
        output  [3:0]    d1l_out,
        output  [3:0]    rr_out,
        output                  kon_out,
        output                  koff_out,
 
        output  [1:0]    cur_op,
 
        output                  zero
);
 
reg [7:0] selected_register;
 
reg             up_clr;
reg             up_rl,  up_kc,  up_kf,  up_pms,
                up_dt1, up_tl,  up_ks,  up_dt2,
                up_d1l, up_kon, up_amsen;
 
wire                    busy_reg;
 
parameter       REG_TEST        =       8'h01,
                        REG_TEST2       =       8'h02,
                        REG_KON         =       8'h08,
                        REG_NOISE       =       8'h0f,
                        REG_CLKA1       =       8'h10,
                        REG_CLKA2       =       8'h11,
                        REG_CLKB        =       8'h12,
                        REG_TIMER       =       8'h14,
                        REG_LFRQ        =       8'h18,
                        REG_PMDAMD      =       8'h19,
                        REG_CTW         =       8'h1b;
 
reg     csm;
 
always @(posedge clk) begin : memory_mapped_registers
        if( rst ) begin
                selected_register       <= 8'h0;
                busy                            <= 1'b0;
                { up_rl, up_kc, up_kf, up_pms, up_dt1, up_tl,
                                up_ks, up_amsen, up_dt2, up_d1l, up_kon } <= 11'd0;
                `ifdef TEST_SUPPORT
                { test_eg, test_op0 } <= 2'd0;
                `endif
                // timers
                { value_A, value_B } <= 18'd0;
                { clr_flag_B, clr_flag_A,
                enable_irq_B, enable_irq_A, load_B, load_A } <= 6'd0;
                { clr_run_A, clr_run_B, set_run_A, set_run_B } <= 4'b1100;
                up_clr <= 1'b0;
                // LFO
                { lfo_amd, lfo_pmd }    <= 14'h0;
                lfo_freq                <= 8'd0;
                lfo_w                   <= 2'd0;
                lfo_rst                 <= 1'b0;
                { ct2, ct1 }    <= 2'd0;
                csm                             <= 1'b0;
        end else begin
                // WRITE IN REGISTERS
                if( write && !busy ) begin
                        busy <= 1'b1;
                        if( !a0 )
                                selected_register <= d_in;
                        else begin
                                // Global registers
                                if( selected_register < 8'h20 ) begin
                                        case( selected_register)
                                        // registros especiales
                                        REG_TEST:       lfo_rst <= 1'b1; // regardless of d_in
                                        `ifdef TEST_SUPPORT
                                        REG_TEST2:      { test_op0, test_eg } <= d_in[1:0];
                                        `endif
                                        REG_KON:        up_kon          <= 1'b1;
                                        REG_NOISE:      { ne, nfrq } <= { d_in[7], d_in[4:0] };
                                        REG_CLKA1:      value_A[9:2]<= d_in;
                                        REG_CLKA2:      value_A[1:0]<= d_in[1:0];
                                        REG_CLKB:       value_B         <= d_in;
                                        REG_TIMER: begin
                                                csm     <= d_in[7];
                                                { clr_flag_B, clr_flag_A,
                                                  enable_irq_B, enable_irq_A,
                                                  load_B, load_A } <= d_in[5:0];
                                                  clr_run_A <= ~d_in[0];
                                                  set_run_A <=  d_in[0];
                                                  clr_run_B <= ~d_in[1];
                                                  set_run_B <=  d_in[1];
                                                end
                                        REG_LFRQ:       lfo_freq <= d_in;
                                        REG_PMDAMD: begin
                                                if( !d_in[7] )
                                                        lfo_amd <= d_in[6:0];
                                                else
                                                        lfo_pmd <= d_in[6:0];
                                                end
                                        REG_CTW: begin
                                                { ct2, ct1 } <= d_in[7:6];
                                                lfo_w            <= d_in[1:0];
                                                end
                                        endcase
                                end else
                                // channel registers
                                if( selected_register < 8'h40 ) begin
                                        case( selected_register[4:3] )
                                                2'h0: up_rl     <= 1'b1;
                                                2'h1: up_kc     <= 1'b1;
                                                2'h2: up_kf     <= 1'b1;
                                                2'h3: up_pms<= 1'b1;
                                        endcase
                                end
                                else
                                // operator registers
                                begin
                                        case( selected_register[7:5] )
                                                3'h2: up_dt1    <= 1'b1;
                                                3'h3: up_tl             <= 1'b1;
                                                3'h4: up_ks             <= 1'b1;
                                                3'h5: up_amsen  <= 1'b1;
                                                3'h6: up_dt2    <= 1'b1;
                                                3'h7: up_d1l    <= 1'b1;
                                        endcase
                                end
                        end
                end
                else begin /* clear once-only bits */
                        csm     <= 1'b0;
                        lfo_rst <= 1'b0;
                        { clr_flag_B, clr_flag_A, load_B, load_A } <= 4'd0;
                        { clr_run_A, clr_run_B, set_run_A, set_run_B } <= 4'd0;
 
                        if( |{ up_rl, up_kc, up_kf, up_pms, up_dt1, up_tl,
                                up_ks, up_amsen, up_dt2, up_d1l, up_kon } == 1'b0 )
                                busy    <= busy_reg;
                        else
                                busy    <= 1'b1;
 
                        if( busy_reg ) begin
                                up_clr <= 1'b1;
                        end
                        else begin
                                up_clr <= 1'b0;
                                if( up_clr      )
                                { up_rl, up_kc, up_kf, up_pms, up_dt1, up_tl,
                                        up_ks, up_amsen, up_dt2, up_d1l, up_kon } <= 11'd0;
                        end
                end
        end
end
 
jt51_reg u_reg(
        .rst    ( rst           ),
        .clk    ( clk           ),                              // P1
        .d_in   ( d_in          ),
 
        .up_rl( up_rl ),
        .up_kc( up_kc ),
        .up_kf( up_kf ),
        .up_pms( up_pms ),
        .up_dt1( up_dt1 ),
        .up_tl( up_tl ),
        .up_ks( up_ks ),
        .up_amsen( up_amsen ),
        .up_dt2( up_dt2 ),
        .up_d1l( up_d1l ),
        .up_kon( up_kon ),
        .op( selected_register[4:3] ),          // operator to update
        .ch( selected_register[2:0] ),           // channel to update
 
        .csm    ( csm           ),
        .flag_A ( flag_A        ),
 
        .busy(  busy_reg ),
        .rl_out( rl_out ),
        .fb_out( fb_out ),
        .con_out( con_out ),
        .kc_out( kc_out ),
        .kf_out( kf_out ),
        .pms_out( pms_out ),
        .ams_out( ams_out ),
        .dt1_out( dt1_out ),
        .mul_out( mul_out ),
        .tl_out( tl_out ),
        .ks_out( ks_out ),
        .ar_out( ar_out ),
        .amsen_out( amsen_out ),
        .d1r_out( d1r_out ),
        .dt2_out( dt2_out ),
        .d2r_out( d2r_out ),
        .d1l_out( d1l_out ),
        .rr_out( rr_out ),
        .kon_out(kon_out),
        .koff_out(koff_out),
 
        .cur_op(cur_op),
        .zero(zero)
);
 
endmodule

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[/] [jt51/] [trunk/] [jt51/] [jt51_mmr.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	gryzor	`/* This file is part of JT51.`
2
3			`JT51 is free software: you can redistribute it and/or modify`
4			`it under the terms of the GNU General Public License as published by`
5			`the Free Software Foundation, either version 3 of the License, or`
6			`(at your option) any later version.`
7
8			`JT51 is distributed in the hope that it will be useful,`
9			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
10			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
11			`GNU General Public License for more details.`
12
13			`You should have received a copy of the GNU General Public License`
14			`along with JT51. If not, see <http://www.gnu.org/licenses/>.`
15
16			`Author: Jose Tejada Gomez. Twitter: @topapate`
17			`Version: 1.0`
18			`Date: 27-10-2016`
19			`*/`
20
21			`timescale 1ns / 1ps
22
23			`module jt51_mmr(`
24			`input rst,`
25			`input clk, // P1`
26			`input [7:0] d_in,`
27			`input write,`
28			`input a0,`
29			`output reg busy,`
30
31			`// CT`
32			`output reg ct1,`
33			`output reg ct2,`
34
35			`// Noise`
36			`output reg ne,`
37			`output reg [4:0] nfrq,`
38
39			`// LFO`
40			`output reg [7:0] lfo_freq,`
41			`output reg [1:0] lfo_w,`
42			`output reg [6:0] lfo_amd,`
43			`output reg [6:0] lfo_pmd,`
44			`output reg lfo_rst,`
45			`// Timers`
46			`output reg [9:0] value_A,`
47			`output reg [7:0] value_B,`
48			`output reg load_A,`
49			`output reg load_B,`
50			`output reg enable_irq_A,`
51			`output reg enable_irq_B,`
52			`output reg clr_flag_A,`
53			`output reg clr_flag_B,`
54			`output reg clr_run_A,`
55			`output reg clr_run_B,`
56			`output reg set_run_A,`
57			`output reg set_run_B,`
58			`input flag_A,`
59
60			`ifdef TEST_SUPPORT
61			`// Test`
62			`output reg test_eg,`
63			`output reg test_op0,`
64			`endif
65			`// REG`
66			`output [1:0] rl_out,`
67			`output [2:0] fb_out,`
68			`output [2:0] con_out,`
69			`output [6:0] kc_out,`
70			`output [5:0] kf_out,`
71			`output [2:0] pms_out,`
72			`output [1:0] ams_out,`
73			`output [2:0] dt1_out,`
74			`output [3:0] mul_out,`
75			`output [6:0] tl_out,`
76			`output [1:0] ks_out,`
77			`output [4:0] ar_out,`
78			`output amsen_out,`
79			`output [4:0] d1r_out,`
80			`output [1:0] dt2_out,`
81			`output [4:0] d2r_out,`
82			`output [3:0] d1l_out,`
83			`output [3:0] rr_out,`
84			`output kon_out,`
85			`output koff_out,`
86
87			`output [1:0] cur_op,`
88
89			`output zero`
90			`);`
91
92			`reg [7:0] selected_register;`
93
94			`reg up_clr;`
95			`reg up_rl, up_kc, up_kf, up_pms,`
96			`up_dt1, up_tl, up_ks, up_dt2,`
97			`up_d1l, up_kon, up_amsen;`
98
99			`wire busy_reg;`
100
101			`parameter REG_TEST = 8'h01,`
102			`REG_TEST2 = 8'h02,`
103			`REG_KON = 8'h08,`
104			`REG_NOISE = 8'h0f,`
105			`REG_CLKA1 = 8'h10,`
106			`REG_CLKA2 = 8'h11,`
107			`REG_CLKB = 8'h12,`
108			`REG_TIMER = 8'h14,`
109			`REG_LFRQ = 8'h18,`
110			`REG_PMDAMD = 8'h19,`
111			`REG_CTW = 8'h1b;`
112
113			`reg csm;`
114
115			`always @(posedge clk) begin : memory_mapped_registers`
116			`if( rst ) begin`
117			`selected_register <= 8'h0;`
118			`busy <= 1'b0;`
119			`{ up_rl, up_kc, up_kf, up_pms, up_dt1, up_tl,`
120			`up_ks, up_amsen, up_dt2, up_d1l, up_kon } <= 11'd0;`
121			`ifdef TEST_SUPPORT
122			`{ test_eg, test_op0 } <= 2'd0;`
123			`endif
124			`// timers`
125			`{ value_A, value_B } <= 18'd0;`
126			`{ clr_flag_B, clr_flag_A,`
127			`enable_irq_B, enable_irq_A, load_B, load_A } <= 6'd0;`
128			`{ clr_run_A, clr_run_B, set_run_A, set_run_B } <= 4'b1100;`
129			`up_clr <= 1'b0;`
130			`// LFO`
131			`{ lfo_amd, lfo_pmd } <= 14'h0;`
132			`lfo_freq <= 8'd0;`
133			`lfo_w <= 2'd0;`
134			`lfo_rst <= 1'b0;`
135			`{ ct2, ct1 } <= 2'd0;`
136			`csm <= 1'b0;`
137			`end else begin`
138			`// WRITE IN REGISTERS`
139			`if( write && !busy ) begin`
140			`busy <= 1'b1;`
141			`if( !a0 )`
142			`selected_register <= d_in;`
143			`else begin`
144			`// Global registers`
145			`if( selected_register < 8'h20 ) begin`
146			`case( selected_register)`
147			`// registros especiales`
148			`REG_TEST: lfo_rst <= 1'b1; // regardless of d_in`
149			`ifdef TEST_SUPPORT
150			`REG_TEST2: { test_op0, test_eg } <= d_in[1:0];`
151			`endif
152			`REG_KON: up_kon <= 1'b1;`
153			`REG_NOISE: { ne, nfrq } <= { d_in[7], d_in[4:0] };`
154			`REG_CLKA1: value_A[9:2]<= d_in;`
155			`REG_CLKA2: value_A[1:0]<= d_in[1:0];`
156			`REG_CLKB: value_B <= d_in;`
157			`REG_TIMER: begin`
158			`csm <= d_in[7];`
159			`{ clr_flag_B, clr_flag_A,`
160			`enable_irq_B, enable_irq_A,`
161			`load_B, load_A } <= d_in[5:0];`
162			`clr_run_A <= ~d_in[0];`
163			`set_run_A <= d_in[0];`
164			`clr_run_B <= ~d_in[1];`
165			`set_run_B <= d_in[1];`
166			`end`
167			`REG_LFRQ: lfo_freq <= d_in;`
168			`REG_PMDAMD: begin`
169			`if( !d_in[7] )`
170			`lfo_amd <= d_in[6:0];`
171			`else`
172			`lfo_pmd <= d_in[6:0];`
173			`end`
174			`REG_CTW: begin`
175			`{ ct2, ct1 } <= d_in[7:6];`
176			`lfo_w <= d_in[1:0];`
177			`end`
178			`endcase`
179			`end else`
180			`// channel registers`
181			`if( selected_register < 8'h40 ) begin`
182			`case( selected_register[4:3] )`
183			`2'h0: up_rl <= 1'b1;`
184			`2'h1: up_kc <= 1'b1;`
185			`2'h2: up_kf <= 1'b1;`
186			`2'h3: up_pms<= 1'b1;`
187			`endcase`
188			`end`
189			`else`
190			`// operator registers`
191			`begin`
192			`case( selected_register[7:5] )`
193			`3'h2: up_dt1 <= 1'b1;`
194			`3'h3: up_tl <= 1'b1;`
195			`3'h4: up_ks <= 1'b1;`
196			`3'h5: up_amsen <= 1'b1;`
197			`3'h6: up_dt2 <= 1'b1;`
198			`3'h7: up_d1l <= 1'b1;`
199			`endcase`
200			`end`
201			`end`
202			`end`
203			`else begin /* clear once-only bits */`
204			`csm <= 1'b0;`
205			`lfo_rst <= 1'b0;`
206			`{ clr_flag_B, clr_flag_A, load_B, load_A } <= 4'd0;`
207			`{ clr_run_A, clr_run_B, set_run_A, set_run_B } <= 4'd0;`
208
209			`if( \|{ up_rl, up_kc, up_kf, up_pms, up_dt1, up_tl,`
210			`up_ks, up_amsen, up_dt2, up_d1l, up_kon } == 1'b0 )`
211			`busy <= busy_reg;`
212			`else`
213			`busy <= 1'b1;`
214
215			`if( busy_reg ) begin`
216			`up_clr <= 1'b1;`
217			`end`
218			`else begin`
219			`up_clr <= 1'b0;`
220			`if( up_clr )`
221			`{ up_rl, up_kc, up_kf, up_pms, up_dt1, up_tl,`
222			`up_ks, up_amsen, up_dt2, up_d1l, up_kon } <= 11'd0;`
223			`end`
224			`end`
225			`end`
226			`end`
227
228			`jt51_reg u_reg(`
229			`.rst ( rst ),`
230			`.clk ( clk ), // P1`
231			`.d_in ( d_in ),`
232
233			`.up_rl( up_rl ),`
234			`.up_kc( up_kc ),`
235			`.up_kf( up_kf ),`
236			`.up_pms( up_pms ),`
237			`.up_dt1( up_dt1 ),`
238			`.up_tl( up_tl ),`
239			`.up_ks( up_ks ),`
240			`.up_amsen( up_amsen ),`
241			`.up_dt2( up_dt2 ),`
242			`.up_d1l( up_d1l ),`
243			`.up_kon( up_kon ),`
244			`.op( selected_register[4:3] ), // operator to update`
245			`.ch( selected_register[2:0] ), // channel to update`
246
247			`.csm ( csm ),`
248			`.flag_A ( flag_A ),`
249
250			`.busy( busy_reg ),`
251			`.rl_out( rl_out ),`
252			`.fb_out( fb_out ),`
253			`.con_out( con_out ),`
254			`.kc_out( kc_out ),`
255			`.kf_out( kf_out ),`
256			`.pms_out( pms_out ),`
257			`.ams_out( ams_out ),`
258			`.dt1_out( dt1_out ),`
259			`.mul_out( mul_out ),`
260			`.tl_out( tl_out ),`
261			`.ks_out( ks_out ),`
262			`.ar_out( ar_out ),`
263			`.amsen_out( amsen_out ),`
264			`.d1r_out( d1r_out ),`
265			`.dt2_out( dt2_out ),`
266			`.d2r_out( d2r_out ),`
267			`.d1l_out( d1l_out ),`
268			`.rr_out( rr_out ),`
269			`.kon_out(kon_out),`
270			`.koff_out(koff_out),`
271
272			`.cur_op(cur_op),`
273			`.zero(zero)`
274			`);`
275
276			`endmodule`