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[/] [jt51/] [trunk/] [jt51/] [jt51_noise.v] - Blame information for rev 2

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/*  This file is part of JT51.
 
    JT51 is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
 
    JT51 is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with JT51.  If not, see <http://www.gnu.org/licenses/>.
 
        Author: Jose Tejada Gomez. Twitter: @topapate
        Version: 1.0
        Date: 27-10-2016
        */
 
`timescale 1ns / 1ps
 
/*
 
        tab size 4
 
        See xapp052.pdf from Xilinx
 
        The NFRQ formula in the App. Note does not make sense:
        Output rate is 55kHz but for NFRQ=1 the formula states that
        the noise is 111kHz, twice the output rate per channel.
 
        That would suggest that the noise for LEFT and RIGHT are
        different but the rest of the system suggest that LEFT and
        RIGHT outputs are calculated at the same time, based on the
        same OP output.
 
        Also, the block diagram states a 1 bit serial input from
        EG to NOISE and that seems unnecessary too.
 
        I have not been able to measure noise in actual chip because
        operator 31 does not produce any output on my two chips.
 
*/
 
module jt51_noise(
        input   rst,
        input   clk,
        input   zero,
        input   ne,
        input   [4:0] nfrq,
        input   [9:0]    eg,
        output  [9:0]    out,
        output                  op31_acc
);
 
reg [9:0] limit;
wire zero_out;
 
always @(posedge clk)
        if( ne ) begin
                if( zero_out )
                        casex ( ~eg )
                                10'b1xxxxxxxxx:  limit <= 10'h3FF;
                                10'b01xxxxxxxx:  limit <= 10'h1FF;
                                10'b001xxxxxxx:  limit <= 10'h0FF;
                                10'b0001xxxxxx:  limit <= 10'h07F;
                                10'b00001xxxxx:  limit <= 10'h03F;
                                10'b000001xxxx:  limit <= 10'h01F;
                                10'b0000001xxx:  limit <= 10'h00F;
                                10'b00000001xx:  limit <= 10'h007;
                                10'b000000001x:  limit <= 10'h003;
                                10'b0000000001:  limit <= 10'h001;
                        endcase
        end
        else limit <= 10'd0;
 
 
reg             base;
reg [4:0]        cnt;
 
always @(posedge clk)
        if( rst ) begin
                base <= 1'b0;
                cnt  <= 5'b1;
        end
        else begin
                if( zero_out ) begin
                        if ( cnt==nfrq && nfrq!=5'd0 ) begin
                                base <= ~base;
                                cnt  <= 5'b1;
                        end
                        else cnt <= cnt + 1'b1;
                end
        end
 
wire [9:0] pre;
 
assign  out = pre & limit;
 
genvar aux;
generate
for( aux=0; aux<10; aux=aux+1) begin : noise_lfsr
        jt51_noise_lfsr #(.init(aux*29+97*aux*aux*aux)) u_lfsr (
                .rst    ( rst ),
                .clk    ( clk ),
                .base   ( base ),
                .out    ( pre[aux] )
        );
end
endgenerate
 
// shift ZERO to make it match the output of OP31 from EG
jt51_sh #( .width(1), .stages(5) ) u_zerosh(
        .clk    ( clk           ),
        .din    ( zero          ),
    .drop       ( zero_out      )
);
 
jt51_sh #( .width(1), .stages(7) ) u_op31sh(
        .clk    ( clk           ),
        .din    ( zero_out      ),
    .drop       ( op31_acc      )
);
 
endmodule

Line No.	Rev	Author	Line
1	2	gryzor	`/* This file is part of JT51.`
2
3			`JT51 is free software: you can redistribute it and/or modify`
4			`it under the terms of the GNU General Public License as published by`
5			`the Free Software Foundation, either version 3 of the License, or`
6			`(at your option) any later version.`
7
8			`JT51 is distributed in the hope that it will be useful,`
9			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
10			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
11			`GNU General Public License for more details.`
12
13			`You should have received a copy of the GNU General Public License`
14			`along with JT51. If not, see <http://www.gnu.org/licenses/>.`
15
16			`Author: Jose Tejada Gomez. Twitter: @topapate`
17			`Version: 1.0`
18			`Date: 27-10-2016`
19			`*/`
20
21			`timescale 1ns / 1ps
22
23			`/*`
24
25			`tab size 4`
26
27			`See xapp052.pdf from Xilinx`
28
29			`The NFRQ formula in the App. Note does not make sense:`
30			`Output rate is 55kHz but for NFRQ=1 the formula states that`
31			`the noise is 111kHz, twice the output rate per channel.`
32
33			`That would suggest that the noise for LEFT and RIGHT are`
34			`different but the rest of the system suggest that LEFT and`
35			`RIGHT outputs are calculated at the same time, based on the`
36			`same OP output.`
37
38			`Also, the block diagram states a 1 bit serial input from`
39			`EG to NOISE and that seems unnecessary too.`
40
41			`I have not been able to measure noise in actual chip because`
42			`operator 31 does not produce any output on my two chips.`
43
44			`*/`
45
46			`module jt51_noise(`
47			`input rst,`
48			`input clk,`
49			`input zero,`
50			`input ne,`
51			`input [4:0] nfrq,`
52			`input [9:0] eg,`
53			`output [9:0] out,`
54			`output op31_acc`
55			`);`
56
57			`reg [9:0] limit;`
58			`wire zero_out;`
59
60			`always @(posedge clk)`
61			`if( ne ) begin`
62			`if( zero_out )`
63			`casex ( ~eg )`
64			`10'b1xxxxxxxxx: limit <= 10'h3FF;`
65			`10'b01xxxxxxxx: limit <= 10'h1FF;`
66			`10'b001xxxxxxx: limit <= 10'h0FF;`
67			`10'b0001xxxxxx: limit <= 10'h07F;`
68			`10'b00001xxxxx: limit <= 10'h03F;`
69			`10'b000001xxxx: limit <= 10'h01F;`
70			`10'b0000001xxx: limit <= 10'h00F;`
71			`10'b00000001xx: limit <= 10'h007;`
72			`10'b000000001x: limit <= 10'h003;`
73			`10'b0000000001: limit <= 10'h001;`
74			`endcase`
75			`end`
76			`else limit <= 10'd0;`
77
78
79			`reg base;`
80			`reg [4:0] cnt;`
81
82			`always @(posedge clk)`
83			`if( rst ) begin`
84			`base <= 1'b0;`
85			`cnt <= 5'b1;`
86			`end`
87			`else begin`
88			`if( zero_out ) begin`
89			`if ( cnt==nfrq && nfrq!=5'd0 ) begin`
90			`base <= ~base;`
91			`cnt <= 5'b1;`
92			`end`
93			`else cnt <= cnt + 1'b1;`
94			`end`
95			`end`
96
97			`wire [9:0] pre;`
98
99			`assign out = pre & limit;`
100
101			`genvar aux;`
102			`generate`
103			`for( aux=0; aux<10; aux=aux+1) begin : noise_lfsr`
104			`jt51_noise_lfsr #(.init(aux29+97auxauxaux)) u_lfsr (`
105			`.rst ( rst ),`
106			`.clk ( clk ),`
107			`.base ( base ),`
108			`.out ( pre[aux] )`
109			`);`
110			`end`
111			`endgenerate`
112
113			`// shift ZERO to make it match the output of OP31 from EG`
114			`jt51_sh #( .width(1), .stages(5) ) u_zerosh(`
115			`.clk ( clk ),`
116			`.din ( zero ),`
117			`.drop ( zero_out )`
118			`);`
119
120			`jt51_sh #( .width(1), .stages(7) ) u_op31sh(`
121			`.clk ( clk ),`
122			`.din ( zero_out ),`
123			`.drop ( op31_acc )`
124			`);`
125
126			`endmodule`

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[/] [jt51/] [trunk/] [jt51/] [jt51_noise.v] - Blame information for rev 2