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[/] [jt51/] [trunk/] [jt51/] [jt51_op.v] - Blame information for rev 2

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1 2 gryzor 
/*  This file is part of JT51.
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    JT51 is free software: you can redistribute it and/or modify
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    it under the terms of the GNU General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    JT51 is distributed in the hope that it will be useful,
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    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with JT51.  If not, see <http://www.gnu.org/licenses/>.
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        Author: Jose Tejada Gomez. Twitter: @topapate
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        Version: 1.0
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        Date: 27-10-2016
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        */
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`timescale 1ns / 1ps
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/*
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        Pipeline operator
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*/
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module jt51_op(
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        `ifdef TEST_SUPPORT
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        input                           test_eg,
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        input                           test_op0,
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        `endif
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        input                   clk,            // P1
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        input           [19:0]   phase_cnt,
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        input           [2:0]    con,
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        input           [1:0]    cur_op,
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        input           [2:0]    fb,
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        // volume
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        input           [9:0]    eg,
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        // output data
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        output reg      signed  [13:0]   out
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);
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reg     [ 9:0]   phase;
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reg [ 4:0]       log_msb, log_msb2;
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reg [12:0]       pre; // preattenuation value
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reg [3:0]        sign;
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reg     [12:0]   out_abs;
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reg     [7:0]    phase_addr;
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wire    [11:0]   log_val;        // sine mantisa, in 2's complement
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jt51_sintable u_sintable(
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        .phase   ( phase_addr   ),
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        .log_val ( log_val      )
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);
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reg     [7:0]    pow_addr;
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wire    [12:0]   pow_val;
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jt51_exptable u_exptable(
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        .pow_addr( pow_addr     ),
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        .pow_val ( pow_val      )
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);
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reg     [9:0]    eg_II, eg_III;
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`ifdef TEST_SUPPORT
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reg     [9:0]    eg_IV, eg_V, eg_VI;
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`endif
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reg     signed  [19:0]   modulation;
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wire    [2:0]    con_I, con_VII;
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wire    [1:0]    cur_op_VII, cur_op_I;
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wire    [2:0]    fb_I;
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parameter mod_lat = 5; /* latency */
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parameter mod_stg = 5*8-mod_lat; /* stages */
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reg     [14*mod_stg-1:0] mod;
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wire signed [13:0] mod1 = mod[ (16-mod_lat)*14-1: (15-mod_lat)*14 ];
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wire signed [13:0] mod2 = mod[ (24-mod_lat)*14-1: (23-mod_lat)*14 ];
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wire signed [13:0] mod3 = mod[ (32-mod_lat)*14-1: (31-mod_lat)*14 ];
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wire signed [13:0] mod4 = mod[ (40-mod_lat)*14-1: (39-mod_lat)*14 ];
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wire signed [13:0] mod7;
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wire mod7_en = cur_op_I==2'd0;
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jt51_sh2 #( .width(14), .stages(8) ) u_mod7sh(
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        .clk    ( clk   ),
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        .en             ( mod7_en ),
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        .ld             ( 1'b1  ),
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        .din    ( mod3  ),
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    .drop       ( mod7  )
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);
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parameter M1=2'd0, M2=2'd1, C1=02'd2, C2=2'd3;
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always @(*) begin
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        case( cur_op_I )
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                default: // M1, FL
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                        case( fb_I )
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                                3'd0: modulation <= 20'd0;
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                                3'd1: modulation <= (mod3+mod7)<<1;
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                                3'd2: modulation <= (mod3+mod7)<<2;
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                                3'd3: modulation <= (mod3+mod7)<<3;
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                                3'd4: modulation <= (mod3+mod7)<<4;
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                                3'd5: modulation <= (mod3+mod7)<<5;
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                                3'd6: modulation <= (mod3+mod7)<<6;
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                                3'd7: modulation <= (mod3+mod7)<<7;
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                        endcase
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                C1: case(con_I)
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                                3'd7, 3'd2, 3'd1:
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                                        modulation <= 20'd0;
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                                default:
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                                        modulation <= mod1<<9; // M1
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                        endcase
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                C2: case(con_I)
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                                default: // 3'd4, 3'd1, 3'd0:
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                                        modulation <= mod1<<9; // M2
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                                3'd2:
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                                        modulation <= (mod1+mod2)<<9; // M2+M1
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                                3'd3:
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                                        modulation <= (mod1+mod4)<<9; // M2+C1
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                                3'd5:
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                                        modulation <= mod2<<9; // M1
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                                3'd7, 3'd6:
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                                        modulation <= 20'd0;
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                        endcase
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                M2: case(con_I)
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                                default: // 3'd2, 3'd0:
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                                        modulation <= mod2<<9; // C1
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                                3'd1:
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                                        modulation <= (mod2+mod4)<<9; // C1+M1
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                                3'd5:
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                                        modulation <= mod4<<9; // M1
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                                3'd7, 3'd6, 3'd4, 3'd3:
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                                        modulation <= 20'd0;
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                        endcase
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        endcase
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end
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always @(posedge clk) begin
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        // I
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        phase <= (phase_cnt + modulation)>>10;
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        eg_II <= eg;
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        // II
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        phase_addr      <= phase[8]? ~phase[7:0]:phase[7:0];
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        sign[0]          <= phase[9];
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        eg_III <= eg_II;
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        // III
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        { log_msb, pow_addr } <= log_val[11:0] + { eg_III, 2'b0};
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        sign[1] <= sign[0];
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        `ifdef TEST_SUPPORT
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        eg_IV <= eg_III;
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        `endif
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        // IV
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        pre             <= pow_val;
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        log_msb2<= log_msb;
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        sign[2] <= sign[1];
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        `ifdef TEST_SUPPORT
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        eg_V <= eg_IV;
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        `endif
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        // V
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        case( log_msb2 )
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                5'h0: out_abs <= pre;
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                5'h1: out_abs <= pre >> 1;
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                5'h2: out_abs <= pre >> 2;
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                5'h3: out_abs <= pre >> 3;
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                5'h4: out_abs <= pre >> 4;
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                5'h5: out_abs <= pre >> 5;
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                5'h6: out_abs <= pre >> 6;
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                5'h7: out_abs <= pre >> 7;
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                5'h8: out_abs <= pre >> 8;
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                5'h9: out_abs <= pre >> 9;
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                5'hA: out_abs <= pre >> 10;
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                5'hB: out_abs <= pre >> 11;
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                5'hC: out_abs <= pre >> 12;
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                default: out_abs <= 13'd0;
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        endcase
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        sign[3] <= sign[2];
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        `ifdef TEST_SUPPORT
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        eg_VI <= eg_V;
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        `endif
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        // VI
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    mod[14*mod_stg-1:14] <= mod[14*(mod_stg-1)-1:0];
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        `ifdef TEST_SUPPORT
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        if( test_eg)
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                mod[14-1:0]      <= eg_VI;
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        else
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        `endif
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                mod[14-1:0]      <= sign[3] ? ~{1'b0,out_abs}+1'b1 : {1'b0,out_abs} ;
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        // VII
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        `ifdef TEST_SUPPORT
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        if( test_op0 ) begin
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                if( cur_op_VII==3'd0)
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                        out <= mod[14-1:0];
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                else
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                        out <= 14'd0;
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        end
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        else
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        `endif
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        case( con_VII )
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                3'd0, 3'd1, 3'd2, 3'd3:
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                        if( cur_op_VII!=2'd3 )
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                                out <= 14'd0;
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                        else
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                                out <= mod[14-1:0];
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                3'd4:
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                        if( cur_op_VII==2'd0 || cur_op_VII==2'd1 )
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                                out <= 14'd0;
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                        else
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                                out <= mod[14-1:0];
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                3'd5, 3'd6:
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                        if( cur_op_VII==2'd0 )
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                                out <= 14'd0;
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                        else
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                                out <= mod[14-1:0];
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                3'd7:   out <= mod[14-1:0];
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        endcase
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end
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jt51_sh #( .width(8), .stages(7) ) u_con1sh(
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        .clk    ( clk   ),
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        .din    ( { con, cur_op, fb }   ),
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    .drop       ( { con_I, cur_op_I, fb_I } )
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);
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jt51_sh #( .width(5), .stages(6) ) u_con7sh(
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        .clk    ( clk   ),
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        .din    ( { con_I, cur_op_I }   ),
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    .drop       ( { con_VII, cur_op_VII } )
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);
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endmodule

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