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robfinch |
// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// KLC32 - 32 bit CPU
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// EXECUTE.v
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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EXECUTE:
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begin
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state <= WRITEBACK;
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case(opcode)
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`R:
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begin
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case(func)
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`ABS: res <= a[31] ? -a : a;
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`SGN: res <= a[31] ? 32'hFFFFFFFF : |a;
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`NEG: res <= -a;
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`NOT: res <= ~a;
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`EXTB: res <= {{24{a[7]}},a[7:0]};
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`EXTH: res <= {{16{a[15]}},a[15:0]};
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10 |
robfinch |
`MFSPR:
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casex(ir[25:21])
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5'b00xxx: res <= GetCr(ir[23:21]);
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5'b01000: res <= cr;
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5'b01001: res <= usp;
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5'b01010:
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if (!sf) begin
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vector <= `PRIVILEGE_VIOLATION;
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state <= TRAP;
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end
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else begin
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res <= im;
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end
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12 |
robfinch |
5'b01011: res <= be_addr;
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5'b01111: res <= tick;
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endcase
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`MTSPR:
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casex(ir[20:16])
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5'b00xxx: // MTSPR CRn,Rn
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begin
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state <= IFETCH;
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case(ir[18:16])
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3'd0: cr0 <= a[3:0];
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3'd1: cr1 <= a[3:0];
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3'd2: cr2 <= a[3:0];
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3'd3: cr3 <= a[3:0];
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3'd4: cr4 <= a[3:0];
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3'd5: cr5 <= a[3:0];
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3'd6: cr6 <= a[3:0];
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3'd7: cr7 <= a[3:0];
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endcase
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end
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5'b01000: // MTSPR CR,Rn
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begin
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state <= IFETCH;
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cr0 <= a[3:0];
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cr1 <= a[7:4];
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cr2 <= a[11:8];
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cr3 <= a[15:12];
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cr4 <= a[19:16];
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cr5 <= a[23:20];
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cr6 <= a[27:24];
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cr7 <= a[31:28];
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end
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5'b01001: usp <= a; // MTSPR USP,Rn
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5'b01010:
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if (!sf) begin
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vector <= `PRIVILEGE_VIOLATION;
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state <= TRAP;
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end
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else begin
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im <= a[2:0];
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state <= IFETCH;
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end
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endcase
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2 |
robfinch |
`EXEC:
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begin
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ir <= a;
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Rn <= a[25:21];
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state <= REGFETCHA;
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end
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`MOV_CRn2CRn:
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begin
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state <= IFETCH;
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case(ir[18:16])
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3'd0: cr0 <= GetCr(ir[23:21]);
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3'd1: cr1 <= GetCr(ir[23:21]);
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3'd2: cr2 <= GetCr(ir[23:21]);
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3'd3: cr3 <= GetCr(ir[23:21]);
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3'd4: cr4 <= GetCr(ir[23:21]);
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3'd5: cr5 <= GetCr(ir[23:21]);
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3'd6: cr6 <= GetCr(ir[23:21]);
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3'd7: cr7 <= GetCr(ir[23:21]);
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endcase
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end
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10 |
robfinch |
default: res <= 32'd0;
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2 |
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endcase
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end
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`RR:
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begin
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case(func)
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`ADD: res <= a + b;
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`SUB: res <= a - b;
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`CMP: res <= a - b;
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`AND: res <= a & b;
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`ANDC: res <= a & ~b;
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`OR: res <= a | b;
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`ORC: res <= a | ~b;
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`EOR: res <= a ^ b;
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`NAND: res <= ~(a & b);
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`NOR: res <= ~(a | b);
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`ENOR: res <= ~(a ^ b);
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`SHL: res <= shlo[31: 0];
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`SHR: res <= shro[63:32];
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`ROL: res <= shlo[31:0]|shlo[63:32];
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`ROR: res <= shro[31:0]|shro[63:32];
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`MIN: res <= as < bs ? as : bs;
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`MAX: res <= as < bs ? bs : as;
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`BCDADD: res <= bcdaddo;
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`BCDSUB: res <= bcdsubo;
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default: res <= 32'd0;
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endcase
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if (func==`JMP_RR) begin
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pc <= a + b;
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pc[1:0] <= 2'b00;
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state <= IFETCH;
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end
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else if (func==`JSR_RR) begin
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tgt <= a + b;
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tgt[1:0] <= 2'b00;
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state <= JSR1;
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end
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case(func)
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`LWX: begin ea <= a + b; mopcode <= `LW; state <= MEMORY1; end
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`LHX: begin ea <= a + b; mopcode <= `LH; state <= MEMORY1; end
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`LHUX: begin ea <= a + b; mopcode <= `LHU; state <= MEMORY1; end
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`LBX: begin ea <= a + b; mopcode <= `LB; state <= MEMORY1; end
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`LBUX: begin ea <= a + b; mopcode <= `LBU; state <= MEMORY1; end
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`SBX: begin ea <= a + b; mopcode <= `SB; b <= c; state <= MEMORY1; end
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`SHX: begin ea <= a + b; mopcode <= `SH; b <= c; state <= MEMORY1; end
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`SWX: begin ea <= a + b; mopcode <= `SW; b <= c; state <= MEMORY1; end
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10 |
robfinch |
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`MULU: state <= MULTDIV1;
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`MULS: state <= MULTDIV1;
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`MULUH: state <= MULTDIV1;
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`MULSH: state <= MULTDIV1;
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`DIVU: state <= MULTDIV1;
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`DIVS: state <= MULTDIV1;
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`MODU: state <= MULTDIV1;
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`MODS: state <= MULTDIV1;
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2 |
robfinch |
endcase
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end
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`SETcc:
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begin
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case(cond)
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`SET: res <= 32'd1;
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`SEQ: res <= cr_zf;
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`SNE: res <= !cr_zf;
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`SMI: res <= ( cr_nf);
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`SPL: res <= (!cr_zf);
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`SHI: res <= (!cr_cf & !cr_zf);
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`SLS: res <= (cf |zf);
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`SHS: res <= (!cr_cf);
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`SLO: res <= ( cr_cf);
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`SGT: res <= ((cr_nf & cr_vf & !cr_zf)|(!cr_nf & !cr_vf & !cr_zf));
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`SLE: res <= (cr_zf | (cr_nf & !cr_vf) | (!cr_nf & cr_vf));
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`SGE: res <= ((cr_nf & cr_vf)|(!cr_nf & !cr_vf));
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`SLT: res <= ((cr_nf & !cr_vf)|(!cr_nf & cr_vf));
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`SVS: res <= ( cr_vf);
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`SVC: res <= (!cr_vf);
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endcase
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end
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`ADDI: res <= a + imm;
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`SUBI: res <= a - imm;
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`CMPI: res <= a - imm;
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`ANDI: res <= a & imm;
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`ORI: res <= a | imm;
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`EORI: res <= a ^ imm;
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10 |
robfinch |
/*
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2 |
robfinch |
case(ir[20:16])
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`ORI_CCR:
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begin
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state <= IFETCH;
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cr0 <= cr0 | imm[3:0];
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cr1 <= cr1 | imm[7:4];
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cr2 <= cr2 | imm[11:8];
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cr3 <= cr3 | imm[15:12];
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cr4 <= cr4 | imm[19:16];
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cr5 <= cr5 | imm[23:20];
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cr6 <= cr6 | imm[27:24];
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cr7 <= cr7 | imm[31:28];
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end
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`ANDI_CCR:
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begin
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state <= IFETCH;
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cr0 <= cr0 & imm[3:0];
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cr1 <= cr1 & imm[7:4];
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cr2 <= cr2 & imm[11:8];
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cr3 <= cr3 & imm[15:12];
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cr4 <= cr4 & imm[19:16];
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cr5 <= cr5 & imm[23:20];
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cr6 <= cr6 & imm[27:24];
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cr7 <= cr7 & imm[31:28];
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end
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`EORI_CCR:
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begin
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state <= IFETCH;
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cr0 <= cr0 ^ imm[3:0];
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cr1 <= cr1 ^ imm[7:4];
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cr2 <= cr2 ^ imm[11:8];
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cr3 <= cr3 ^ imm[15:12];
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cr4 <= cr4 ^ imm[19:16];
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cr5 <= cr5 ^ imm[23:20];
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cr6 <= cr6 ^ imm[27:24];
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cr7 <= cr7 ^ imm[31:28];
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end
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endcase
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10 |
robfinch |
*/
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robfinch |
`LINK: state <= LINK;
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robfinch |
`MULUI: state <= MULTDIV1;
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`MULSI: state <= MULTDIV1;
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`DIVUI: state <= MULTDIV1;
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`DIVSI: state <= MULTDIV1;
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2 |
robfinch |
default: res <= 32'd0;
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endcase
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case(opcode)
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`TAS: begin ea <= a + imm; mopcode <= opcode; state <= TAS; end
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`LW: begin ea <= a + imm; mopcode <= opcode; state <= MEMORY1; end
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`LH: begin ea <= a + imm; mopcode <= opcode; state <= MEMORY1; end
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`LB: begin ea <= a + imm; mopcode <= opcode; state <= MEMORY1; end
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`LHU: begin ea <= a + imm; mopcode <= opcode; state <= MEMORY1; end
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`LBU: begin ea <= a + imm; mopcode <= opcode; state <= MEMORY1; end
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`SW: begin ea <= a + imm; mopcode <= opcode; state <= MEMORY1; end
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`SH: begin ea <= a + imm; mopcode <= opcode; state <= MEMORY1; end
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`SB: begin ea <= a + imm; mopcode <= opcode; state <= MEMORY1; end
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`PEA: begin ea <= a + imm; mopcode <= opcode; state <= PEA; end
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default: ea <= 32'd0;
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endcase
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end
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