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[/] [klc32/] [trunk/] [rtl/] [verilog/] [MULTDIV.v] - Blame information for rev 10

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// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// MULTDIV.v
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
MULTDIV1:
        begin
                state <= IsMult ? MULT1 : DIV1;
                cnt <= 6'd0;
                case(opcode)
                `RR:    // RR
                        case(func)
                        `MULS,`MULSH,`DIVS,`MODS:
                                begin
                                        aa <= a[31] ? -a : a;
                                        bb <= b[31] ? -b : b;
                                        res_sgn <= a[31] ^ b[31];
                                end
                        `MULU,`MULUH,`DIVU,`MODU:
                                begin
                                        aa <= a;
                                        bb <= b;
                                        res_sgn <= 1'b0;
                                end
                        endcase
                `MULSI,`DIVSI:
                        begin
                                aa <= a[31] ? -a : a;
                                bb <= imm[31] ? -imm : imm;
                                res_sgn <= a[31] ^ imm[31];
                        end
                `MULUI,`DIVUI:
                        begin
                                aa <= a;
                                bb <= imm;
                                res_sgn <= 1'b0;
                        end
                endcase
        end
 
MULT1:  begin prod <= {mp3,mp0} + {mp1,16'd0}; state <= MULT2; end
MULT2:  begin prod <= prod + {mp2,16'd0}; state <= res_sgn ? MULT6 : MULTDIV2; end
MULT6:
        begin
                state <= MULTDIV2;
                prod <= -prod;
        end
 
// Non-restoring divide
DIV1:
        if (cnt <= 32) begin
                cnt <= cnt + 8'd1;
                aa[0] <= ~div_dif[31];           // get test result
                aa[31:1] <= aa[30:0];                    // shift quotient
                div_r0[0] <= aa[31];                     // shift bit into test area (remainder)
                if (~div_dif[31])
                        div_r0[31:1] <= div_dif[31:0];
                else
                        div_r0[31:1] <= div_r0[30:0];
        end
        else
                state <= DIV2;
DIV2:
        begin
                state <= MULTDIV2;
                if (res_sgn) begin
                        div_q <= -aa;
                        div_r <= -div_r0;
                end
                else begin
                        div_q <= aa;
                        div_r <= div_r0;
                end
        end
 
MULTDIV2:
        begin
                state <= WRITEBACK;
                case(opcode)
                `RR:
                        case(func)
                        `MULU:  begin res <= prod[31:0]; vf <= |prod[63:32]; end
                        `MULS:  begin res <= prod[31:0]; vf <= prod[31] ? ~&prod[63:32] : |prod[63:32]; end
                        `MULUH: begin res <= prod[63:32]; end
                        `MULSH: begin res <= prod[63:32]; end
                        `DIVS:  res <= div_q;
                        `DIVU:  res <= div_q;
                        `MODS:  res <= div_r;
                        `MODU:  res <= div_r;
                        endcase
                `MULSI: begin res <= prod[31:0]; vf <= prod[31] ? ~&prod[63:32] : |prod[63:32]; end
                `MULUI: begin res <= prod[31:0]; vf <= |prod[63:32]; end
                `DIVUI: res <= div_q;
                `DIVSI: res <= div_q;
                endcase
        end

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// MULTDIV.v`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`// ============================================================================`
23			`//`
24			`MULTDIV1:`
25			`begin`
26			`state <= IsMult ? MULT1 : DIV1;`
27			`cnt <= 6'd0;`
28			`case(opcode)`
29			`RR: // RR
30			`case(func)`
31			`MULS,`MULSH,`DIVS,`MODS:
32			`begin`
33			`aa <= a[31] ? -a : a;`
34			`bb <= b[31] ? -b : b;`
35			`res_sgn <= a[31] ^ b[31];`
36			`end`
37			`MULU,`MULUH,`DIVU,`MODU:
38			`begin`
39			`aa <= a;`
40			`bb <= b;`
41			`res_sgn <= 1'b0;`
42			`end`
43			`endcase`
44			`MULSI,`DIVSI:
45			`begin`
46			`aa <= a[31] ? -a : a;`
47			`bb <= imm[31] ? -imm : imm;`
48			`res_sgn <= a[31] ^ imm[31];`
49			`end`
50			`MULUI,`DIVUI:
51			`begin`
52			`aa <= a;`
53			`bb <= imm;`
54			`res_sgn <= 1'b0;`
55			`end`
56			`endcase`
57			`end`
58
59			`MULT1: begin prod <= {mp3,mp0} + {mp1,16'd0}; state <= MULT2; end`
60			`MULT2: begin prod <= prod + {mp2,16'd0}; state <= res_sgn ? MULT6 : MULTDIV2; end`
61			`MULT6:`
62			`begin`
63			`state <= MULTDIV2;`
64			`prod <= -prod;`
65			`end`
66
67			`// Non-restoring divide`
68			`DIV1:`
69			`if (cnt <= 32) begin`
70			`cnt <= cnt + 8'd1;`
71			`aa[0] <= ~div_dif[31]; // get test result`
72			`aa[31:1] <= aa[30:0]; // shift quotient`
73			`div_r0[0] <= aa[31]; // shift bit into test area (remainder)`
74			`if (~div_dif[31])`
75			`div_r0[31:1] <= div_dif[31:0];`
76			`else`
77			`div_r0[31:1] <= div_r0[30:0];`
78			`end`
79			`else`
80			`state <= DIV2;`
81			`DIV2:`
82			`begin`
83			`state <= MULTDIV2;`
84			`if (res_sgn) begin`
85			`div_q <= -aa;`
86			`div_r <= -div_r0;`
87			`end`
88			`else begin`
89			`div_q <= aa;`
90			`div_r <= div_r0;`
91			`end`
92			`end`
93
94			`MULTDIV2:`
95			`begin`
96			`state <= WRITEBACK;`
97			`case(opcode)`
98			`RR:
99			`case(func)`
100			`MULU: begin res <= prod[31:0]; vf <= \|prod[63:32]; end
101			`MULS: begin res <= prod[31:0]; vf <= prod[31] ? ~&prod[63:32] : \|prod[63:32]; end
102			`MULUH: begin res <= prod[63:32]; end
103			`MULSH: begin res <= prod[63:32]; end
104			`DIVS: res <= div_q;
105			`DIVU: res <= div_q;
106			`MODS: res <= div_r;
107			`MODU: res <= div_r;
108			`endcase`
109			`MULSI: begin res <= prod[31:0]; vf <= prod[31] ? ~&prod[63:32] : \|prod[63:32]; end
110			`MULUI: begin res <= prod[31:0]; vf <= \|prod[63:32]; end
111			`DIVUI: res <= div_q;
112			`DIVSI: res <= div_q;
113			`endcase`
114			`end`

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[/] [klc32/] [trunk/] [rtl/] [verilog/] [MULTDIV.v] - Blame information for rev 10