OpenCores
URL https://opencores.org/ocsvn/klc32/klc32/trunk

Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [POP.v] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch 
// ============================================================================
2 
// (C) 2011 Robert Finch
3 
// All Rights Reserved.
4 
// robfinch<remove>@opencores.org
5 
//
6 
// KLC32 - 32 bit CPU
7 
// POP type instructions
8 
// POP / UNLK
9 
//
10 
// This source file is free software: you can redistribute it and/or modify
11 
// it under the terms of the GNU Lesser General Public License as published
12 
// by the Free Software Foundation, either version 3 of the License, or
13 
// (at your option) any later version.
14 
//
15 
// This source file is distributed in the hope that it will be useful,
16 
// but WITHOUT ANY WARRANTY; without even the implied warranty of
17 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 
// GNU General Public License for more details.
19 
//
20 
// You should have received a copy of the GNU General Public License
21 
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
22 
//
23 
// ============================================================================
24 
//
25 
POP1:
26 
        if (ir[25:1]==25'd0)
27 
                state <= IFETCH;
28 
        else begin
29 
                Rn <= ir[25:21];
30 
                ir[25:0] <= {ir[20:1],6'b0};
31 10 robfinch 
                if (ir[25:21]!=5'd0)
32 
                        state <= POP2;
33 2 robfinch 
        end
34 
POP2:
35 
        begin
36 
                fc_o <= {sf,2'b01};
37 
                cyc_o <= 1'b1;
38 
                stb_o <= 1'b1;
39 
                sel_o <= 4'b1111;
40 
                adr_o <= sf ? ssp : usp;
41 
                state <= POP3;
42 
        end
43 
POP3:
44 
        if (ack_i) begin
45 
                cyc_o <= 1'b0;
46 
                stb_o <= 1'b0;
47 
                sel_o <= 4'b0000;
48 
                if (sf)
49 
                        ssp <= ssp + 32'd4;
50 
                else
51 
                        usp <= usp + 32'd4;
52 
                res <= dat_i;
53 
                state <= WRITEBACK;
54 
        end
55 
        else if (err_i) begin
56 
                cyc_o <= 1'b0;
57 
                stb_o <= 1'b0;
58 
                sel_o <= 4'b0000;
59 
                vector <= `BUS_ERR_VECTOR;
60 
                state <= TRAP;
61 
        end
62 
 
63 
UNLK:
64 
        if (!cyc_o) begin
65 
                fc_o <= {sf,2'b01};
66 
                cyc_o <= 1'b1;
67 
                stb_o <= 1'b1;
68 
                sel_o <= 4'b1111;
69 
                adr_o <= a;
70 
                if (sf)
71 
                        ssp <= a;
72 
                else
73 
                        usp <= a;
74 
        end
75 
        else if (ack_i) begin
76 
                cyc_o <= 1'b0;
77 
                stb_o <= 1'b0;
78 
                sel_o <= 4'b0000;
79 
                if (sf)
80 
                        ssp <= ssp + 32'd4;
81 
                else
82 
                        usp <= usp + 32'd4;
83 
                res <= dat_i;
84 
                state <= WRITEBACK;
85 
        end
86 
        else if (err_i) begin
87 
                cyc_o <= 1'b0;
88 
                stb_o <= 1'b0;
89 
                sel_o <= 4'b0000;
90 
                vector <= `BUS_ERR_VECTOR;
91 
                state <= TRAP;
92 
        end
93 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.