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[/] [klc32/] [trunk/] [rtl/] [verilog/] [POP.v] - Blame information for rev 2

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// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// POP type instructions
// POP / UNLK
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
POP1:
        if (ir[25:1]==25'd0)
                state <= IFETCH;
        else begin
                Rn <= ir[25:21];
                ir[25:0] <= {ir[20:1],6'b0};
                state <= POP2;
        end
POP2:
        begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= sf ? ssp : usp;
                state <= POP3;
        end
POP3:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf)
                        ssp <= ssp + 32'd4;
                else
                        usp <= usp + 32'd4;
                res <= dat_i;
                state <= WRITEBACK;
        end
        else if (err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'b0000;
                vector <= `BUS_ERR_VECTOR;
                state <= TRAP;
        end
 
UNLK:
        if (!cyc_o) begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= a;
                if (sf)
                        ssp <= a;
                else
                        usp <= a;
        end
        else if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf)
                        ssp <= ssp + 32'd4;
                else
                        usp <= usp + 32'd4;
                res <= dat_i;
                state <= WRITEBACK;
        end
        else if (err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'b0000;
                vector <= `BUS_ERR_VECTOR;
                state <= TRAP;
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// POP type instructions`
8			`// POP / UNLK`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`// ============================================================================`
24			`//`
25			`POP1:`
26			`if (ir[25:1]==25'd0)`
27			`state <= IFETCH;`
28			`else begin`
29			`Rn <= ir[25:21];`
30			`ir[25:0] <= {ir[20:1],6'b0};`
31			`state <= POP2;`
32			`end`
33			`POP2:`
34			`begin`
35			`fc_o <= {sf,2'b01};`
36			`cyc_o <= 1'b1;`
37			`stb_o <= 1'b1;`
38			`sel_o <= 4'b1111;`
39			`adr_o <= sf ? ssp : usp;`
40			`state <= POP3;`
41			`end`
42			`POP3:`
43			`if (ack_i) begin`
44			`cyc_o <= 1'b0;`
45			`stb_o <= 1'b0;`
46			`sel_o <= 4'b0000;`
47			`if (sf)`
48			`ssp <= ssp + 32'd4;`
49			`else`
50			`usp <= usp + 32'd4;`
51			`res <= dat_i;`
52			`state <= WRITEBACK;`
53			`end`
54			`else if (err_i) begin`
55			`cyc_o <= 1'b0;`
56			`stb_o <= 1'b0;`
57			`sel_o <= 4'b0000;`
58			vector <= `BUS_ERR_VECTOR;
59			`state <= TRAP;`
60			`end`
61
62			`UNLK:`
63			`if (!cyc_o) begin`
64			`fc_o <= {sf,2'b01};`
65			`cyc_o <= 1'b1;`
66			`stb_o <= 1'b1;`
67			`sel_o <= 4'b1111;`
68			`adr_o <= a;`
69			`if (sf)`
70			`ssp <= a;`
71			`else`
72			`usp <= a;`
73			`end`
74			`else if (ack_i) begin`
75			`cyc_o <= 1'b0;`
76			`stb_o <= 1'b0;`
77			`sel_o <= 4'b0000;`
78			`if (sf)`
79			`ssp <= ssp + 32'd4;`
80			`else`
81			`usp <= usp + 32'd4;`
82			`res <= dat_i;`
83			`state <= WRITEBACK;`
84			`end`
85			`else if (err_i) begin`
86			`cyc_o <= 1'b0;`
87			`stb_o <= 1'b0;`
88			`sel_o <= 4'b0000;`
89			vector <= `BUS_ERR_VECTOR;
90			`state <= TRAP;`
91			`end`
92

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[/] [klc32/] [trunk/] [rtl/] [verilog/] [POP.v] - Blame information for rev 2