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[/] [klc32/] [trunk/] [rtl/] [verilog/] [PUSH.v] - Blame information for rev 10

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// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// PUSH.v - push type instructions
// PUSH / PEA / LINK
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
PUSH1:
        if (ir[25:1]==25'd0)
                state <= IFETCH;
        else begin
                Rn <= ir[25:21];
                ir[25:0] <= {ir[20:1],6'b0};
                if (ir[25:21]!=5'd0)
                        state <= PUSH2;
        end
PUSH2:
        begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;
                dat_o <= rfo;
                state <= PUSH3;
        end
PUSH3:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf)
                        ssp <= ssp - 32'd4;
                else
                        usp <= usp - 32'd4;
                state <= PUSH1;
        end
        else if (err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                vector <= `BUS_ERR_VECTOR;
                state <= TRAP;
        end
 
PEA:
        if (!cyc_o) begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;
                dat_o <= ea;
        end
        else if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf)
                        ssp <= ssp - 32'd4;
                else
                        usp <= usp - 32'd4;
                state <= IFETCH;
        end
        else if (err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                vector <= `BUS_ERR_VECTOR;
                state <= TRAP;
        end
 
LINK:
        if (!cyc_o) begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;
                dat_o <= a;
        end
        else if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf) begin
                        ssp <= ssp - 32'd4;
                        res <= ssp - 32'd4;
                end
                else begin
                        usp <= usp - 32'd4;
                        res <= usp - 32'd4;
                end
                state <= WRITEBACK;
        end
        else if (err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                vector <= `BUS_ERR_VECTOR;
                state <= TRAP;
        end

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// PUSH.v - push type instructions`
8			`// PUSH / PEA / LINK`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`// ============================================================================`
24			`//`
25			`PUSH1:`
26			`if (ir[25:1]==25'd0)`
27			`state <= IFETCH;`
28			`else begin`
29			`Rn <= ir[25:21];`
30			`ir[25:0] <= {ir[20:1],6'b0};`
31	10	robfinch	`if (ir[25:21]!=5'd0)`
32			`state <= PUSH2;`
33	2	robfinch	`end`
34			`PUSH2:`
35			`begin`
36			`fc_o <= {sf,2'b01};`
37			`cyc_o <= 1'b1;`
38			`stb_o <= 1'b1;`
39			`we_o <= 1'b1;`
40			`sel_o <= 4'b1111;`
41			`adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;`
42			`dat_o <= rfo;`
43			`state <= PUSH3;`
44			`end`
45			`PUSH3:`
46			`if (ack_i) begin`
47			`cyc_o <= 1'b0;`
48			`stb_o <= 1'b0;`
49			`we_o <= 1'b0;`
50			`sel_o <= 4'b0000;`
51			`if (sf)`
52			`ssp <= ssp - 32'd4;`
53			`else`
54			`usp <= usp - 32'd4;`
55			`state <= PUSH1;`
56			`end`
57			`else if (err_i) begin`
58			`cyc_o <= 1'b0;`
59			`stb_o <= 1'b0;`
60			`we_o <= 1'b0;`
61			`sel_o <= 4'b0000;`
62			vector <= `BUS_ERR_VECTOR;
63			`state <= TRAP;`
64			`end`
65
66			`PEA:`
67			`if (!cyc_o) begin`
68			`fc_o <= {sf,2'b01};`
69			`cyc_o <= 1'b1;`
70			`stb_o <= 1'b1;`
71			`we_o <= 1'b1;`
72			`sel_o <= 4'b1111;`
73			`adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;`
74			`dat_o <= ea;`
75			`end`
76			`else if (ack_i) begin`
77			`cyc_o <= 1'b0;`
78			`stb_o <= 1'b0;`
79			`we_o <= 1'b0;`
80			`sel_o <= 4'b0000;`
81			`if (sf)`
82			`ssp <= ssp - 32'd4;`
83			`else`
84			`usp <= usp - 32'd4;`
85			`state <= IFETCH;`
86			`end`
87			`else if (err_i) begin`
88			`cyc_o <= 1'b0;`
89			`stb_o <= 1'b0;`
90			`we_o <= 1'b0;`
91			`sel_o <= 4'b0000;`
92			vector <= `BUS_ERR_VECTOR;
93			`state <= TRAP;`
94			`end`
95
96			`LINK:`
97			`if (!cyc_o) begin`
98			`fc_o <= {sf,2'b01};`
99			`cyc_o <= 1'b1;`
100			`stb_o <= 1'b1;`
101			`we_o <= 1'b1;`
102			`sel_o <= 4'b1111;`
103			`adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;`
104			`dat_o <= a;`
105			`end`
106			`else if (ack_i) begin`
107			`cyc_o <= 1'b0;`
108			`stb_o <= 1'b0;`
109			`we_o <= 1'b0;`
110			`sel_o <= 4'b0000;`
111			`if (sf) begin`
112			`ssp <= ssp - 32'd4;`
113			`res <= ssp - 32'd4;`
114			`end`
115			`else begin`
116			`usp <= usp - 32'd4;`
117			`res <= usp - 32'd4;`
118			`end`
119			`state <= WRITEBACK;`
120			`end`
121			`else if (err_i) begin`
122			`cyc_o <= 1'b0;`
123			`stb_o <= 1'b0;`
124			`we_o <= 1'b0;`
125			`sel_o <= 4'b0000;`
126			vector <= `BUS_ERR_VECTOR;
127			`state <= TRAP;`
128			`end`

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[/] [klc32/] [trunk/] [rtl/] [verilog/] [PUSH.v] - Blame information for rev 10