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[/] [klc32/] [trunk/] [rtl/] [verilog/] [PUSH.v] - Blame information for rev 2

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// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// PUSH.v - push type instructions
// PUSH / PEA / LINK
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
PUSH1:
        if (ir[25:1]==25'd0)
                state <= IFETCH;
        else begin
                Rn <= ir[25:21];
                ir[25:0] <= {ir[20:1],6'b0};
                state <= PUSH2;
        end
PUSH2:
        begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;
                dat_o <= rfo;
                state <= PUSH3;
        end
PUSH3:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf)
                        ssp <= ssp - 32'd4;
                else
                        usp <= usp - 32'd4;
                state <= PUSH1;
        end
        else if (err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                vector <= `BUS_ERR_VECTOR;
                state <= TRAP;
        end
 
PEA:
        if (!cyc_o) begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;
                dat_o <= ea;
        end
        else if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf)
                        ssp <= ssp - 32'd4;
                else
                        usp <= usp - 32'd4;
                state <= IFETCH;
        end
        else if (err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                vector <= `BUS_ERR_VECTOR;
                state <= TRAP;
        end
 
LINK:
        if (!cyc_o) begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;
                dat_o <= a;
        end
        else if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf) begin
                        ssp <= ssp - 32'd4;
                        res <= ssp - 32'd4;
                end
                else begin
                        usp <= usp - 32'd4;
                        res <= usp - 32'd4;
                end
                state <= WRITEBACK;
        end
        else if (err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                vector <= `BUS_ERR_VECTOR;
                state <= TRAP;
        end

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// PUSH.v - push type instructions`
8			`// PUSH / PEA / LINK`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`// ============================================================================`
24			`//`
25			`PUSH1:`
26			`if (ir[25:1]==25'd0)`
27			`state <= IFETCH;`
28			`else begin`
29			`Rn <= ir[25:21];`
30			`ir[25:0] <= {ir[20:1],6'b0};`
31			`state <= PUSH2;`
32			`end`
33			`PUSH2:`
34			`begin`
35			`fc_o <= {sf,2'b01};`
36			`cyc_o <= 1'b1;`
37			`stb_o <= 1'b1;`
38			`we_o <= 1'b1;`
39			`sel_o <= 4'b1111;`
40			`adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;`
41			`dat_o <= rfo;`
42			`state <= PUSH3;`
43			`end`
44			`PUSH3:`
45			`if (ack_i) begin`
46			`cyc_o <= 1'b0;`
47			`stb_o <= 1'b0;`
48			`we_o <= 1'b0;`
49			`sel_o <= 4'b0000;`
50			`if (sf)`
51			`ssp <= ssp - 32'd4;`
52			`else`
53			`usp <= usp - 32'd4;`
54			`state <= PUSH1;`
55			`end`
56			`else if (err_i) begin`
57			`cyc_o <= 1'b0;`
58			`stb_o <= 1'b0;`
59			`we_o <= 1'b0;`
60			`sel_o <= 4'b0000;`
61			vector <= `BUS_ERR_VECTOR;
62			`state <= TRAP;`
63			`end`
64
65			`PEA:`
66			`if (!cyc_o) begin`
67			`fc_o <= {sf,2'b01};`
68			`cyc_o <= 1'b1;`
69			`stb_o <= 1'b1;`
70			`we_o <= 1'b1;`
71			`sel_o <= 4'b1111;`
72			`adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;`
73			`dat_o <= ea;`
74			`end`
75			`else if (ack_i) begin`
76			`cyc_o <= 1'b0;`
77			`stb_o <= 1'b0;`
78			`we_o <= 1'b0;`
79			`sel_o <= 4'b0000;`
80			`if (sf)`
81			`ssp <= ssp - 32'd4;`
82			`else`
83			`usp <= usp - 32'd4;`
84			`state <= IFETCH;`
85			`end`
86			`else if (err_i) begin`
87			`cyc_o <= 1'b0;`
88			`stb_o <= 1'b0;`
89			`we_o <= 1'b0;`
90			`sel_o <= 4'b0000;`
91			vector <= `BUS_ERR_VECTOR;
92			`state <= TRAP;`
93			`end`
94
95			`LINK:`
96			`if (!cyc_o) begin`
97			`fc_o <= {sf,2'b01};`
98			`cyc_o <= 1'b1;`
99			`stb_o <= 1'b1;`
100			`we_o <= 1'b1;`
101			`sel_o <= 4'b1111;`
102			`adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;`
103			`dat_o <= a;`
104			`end`
105			`else if (ack_i) begin`
106			`cyc_o <= 1'b0;`
107			`stb_o <= 1'b0;`
108			`we_o <= 1'b0;`
109			`sel_o <= 4'b0000;`
110			`if (sf) begin`
111			`ssp <= ssp - 32'd4;`
112			`res <= ssp - 32'd4;`
113			`end`
114			`else begin`
115			`usp <= usp - 32'd4;`
116			`res <= usp - 32'd4;`
117			`end`
118			`state <= WRITEBACK;`
119			`end`
120			`else if (err_i) begin`
121			`cyc_o <= 1'b0;`
122			`stb_o <= 1'b0;`
123			`we_o <= 1'b0;`
124			`sel_o <= 4'b0000;`
125			vector <= `BUS_ERR_VECTOR;
126			`state <= TRAP;`
127			`end`

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[/] [klc32/] [trunk/] [rtl/] [verilog/] [PUSH.v] - Blame information for rev 2