OpenCores
URL https://opencores.org/ocsvn/klc32/klc32/trunk

Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [RTS.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch
// ============================================================================
2
// (C) 2011 Robert Finch
3
// All Rights Reserved.
4
// robfinch<remove>@opencores.org
5
//
6
// KLC32 - 32 bit CPU
7
// RTS.v - return from subroutine
8
//
9
// This source file is free software: you can redistribute it and/or modify 
10
// it under the terms of the GNU Lesser General Public License as published 
11
// by the Free Software Foundation, either version 3 of the License, or     
12
// (at your option) any later version.                                      
13
//                                                                          
14
// This source file is distributed in the hope that it will be useful,      
15
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
16
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
17
// GNU General Public License for more details.                             
18
//                                                                          
19
// You should have received a copy of the GNU General Public License        
20
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
21
//                                                                          
22
// ============================================================================
23
//
24
RTS:
25
        if (!cyc_o) begin
26
                fc_o <= {sf,2'b01};
27
                cyc_o <= 1'b1;
28
                stb_o <= 1'b1;
29
                sel_o <= 4'b1111;
30
                adr_o <= sf ? ssp : usp;
31
        end
32
        else if (ack_i) begin
33
                cyc_o <= 1'b0;
34
                stb_o <= 1'b0;
35
                sel_o <= 4'b0000;
36
                if (sf)
37
                        ssp <= ssp + 32'd4 + ir[21:6];
38
                else
39
                        usp <= usp + 32'd4 + ir[21:6];
40
                pc <= {dat_i[31:2],2'b00}+{ir[25:22],2'b00};
41
                state <= IFETCH;
42
        end
43
        else if (err_i) begin
44
                cyc_o <= 1'b0;
45
                stb_o <= 1'b0;
46
                sel_o <= 4'b0000;
47
                vector <= `BUS_ERR_VECTOR;
48
                state <= TRAP;
49
        end
50
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.