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[/] [klc32/] [trunk/] [rtl/] [verilog/] [WRITE_FLAGS.v] - Blame information for rev 10

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// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// WRITE_FLAGS.v - update the CR registers
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
WRITE_FLAGS:
        begin
                state <= IFETCH;
                if (opcode==`CMPI || (opcode==`RR && func==`CMP)) begin
                        case(Rn[4:2])
                        3'd0:   cr0 <= {nf,zf,vf,cf};
                        3'd1:   cr1 <= {nf,zf,vf,cf};
                        3'd2:   cr2 <= {nf,zf,vf,cf};
                        3'd3:   cr3 <= {nf,zf,vf,cf};
                        3'd4:   cr4 <= {nf,zf,vf,cf};
                        3'd5:   cr5 <= {nf,zf,vf,cf};
                        3'd6:   cr6 <= {nf,zf,vf,cf};
                        3'd7:   cr7 <= {nf,zf,vf,cf};
                        endcase
                end
                else begin
                        case(opcode)
                        `R:
                                case(func)
                                `ABS,`SGN,`NEG,`NOT,`EXTB,`EXTH:
                                        if (Rcbit) cr0 <= {nf,zf,vf,cf};
                                default:        ;
                                endcase
                        `RR:
                                case(func)
                                `MULU,`MULS,`MULUH,`MULSH,`DIVU,`DIVS,`MODU,`MODS,
                                `ADD,`SUB,`AND,`ANDC,`OR,`ORC,`EOR,`NAND,`NOR,`ENOR,
                                `MIN,`MAX,
                                `BCDADD,`BCDSUB,
                                `SHL,`SHR,`ROL,`ROR,
                                `LWX,`LHX,`LBX,`LHUX,`LBUX:
                                        if (Rcbit) cr0 <= {nf,zf,vf,cf};
                                default:        ;
                        endcase
                        `MULUI,`MULSI,`DIVUI,`DIVSI,
                        `ADDI,`SUBI,`ANDI,`ORI,`EORI,`LW,`LH,`LB,`LHU,`LBU,`TAS:
                                cr0 <= {nf,zf,vf,cf};
                        default:        ;
                        endcase
                end
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// WRITE_FLAGS.v - update the CR registers`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`// ============================================================================`
23			`//`
24			`WRITE_FLAGS:`
25			`begin`
26			`state <= IFETCH;`
27			if (opcode==`CMPI \|\| (opcode==`RR && func==`CMP)) begin
28	10	robfinch	`case(Rn[4:2])`
29	2	robfinch	`3'd0: cr0 <= {nf,zf,vf,cf};`
30			`3'd1: cr1 <= {nf,zf,vf,cf};`
31			`3'd2: cr2 <= {nf,zf,vf,cf};`
32			`3'd3: cr3 <= {nf,zf,vf,cf};`
33			`3'd4: cr4 <= {nf,zf,vf,cf};`
34			`3'd5: cr5 <= {nf,zf,vf,cf};`
35			`3'd6: cr6 <= {nf,zf,vf,cf};`
36			`3'd7: cr7 <= {nf,zf,vf,cf};`
37			`endcase`
38			`end`
39			`else begin`
40			`case(opcode)`
41			`R:
42			`case(func)`
43			`ABS,`SGN,`NEG,`NOT,`EXTB,`EXTH:
44	10	robfinch	`if (Rcbit) cr0 <= {nf,zf,vf,cf};`
45	2	robfinch	`default: ;`
46			`endcase`
47			`RR:
48			`case(func)`
49	10	robfinch	`MULU,`MULS,`MULUH,`MULSH,`DIVU,`DIVS,`MODU,`MODS,
50			`ADD,`SUB,`AND,`ANDC,`OR,`ORC,`EOR,`NAND,`NOR,`ENOR,
51	2	robfinch	`MIN,`MAX,
52			`BCDADD,`BCDSUB,
53			`SHL,`SHR,`ROL,`ROR,
54			`LWX,`LHX,`LBX,`LHUX,`LBUX:
55	10	robfinch	`if (Rcbit) cr0 <= {nf,zf,vf,cf};`
56	2	robfinch	`default: ;`
57	10	robfinch	`endcase`
58			`MULUI,`MULSI,`DIVUI,`DIVSI,
59	2	robfinch	`ADDI,`SUBI,`ANDI,`ORI,`EORI,`LW,`LH,`LB,`LHU,`LBU,`TAS:
60			`cr0 <= {nf,zf,vf,cf};`
61			`default: ;`
62			`endcase`
63			`end`
64			`end`
65

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[/] [klc32/] [trunk/] [rtl/] [verilog/] [WRITE_FLAGS.v] - Blame information for rev 10