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[/] [kvcordic/] [trunk/] [syn/] [xise/] [log/] [cordic-xst14.6.txt] - Blame information for rev 2

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1 2 kavi
Release 14.6 - xst P.68d (nt)
2
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
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-->
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TABLE OF CONTENTS
5
  1) Synthesis Options Summary
6
  2) HDL Parsing
7
  3) HDL Elaboration
8
  4) HDL Synthesis
9
       4.1) HDL Synthesis Report
10
  5) Advanced HDL Synthesis
11
       5.1) Advanced HDL Synthesis Report
12
  6) Low Level Synthesis
13
  7) Partition Report
14
  8) Design Summary
15
       8.1) Primitive and Black Box Usage
16
       8.2) Device utilization summary
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       8.3) Partition Resource Summary
18
       8.4) Timing Report
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            8.4.1) Clock Information
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            8.4.2) Asynchronous Control Signals Information
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            8.4.3) Timing Summary
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            8.4.4) Timing Details
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            8.4.5) Cross Clock Domains Report
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25
 
26
=========================================================================
27
*                      Synthesis Options Summary                        *
28
=========================================================================
29
---- Source Parameters
30
Input File Name                    : ".work"
31
Input Format                       : mixed
32
 
33
---- Target Parameters
34
Output File Name                   : ".ngc"
35
Output Format                      : NGC
36
Target Device                      : xc6vlx75t-ff484-1
37
 
38
---- Source Options
39
Top Module Name                    : cordic
40
 
41
---- Target Options
42
Add IO Buffers                     : no
43
 
44
---- General Options
45
Optimization Goal                  : Speed
46
Optimization Effort                : 1
47
 
48
=========================================================================
49
 
50
 
51
=========================================================================
52
*                          HDL Parsing                                  *
53
=========================================================================
54
Parsing VHDL file "E:\projects\cordic\sim\rtl_sim\vhdl\operpack.vhd" into library work
55
Parsing package .
56
Parsing package body .
57
Parsing VHDL file "E:\projects\cordic\rtl\vhdl\cordic_cdt_pkg.vhd" into library work
58
Parsing package .
59
Parsing VHDL file "E:\projects\cordic\rtl\vhdl\cordic.vhd" into library work
60
Parsing entity .
61
Parsing architecture  of entity .
62
 
63
=========================================================================
64
*                            HDL Elaboration                            *
65
=========================================================================
66
 
67
Elaborating entity  (architecture ) from library .
68
WARNING:HDLCompiler:92 - "E:\projects\cordic\rtl\vhdl\cordic.vhd" Line 367: cordic_hyp_steps should be on the sensitivity list of the process
69
WARNING:HDLCompiler:92 - "E:\projects\cordic\rtl\vhdl\cordic.vhd" Line 387: cordic_tab should be on the sensitivity list of the process
70
 
71
=========================================================================
72
*                           HDL Synthesis                               *
73
=========================================================================
74
 
75
Synthesizing Unit .
76
    Related source file is "E:\projects\cordic\rtl\vhdl\cordic.vhd".
77
WARNING:Xst:2999 - Signal 'cordic_hyp_steps', unconnected in block 'cordic', is tied to its initial value.
78
WARNING:Xst:2999 - Signal 'cordic_tab', unconnected in block 'cordic', is tied to its initial value.
79
WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch.
80
    Found 15x16-bit single-port Read Only RAM  for signal .
81
WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch.
82
    Found 42x16-bit single-port Read Only RAM  for signal .
83
    Found 16-bit register for signal .
84
    Found 16-bit register for signal .
85
    Found 16-bit register for signal .
86
    Found 16-bit register for signal .
87
    Found 16-bit register for signal .
88
    Found 16-bit register for signal .
89
    Found 16-bit register for signal .
90
    Found 16-bit register for signal .
91
    Found 16-bit register for signal .
92
    Found 16-bit register for signal .
93
    Found 16-bit register for signal .
94
    Found 16-bit register for signal .
95
    Found 16-bit register for signal .
96
    Found 16-bit register for signal .
97
    Found 16-bit register for signal .
98
    Found 16-bit register for signal .
99
    Found 16-bit register for signal .
100
    Found 16-bit register for signal .
101
    Found 16-bit register for signal .
102
    Found 16-bit register for signal .
103
    Found 16-bit register for signal .
104
    Found 16-bit register for signal .
105
    Found 16-bit register for signal .
106
    Found 16-bit register for signal .
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    Found 16-bit register for signal .
108
    Found 16-bit register for signal .
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    Found 16-bit register for signal .
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    Found 16-bit register for signal .
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    Found 16-bit register for signal .
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    Found 16-bit register for signal .
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    Found 16-bit register for signal .
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    Found 16-bit register for signal .
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    Found 16-bit register for signal .
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    Found 16-bit register for signal .
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    Found 3-bit register for signal .
118
    Found finite state machine  for signal .
119
    -----------------------------------------------------------------------
120
    | States             | 6                                              |
121
    | Transitions        | 9                                              |
122
    | Inputs             | 3                                              |
123
    | Outputs            | 5                                              |
124
    | Clock              | clk (rising_edge)                              |
125
    | Reset              | reset (positive)                               |
126
    | Reset type         | asynchronous                                   |
127
    | Reset State        | s_entry                                        |
128
    | Power Up State     | s_entry                                        |
129
    | Encoding           | auto                                           |
130
    | Implementation     | LUT                                            |
131
    -----------------------------------------------------------------------
132
    Found 16-bit adder for signal  created at line 374.
133
    Found 16-bit adder for signal  created at line 386.
134
    Found 16-bit adder for signal  created at line 408.
135
    Found 16-bit adder for signal  created at line 409.
136
    Found 16-bit adder for signal  created at line 412.
137
    Found 16-bit adder for signal  created at line 428.
138
    Found 16-bit subtractor for signal > created at line 407.
139
    Found 16-bit subtractor for signal > created at line 410.
140
    Found 16-bit subtractor for signal > created at line 411.
141
    Found 16-bit comparator greater for signal  created at line 361
142
    Found 16-bit comparator greater for signal  created at line 429
143
    Summary:
144
        inferred   2 RAM(s).
145
        inferred   9 Adder/Subtractor(s).
146
        inferred 528 D-type flip-flop(s).
147
        inferred   2 Comparator(s).
148
        inferred  49 Multiplexer(s).
149
        inferred   1 Finite State Machine(s).
150
Unit  synthesized.
151
 
152
=========================================================================
153
HDL Synthesis Report
154
 
155
Macro Statistics
156
# RAMs                                                 : 2
157
 15x16-bit single-port Read Only RAM                   : 1
158
 42x16-bit single-port Read Only RAM                   : 1
159
# Adders/Subtractors                                   : 9
160
 16-bit adder                                          : 6
161
 16-bit subtractor                                     : 3
162
# Registers                                            : 33
163
 16-bit register                                       : 33
164
# Comparators                                          : 2
165
 16-bit comparator greater                             : 2
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# Multiplexers                                         : 49
167
 16-bit 2-to-1 multiplexer                             : 49
168
# FSMs                                                 : 1
169
 
170
=========================================================================
171
 
172
=========================================================================
173
*                       Advanced HDL Synthesis                          *
174
=========================================================================
175
 
176
WARNING:Xst:2404 -  FFs/Latches > (without init value) have a constant value of 0 in block .
177
WARNING:Xst:2404 -  FFs/Latches > (without init value) have a constant value of 0 in block .
178
 
179
Synthesizing (advanced) Unit .
180
INFO:Xst:3218 - HDL ADVISOR - The RAM  will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
181
    -----------------------------------------------------------------------
182
    | ram_type           | Distributed                         |          |
183
    -----------------------------------------------------------------------
184
    | Port A                                                              |
185
    |     aspect ratio   | 15-word x 16-bit                    |          |
186
    |     weA            | connected to signal            | high     |
187
    |     addrA          | connected to signal >    |          |
188
    |     diA            | connected to signal            |          |
189
    |     doA            | connected to internal node          |          |
190
    -----------------------------------------------------------------------
191
INFO:Xst:3218 - HDL ADVISOR - The RAM  will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
192
    -----------------------------------------------------------------------
193
    | ram_type           | Distributed                         |          |
194
    -----------------------------------------------------------------------
195
    | Port A                                                              |
196
    |     aspect ratio   | 42-word x 16-bit                    |          |
197
    |     weA            | connected to signal            | high     |
198
    |     addrA          | connected to signal >  |          |
199
    |     diA            | connected to signal            |          |
200
    |     doA            | connected to internal node          |          |
201
    -----------------------------------------------------------------------
202
Unit  synthesized (advanced).
203
 
204
=========================================================================
205
Advanced HDL Synthesis Report
206
 
207
Macro Statistics
208
# RAMs                                                 : 2
209
 15x16-bit single-port distributed Read Only RAM       : 1
210
 42x16-bit single-port distributed Read Only RAM       : 1
211
# Adders/Subtractors                                   : 9
212
 16-bit adder                                          : 6
213
 16-bit subtractor                                     : 3
214
# Registers                                            : 501
215
 Flip-Flops                                            : 501
216
# Comparators                                          : 2
217
 16-bit comparator greater                             : 2
218
# Multiplexers                                         : 49
219
 16-bit 2-to-1 multiplexer                             : 49
220
# FSMs                                                 : 1
221
 
222
=========================================================================
223
 
224
=========================================================================
225
*                         Low Level Synthesis                           *
226
=========================================================================
227
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 3 FFs/Latches, which will be removed :   
228
Analyzing FSM  for best encoding.
229
Optimizing FSM  on signal  with user encoding.
230
-----------------------
231
 State     | Encoding
232
-----------------------
233
 s_entry   | 000
234
 s_exit    | 001
235
 s_001_001 | 010
236
 s_002_001 | 011
237
 s_003_001 | 100
238
 s_004_001 | 101
239
-----------------------
240
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
241
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
242
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
243
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
244
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
245
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
246
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
247
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
248
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
249
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
250
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
251
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
252
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
253
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
254
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
255
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
256
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
257
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
258
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
259
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
260
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
365
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
366
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
367
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
368
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
379
 
380
Optimizing unit  ...
381
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
382
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
383
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
385
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
386
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
387
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
388
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
389
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
390
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
391
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
393
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
394
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
395
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
396
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
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WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
398
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
399
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
400
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
401
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
402
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
403
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
404
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
405
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
406
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
407
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
408
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
409
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
410
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
411
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
412
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
413
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
414
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
415
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
416
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
417
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
418
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
419
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
420
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
421
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
422
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
423
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
424
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
425
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
426
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
427
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
428
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
429
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
430
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
431
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
432
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
433
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
434
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
435
 
436
Mapping all equations...
437
Building and optimizing final netlist ...
438
Found area constraint ratio of 100 (+ 0) on block cordic, actual ratio is 1.
439
FlipFlop current_state_FSM_FFd1 has been replicated 1 time(s)
440
FlipFlop current_state_FSM_FFd3 has been replicated 1 time(s)
441
FlipFlop k_reg_1 has been replicated 1 time(s)
442
 
443
Final Macro Processing ...
444
 
445
=========================================================================
446
Final Register Report
447
 
448
Macro Statistics
449
# Registers                                            : 310
450
 Flip-Flops                                            : 310
451
 
452
=========================================================================
453
 
454
=========================================================================
455
*                           Partition Report                            *
456
=========================================================================
457
 
458
Partition Implementation Status
459
-------------------------------
460
 
461
  No Partitions were found in this design.
462
 
463
-------------------------------
464
 
465
=========================================================================
466
*                            Design Summary                             *
467
=========================================================================
468
 
469
Top Level Output File Name         : .ngc.ngc
470
 
471
Primitive and Black Box Usage:
472
------------------------------
473
# BELS                             : 1046
474
#      GND                         : 1
475
#      INV                         : 1
476
#      LUT1                        : 4
477
#      LUT2                        : 17
478
#      LUT3                        : 28
479
#      LUT4                        : 149
480
#      LUT5                        : 69
481
#      LUT6                        : 527
482
#      MUXCY                       : 113
483
#      MUXF7                       : 13
484
#      VCC                         : 1
485
#      XORCY                       : 123
486
# FlipFlops/Latches                : 310
487
#      FDC                         : 194
488
#      FDCE                        : 116
489
 
490
Device utilization summary:
491
---------------------------
492
 
493
Selected Device : 6vlx75tff484-1
494
 
495
 
496
Slice Logic Utilization:
497
 Number of Slice Registers:             310  out of  93120     0%
498
 Number of Slice LUTs:                  795  out of  46560     1%
499
    Number used as Logic:               795  out of  46560     1%
500
 
501
Slice Logic Distribution:
502
 Number of LUT Flip Flop pairs used:    871
503
   Number with an unused Flip Flop:     561  out of    871    64%
504
   Number with an unused LUT:            76  out of    871     8%
505
   Number of fully used LUT-FF pairs:   234  out of    871    26%
506
   Number of unique control sets:         4
507
 
508
IO Utilization:
509
 Number of IOs:                         133
510
 Number of bonded IOBs:                   0  out of    240     0%
511
 
512
Specific Feature Utilization:
513
 
514
---------------------------
515
Partition Resource Summary:
516
---------------------------
517
 
518
  No Partitions were found in this design.
519
 
520
---------------------------
521
 
522
 
523
=========================================================================
524
Timing Report
525
 
526
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
527
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
528
      GENERATED AFTER PLACE-and-ROUTE.
529
 
530
Clock Information:
531
------------------
532
-----------------------------------+------------------------+-------+
533
Clock Signal                       | Clock buffer(FF name)  | Load  |
534
-----------------------------------+------------------------+-------+
535
clk                                | NONE(ldirection_reg_0) | 310   |
536
-----------------------------------+------------------------+-------+
537
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
538
 
539
Asynchronous Control Signals Information:
540
----------------------------------------
541
No asynchronous control signals found in this design
542
 
543
Timing Summary:
544
---------------
545
Speed Grade: -1
546
 
547
   Minimum period: 6.273ns (Maximum Frequency: 159.413MHz)
548
   Minimum input arrival time before clock: 2.513ns
549
   Maximum output required time after clock: 1.256ns
550
   Maximum combinational path delay: No path found
551
 
552
Timing Details:
553
---------------
554
All values displayed in nanoseconds (ns)
555
 
556
=========================================================================
557
Timing constraint: Default period analysis for Clock 'clk'
558
  Clock period: 6.273ns (frequency: 159.413MHz)
559
  Total number of paths / destination ports: 1871281 / 410
560
-------------------------------------------------------------------------
561
Delay:               6.273ns (Levels of Logic = 23)
562
  Source:            lmode_reg_4 (FF)
563
  Destination:       z_reg_15 (FF)
564
  Source Clock:      clk rising
565
  Destination Clock: clk rising
566
 
567
  Data Path: lmode_reg_4 to z_reg_15
568
                                Gate     Net
569
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
570
    ----------------------------------------  ------------
571
     FDC:C->Q              2   0.375   0.784  lmode_reg_4 (lmode_reg_4)
572
     LUT6:I0->O            7   0.068   0.531  GND_6_o_lmode_reg[15]_equal_60_o<15>11 (GND_6_o_lmode_reg[15]_equal_60_o<15>11)
573
     LUT6:I4->O            3   0.068   0.431  n0043<15>1_1 (n0043<15>1)
574
     LUT6:I5->O            1   0.068   0.000  Madd_kk_next[15]_offset_reg[15]_add_63_OUT_lut<1> (Madd_kk_next[15]_offset_reg[15]_add_63_OUT_lut<1>)
575
     MUXCY:S->O            1   0.290   0.000  Madd_kk_next[15]_offset_reg[15]_add_63_OUT_cy<1> (Madd_kk_next[15]_offset_reg[15]_add_63_OUT_cy<1>)
576
     MUXCY:CI->O           1   0.020   0.000  Madd_kk_next[15]_offset_reg[15]_add_63_OUT_cy<2> (Madd_kk_next[15]_offset_reg[15]_add_63_OUT_cy<2>)
577
     XORCY:CI->O          20   0.239   0.542  Madd_kk_next[15]_offset_reg[15]_add_63_OUT_xor<3> (kk_next[15]_offset_reg[15]_add_63_OUT<3>)
578
     LUT4:I3->O           20   0.068   0.903  Mmux_t5_next101 (t5_next<3>)
579
     LUT6:I0->O            3   0.068   0.431  Mmux_tabval_next103 (Mmux_tabval_next102)
580
     LUT6:I5->O            1   0.068   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_lut<3> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_lut<3>)
581
     MUXCY:S->O            1   0.290   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<3> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<3>)
582
     MUXCY:CI->O           1   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<4> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<4>)
583
     MUXCY:CI->O           1   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<5> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<5>)
584
     MUXCY:CI->O           1   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<6> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<6>)
585
     MUXCY:CI->O           1   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<7> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<7>)
586
     MUXCY:CI->O           1   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<8> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<8>)
587
     MUXCY:CI->O           1   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<9> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<9>)
588
     MUXCY:CI->O           1   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<10> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<10>)
589
     MUXCY:CI->O           1   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<11> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<11>)
590
     MUXCY:CI->O           1   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<12> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<12>)
591
     MUXCY:CI->O           1   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<13> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<13>)
592
     MUXCY:CI->O           0   0.020   0.000  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<14> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<14>)
593
     XORCY:CI->O           2   0.239   0.497  Madd_z_reg[15]_tabval_next[15]_add_76_OUT_xor<15> (z_reg[15]_tabval_next[15]_add_76_OUT<15>)
594
     LUT6:I4->O            1   0.068   0.000  Mmux_z_next71 (z_next<15>)
595
     FDCE:D                    0.011          z_reg_15
596
    ----------------------------------------
597
    Total                      6.273ns (2.154ns logic, 4.119ns route)
598
                                       (34.3% logic, 65.7% route)
599
 
600
=========================================================================
601
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
602
  Total number of paths / destination ports: 619 / 396
603
-------------------------------------------------------------------------
604
Offset:              2.513ns (Levels of Logic = 4)
605
  Source:            mode<3> (PAD)
606
  Destination:       offset_reg_4 (FF)
607
  Destination Clock: clk rising
608
 
609
  Data Path: mode<3> to offset_reg_4
610
                                Gate     Net
611
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
612
    ----------------------------------------  ------------
613
     LUT5:I4->O            2   0.068   0.784  Mmux_lmode_next101 (lmode_next<3>)
614
     LUT6:I0->O            2   0.068   0.644  GND_6_o_lmode_next[15]_equal_37_o<15>11 (GND_6_o_lmode_next[15]_equal_37_o<15>11)
615
     LUT6:I2->O            2   0.068   0.784  GND_6_o_lmode_next[15]_equal_39_o<15>1 (GND_6_o_lmode_next[15]_equal_39_o)
616
     LUT6:I0->O            1   0.068   0.000  Mmux_t0_next[15]_GND_6_o_mux_39_OUT111 (t0_next[15]_GND_6_o_mux_39_OUT<4>)
617
     FDCE:D                    0.011          offset_reg_4
618
    ----------------------------------------
619
    Total                      2.513ns (0.301ns logic, 2.212ns route)
620
                                       (12.0% logic, 88.0% route)
621
 
622
=========================================================================
623
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
624
  Total number of paths / destination ports: 54 / 50
625
-------------------------------------------------------------------------
626
Offset:              1.256ns (Levels of Logic = 1)
627
  Source:            current_state_FSM_FFd3 (FF)
628
  Destination:       ready (PAD)
629
  Source Clock:      clk rising
630
 
631
  Data Path: current_state_FSM_FFd3 to ready
632
                                Gate     Net
633
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
634
    ----------------------------------------  ------------
635
     FDC:C->Q            395   0.375   0.813  current_state_FSM_FFd3 (current_state_FSM_FFd3)
636
     LUT3:I0->O            0   0.068   0.000  current_state__n0432<0>1 (ready)
637
    ----------------------------------------
638
    Total                      1.256ns (0.443ns logic, 0.813ns route)
639
                                       (35.3% logic, 64.7% route)
640
 
641
=========================================================================
642
 
643
Cross Clock Domains Report:
644
--------------------------
645
 
646
Clock to Setup on destination clock clk
647
---------------+---------+---------+---------+---------+
648
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
649
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
650
---------------+---------+---------+---------+---------+
651
clk            |    6.273|         |         |         |
652
---------------+---------+---------+---------+---------+
653
 
654
=========================================================================
655
 
656
 
657
Total REAL time to Xst completion: 38.00 secs
658
Total CPU time to Xst completion: 37.57 secs
659
 
660
-->
661
 
662
Total memory usage is 261536 kilobytes
663
 
664
Number of errors   :    0 (   0 filtered)
665
Number of warnings :  194 (   0 filtered)
666
Number of infos    :   11 (   0 filtered)
667
 

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