OpenCores
URL https://opencores.org/ocsvn/layer2/layer2/trunk

Subversion Repositories layer2

[/] [layer2/] [trunk/] [vhdl/] [rs232/] [rtl/] [counter.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 idiolatrie
--------------------------------------------------------------------------------
2
-- Baud Rate Counter                                                          --
3
--------------------------------------------------------------------------------
4
-- Copyright (C)2011  Mathias Hörtnagl <mathias.hoertnagl@gmail.comt>         --
5
--                                                                            --
6
-- This program is free software: you can redistribute it and/or modify       --
7
-- it under the terms of the GNU General Public License as published by       --
8
-- the Free Software Foundation, either version 3 of the License, or          --
9
-- (at your option) any later version.                                        --
10
--                                                                            --
11
-- This program is distributed in the hope that it will be useful,            --
12
-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --
13
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --
14
-- GNU General Public License for more details.                               --
15
--                                                                            --
16
-- You should have received a copy of the GNU General Public License          --
17
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.      --
18
--------------------------------------------------------------------------------
19
library ieee;
20
use ieee.std_logic_1164.all;
21
use ieee.numeric_std.all;
22
 
23
entity counter is
24
   generic(
25
      FREQ : positive := 50;           -- Clock frequency in MHz.
26
      RATE : positive := 19200         -- Baud rate (times sampling rate).
27
   );
28
   port(
29
      clk    : in  std_logic;
30
      rst    : in  std_logic;
31
      tick   : out std_logic
32
   );
33
end counter;
34
 
35
architecture rtl of counter is
36
 
37
   constant MAX : positive := (FREQ*1000000)/(RATE*16);
38
 
39
   signal c, cin : natural range 0 to MAX;
40
begin
41
 
42
   tick <= '1' when c = MAX else '0';
43
   cin  <=  0  when c = MAX else c + 1;
44
 
45
   reg : process (clk)
46
   begin
47
      if rising_edge(clk) then
48
         if rst = '1' then
49
            c <= 0;
50
         else
51
            c <= cin;
52
         end if;
53
      end if;
54
   end process;
55
end rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.