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#

# Xilinx Core Generator version 13.4

# Date: Thu May 24 21:21:25 2012

#

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#

#  This file contains the customisation parameters for a

#  Xilinx CORE Generator IP GUI. It is strongly recommended

#  that you do not manually alter this file as it may cause

#  unexpected and unsupported behavior.

#

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#

#  Generated from component: xilinx.com:ip:chipscope_vio:1.05.a

#

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#

# BEGIN Project Options

SET addpads = false

SET asysymbol = true

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = false

SET designentry = Verilog

SET device = xc3s500e

SET devicefamily = spartan3e

SET flowvendor = Other

SET formalverification = false

SET foundationsym = false

SET implementationfiletype = Ngc

SET package = fg320

SET removerpms = false

SET simulationfiles = Structural

SET speedgrade = -4

SET verilogsim = true

SET vhdlsim = false

# END Project Options

# BEGIN Select

SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a

# END Select

# BEGIN Parameters

CSET asynchronous_input_port_width=8

CSET asynchronous_output_port_width=8

CSET component_name=coreVIO

CSET constraint_type=external

CSET enable_asynchronous_input_port=false

CSET enable_asynchronous_output_port=false

CSET enable_synchronous_input_port=false

CSET enable_synchronous_output_port=true

CSET example_design=true

CSET invert_clock_input=true

CSET synchronous_input_port_width=8

CSET synchronous_output_port_width=19

# END Parameters

# BEGIN Extra information

MISC pkg_timestamp=2012-01-07T09:20:13Z

# END Extra information

GENERATE

# CRC: d7309c64