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[/] [loadbalancer/] [trunk/] [ARP/] [arp_response.vhd] - Blame information for rev 2

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1 2 atalla 
---this file could be used to build ARP RESPONSE
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--------------------------------------------------------
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        LIBRARY IEEE;
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        USE IEEE.STD_LOGIC_1164.ALL;
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        use ieee.numeric_std.all;
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        use IEEE.STD_LOGIC_ARITH.ALL;
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        use IEEE.STD_LOGIC_UNSIGNED.ALL;
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        USE WORK.CONFIG.ALL;
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-------------------------------
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        ENTITY  arp_response IS
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        GENERIC(DATA_WIDTH :INTEGER := 64;
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                        CTRL_WIDTH :INTEGER := 8);
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        PORT(
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        SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
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        SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
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    SIGNAL out_wr : OUT STD_LOGIC;
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        SIGNAL header : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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     --- ethr  header
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    SIGNAL src_mac : IN STD_LOGIC_VECTOR(47 DOWNTO 0); --ethernet source MAC
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        SIGNAL SHA :IN STD_LOGIC_VECTOR(47 DOWNTO 0);--Sender hardware address (SHA)    Hardware (MAC) address of the sender.
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        SIGNAL SPA :IN STD_LOGIC_VECTOR(31 DOWNTO 0);--Sender protocol address (SPA)    Upper layer protocol address of the sender.
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        SIGNAL THA : IN STD_LOGIC_VECTOR(47 DOWNTO 0);--Hardware address of the intended receiver. This field is ignored in requests.
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        SIGNAL TPA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);-- Upper layer protocol address of the intended receiver.
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    --- Misc
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    SIGNAL rdy :IN STD_LOGIC;
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    SIGNAL reset :IN STD_LOGIC;
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    SIGNAL clk   :IN STD_LOGIC
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        );
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        END ENTITY;
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 ------------------------------------------------------
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        ARCHITECTURE behavior OF arp_response IS
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------------ one hot encoding state definition
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        TYPE state_type is (IDLE, WRITE_HEADER, WRITE_WORD_1 , WRITE_WORD_2, WRITE_WORD_3,
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                                                WRITE_WORD_4,WRITE_WORD_5, WRITE_WORD_6,WRITE_DUMP1,WRITE_DUMP2, WAIT_EOP);
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        ATTRIBUTE enum_encoding: STRING;
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        ATTRIBUTE enum_encoding OF state_type: TYPE IS "onehot";
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        SIGNAL state, state_next: state_type;
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------------end state machine definition
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---------------internal signals
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    SIGNAL              out_data_p                      :   STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
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        SIGNAL          out_ctrl_p                      :   STD_LOGIC_VECTOR(CTRL_WIDTH-1 DOWNTO 0);
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    SIGNAL              out_wr_p                        :       STD_LOGIC;
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        SIGNAL          source_port                     :       STD_LOGIC_VECTOR(1 DOWNTO 0);--just four ports
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        SIGNAL          dest_port                       :       STD_LOGIC_VECTOR(15 DOWNTO 0);--just four ports
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-------------------------------------------
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        BEGIN
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           PROCESS(clk)
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                BEGIN
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                        IF RISING_EDGE( clk )THEN
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                                        IF( rdy ='1' ) THEN
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                                                IF header(31 DOWNTO 16)=X"0000" THEN
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                                                                source_port <= "00";
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                                                                dest_port <= X"0001";
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                                                        ELSIF header(31 DOWNTO 16)=X"0002" THEN
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                                                                source_port <= "01";
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                                                                dest_port <= X"0004";
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                                                        ELSIF header(31 DOWNTO 16)=X"0004" THEN
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                                                                source_port <= "10";
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                                                                dest_port <= X"0010";
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                                                        ELSIF header(31 DOWNTO 16)=X"0006" THEN
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                                                                source_port <= "11";
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                                                                dest_port <= X"0040";
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                                                END IF;
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                                        END IF;
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                        END IF;
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                END PROCESS;
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                PROCESS(reset,clk)
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                BEGIN
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                        IF (reset ='1') THEN
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                                        state                                                           <=      IDLE;
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                        ELSIF clk'EVENT AND clk ='1' THEN
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                                        state                                                           <=      state_next;
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                        END IF;
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                END PROCESS;
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                PROCESS(state, rdy)
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                BEGIN
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                                        state_next                                                      <=      state;
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                        CASE state IS
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                        WHEN IDLE =>
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                                IF rdy ='1' THEN
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                                        state_next                                      <=      WRITE_HEADER;
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                                END IF;
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                        WHEN WRITE_HEADER =>
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                                        state_next                                      <=      WRITE_WORD_1;
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                        WHEN WRITE_WORD_1 =>
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                                        state_next                                      <=      WRITE_WORD_2;
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                        WHEN WRITE_WORD_2 =>
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                                        state_next                                      <=      WRITE_WORD_3;
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                        WHEN WRITE_WORD_3 =>
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                                        state_next                                      <=      WRITE_WORD_4;
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                        WHEN WRITE_WORD_4 =>
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                                        state_next                                              <=      WRITE_WORD_5;
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                        WHEN WRITE_WORD_5 =>
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                                        state_next                                              <=      WRITE_WORD_6;
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                        WHEN WRITE_WORD_6 =>
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                                        state_next                                              <=      WRITE_DUMP1;
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                        WHEN WRITE_DUMP1 =>
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                                        state_next                                              <=      WRITE_DUMP2;
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                        WHEN WRITE_DUMP2 =>
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                                        state_next                                              <=      WAIT_EOP;
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                        WHEN WAIT_EOP =>
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                                        state_next                                                      <=      IDLE;
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                        WHEN OTHERS =>
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                                        state_next                                                      <=      IDLE;
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                        END CASE;
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                END PROCESS;
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                -------------------OUTPUT ASSIGNMENT
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                with state select
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                 out_data_p <= dest_port & X"0008" & header(31 DOWNTO 16)&X"0040" WHEN WRITE_HEADER,
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                                           src_mac & mac_array(CONV_INTEGER(source_port))(47 downto 32) when WRITE_WORD_1,
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                                           mac_array(CONV_INTEGER(source_port))(31 downto 0) & X"0806" & X"0001" when WRITE_WORD_2,
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                                           X"0800" & X"06" & X"04" & X"0002" & mac_array(CONV_INTEGER(source_port))(47 downto 32) when WRITE_WORD_3,
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                                           mac_array(CONV_INTEGER(source_port))(31 downto 0) & TPA WHEN WRITE_WORD_4,
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                                           SHA & SPA(31 DOWNTO 16) WHEN WRITE_WORD_5,
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                                           SPA(15 DOWNTO 0) & ( X"000000000000") WHEN WRITE_WORD_6,
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                                           X"0000000000000000" WHEN WRITE_DUMP1,
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                                           X"0000000000000000" WHEN WRITE_DUMP2,
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                                           ( OTHERS=>'0') when others;
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           with state select
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                                 out_wr_p <= '1' when WRITE_HEADER|WRITE_WORD_1| WRITE_WORD_2| WRITE_WORD_3|WRITE_WORD_4| WRITE_WORD_5|WRITE_WORD_6| WRITE_DUMP1|WRITE_DUMP2,
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                                                           '0' when others;
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                with state select
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                                 out_ctrl_p <= X"FF" when WRITE_HEADER,
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                                                           X"00" WHEN WRITE_WORD_1| WRITE_WORD_2| WRITE_WORD_3|WRITE_WORD_4| WRITE_WORD_5|WRITE_WORD_6 | WRITE_DUMP1,
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                                                           X"01" WHEN WRITE_DUMP2,
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                                                           X"00" when others;
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                PROCESS(reset, clk)
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                BEGIN
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                IF (reset ='1') THEN
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                    out_data<=(others=>'0');
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                        out_ctrl<=(others=>'0');
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                        out_wr<='0';
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                ELSIF clk'EVENT AND clk ='1' THEN
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                        out_data<=out_data_p;
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                        out_ctrl<=out_ctrl_p;
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                        out_wr<=out_wr_p;
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                END IF;
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                END PROCESS;
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END behavior;
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