URL
https://opencores.org/ocsvn/loadbalancer/loadbalancer/trunk
[/] [loadbalancer/] [trunk/] [LB.fit.summary] - Blame information for rev 2
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
2 |
atalla |
Fitter Status : Successful - Sun Jan 10 21:12:58 2010
|
| 2 |
|
|
Quartus II Version : 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
|
| 3 |
|
|
Revision Name : LB
|
| 4 |
|
|
Top-level Entity Name : LB
|
| 5 |
|
|
Family : Stratix II
|
| 6 |
|
|
Device : EP2S15F484C3
|
| 7 |
|
|
Timing Models : Final
|
| 8 |
|
|
Logic utilization : 8 %
|
| 9 |
|
|
Combinational ALUTs : 524 / 12,480 ( 4 % )
|
| 10 |
|
|
Dedicated logic registers : 870 / 12,480 ( 7 % )
|
| 11 |
|
|
Total registers : 870
|
| 12 |
|
|
Total pins : 145 / 343 ( 42 % )
|
| 13 |
|
|
Total virtual pins : 0
|
| 14 |
|
|
Total block memory bits : 154,560 / 419,328 ( 37 % )
|
| 15 |
|
|
DSP block 9-bit elements : 0 / 96 ( 0 % )
|
| 16 |
|
|
Total PLLs : 0 / 6 ( 0 % )
|
| 17 |
|
|
Total DLLs : 0 / 2 ( 0 % )
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
