| 1 |
2 |
atalla |
Flow report for LB
|
| 2 |
|
|
Sun Jan 10 21:13:57 2010
|
| 3 |
|
|
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
|
| 4 |
|
|
|
| 5 |
|
|
|
| 6 |
|
|
---------------------
|
| 7 |
|
|
; Table of Contents ;
|
| 8 |
|
|
---------------------
|
| 9 |
|
|
1. Legal Notice
|
| 10 |
|
|
2. Flow Summary
|
| 11 |
|
|
3. Flow Settings
|
| 12 |
|
|
4. Flow Non-Default Global Settings
|
| 13 |
|
|
5. Flow Elapsed Time
|
| 14 |
|
|
6. Flow Log
|
| 15 |
|
|
|
| 16 |
|
|
|
| 17 |
|
|
|
| 18 |
|
|
----------------
|
| 19 |
|
|
; Legal Notice ;
|
| 20 |
|
|
----------------
|
| 21 |
|
|
Copyright (C) 1991-2007 Altera Corporation
|
| 22 |
|
|
Your use of Altera Corporation's design tools, logic functions
|
| 23 |
|
|
and other software and tools, and its AMPP partner logic
|
| 24 |
|
|
functions, and any output files from any of the foregoing
|
| 25 |
|
|
(including device programming or simulation files), and any
|
| 26 |
|
|
associated documentation or information are expressly subject
|
| 27 |
|
|
to the terms and conditions of the Altera Program License
|
| 28 |
|
|
Subscription Agreement, Altera MegaCore Function License
|
| 29 |
|
|
Agreement, or other applicable license agreement, including,
|
| 30 |
|
|
without limitation, that your use is for the sole purpose of
|
| 31 |
|
|
programming logic devices manufactured by Altera and sold by
|
| 32 |
|
|
Altera or its authorized distributors. Please refer to the
|
| 33 |
|
|
applicable agreement for further details.
|
| 34 |
|
|
|
| 35 |
|
|
|
| 36 |
|
|
|
| 37 |
|
|
+-------------------------------------------------------------------------------+
|
| 38 |
|
|
; Flow Summary ;
|
| 39 |
|
|
+-------------------------------+-----------------------------------------------+
|
| 40 |
|
|
; Flow Status ; Successful - Sun Jan 10 21:13:56 2010 ;
|
| 41 |
|
|
; Quartus II Version ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
|
| 42 |
|
|
; Revision Name ; LB ;
|
| 43 |
|
|
; Top-level Entity Name ; LB ;
|
| 44 |
|
|
; Family ; Stratix II ;
|
| 45 |
|
|
; Met timing requirements ; Yes ;
|
| 46 |
|
|
; Logic utilization ; 8 % ;
|
| 47 |
|
|
; Combinational ALUTs ; 524 / 12,480 ( 4 % ) ;
|
| 48 |
|
|
; Dedicated logic registers ; 870 / 12,480 ( 7 % ) ;
|
| 49 |
|
|
; Total registers ; 870 ;
|
| 50 |
|
|
; Total pins ; 145 / 343 ( 42 % ) ;
|
| 51 |
|
|
; Total virtual pins ; 0 ;
|
| 52 |
|
|
; Total block memory bits ; 154,560 / 419,328 ( 37 % ) ;
|
| 53 |
|
|
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
|
| 54 |
|
|
; Total PLLs ; 0 / 6 ( 0 % ) ;
|
| 55 |
|
|
; Total DLLs ; 0 / 2 ( 0 % ) ;
|
| 56 |
|
|
; Device ; EP2S15F484C3 ;
|
| 57 |
|
|
; Timing Models ; Final ;
|
| 58 |
|
|
+-------------------------------+-----------------------------------------------+
|
| 59 |
|
|
|
| 60 |
|
|
|
| 61 |
|
|
+-----------------------------------------+
|
| 62 |
|
|
; Flow Settings ;
|
| 63 |
|
|
+-------------------+---------------------+
|
| 64 |
|
|
; Option ; Setting ;
|
| 65 |
|
|
+-------------------+---------------------+
|
| 66 |
|
|
; Start date & time ; 01/10/2010 21:10:54 ;
|
| 67 |
|
|
; Main task ; Compilation ;
|
| 68 |
|
|
; Revision Name ; LB ;
|
| 69 |
|
|
+-------------------+---------------------+
|
| 70 |
|
|
|
| 71 |
|
|
|
| 72 |
|
|
+-----------------------------------------------------------------------------------------+
|
| 73 |
|
|
; Flow Non-Default Global Settings ;
|
| 74 |
|
|
+------------------------------------+---------+---------------+-------------+------------+
|
| 75 |
|
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
| 76 |
|
|
+------------------------------------+---------+---------------+-------------+------------+
|
| 77 |
|
|
; FMAX_REQUIREMENT ; 125 MHz ; -- ; -- ; -- ;
|
| 78 |
|
|
; PARTITION_COLOR ; 2147039 ; -- ; -- ; Top ;
|
| 79 |
|
|
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
|
| 80 |
|
|
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_palace ;
|
| 81 |
|
|
+------------------------------------+---------+---------------+-------------+------------+
|
| 82 |
|
|
|
| 83 |
|
|
|
| 84 |
|
|
+------------------------------------------------------------------+
|
| 85 |
|
|
; Flow Elapsed Time ;
|
| 86 |
|
|
+-------------------------+--------------+-------------------------+
|
| 87 |
|
|
; Module Name ; Elapsed Time ; Average Processors Used ;
|
| 88 |
|
|
+-------------------------+--------------+-------------------------+
|
| 89 |
|
|
; Analysis & Synthesis ; 00:00:48 ; 1.0 ;
|
| 90 |
|
|
; Fitter ; 00:01:11 ; 1.0 ;
|
| 91 |
|
|
; Assembler ; 00:00:34 ; 1.0 ;
|
| 92 |
|
|
; Classic Timing Analyzer ; 00:00:08 ; 1.0 ;
|
| 93 |
|
|
; Total ; 00:02:41 ; -- ;
|
| 94 |
|
|
+-------------------------+--------------+-------------------------+
|
| 95 |
|
|
|
| 96 |
|
|
|
| 97 |
|
|
------------
|
| 98 |
|
|
; Flow Log ;
|
| 99 |
|
|
------------
|
| 100 |
|
|
quartus_map --read_settings_files=on --write_settings_files=off LB -c LB
|
| 101 |
|
|
quartus_fit --read_settings_files=off --write_settings_files=off LB -c LB
|
| 102 |
|
|
quartus_asm --read_settings_files=off --write_settings_files=off LB -c LB
|
| 103 |
|
|
quartus_tan --read_settings_files=off --write_settings_files=off LB -c LB --timing_analysis_only
|
| 104 |
|
|
|
| 105 |
|
|
|
| 106 |
|
|
|
