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[/] [loadbalancer/] [trunk/] [PASS/] [pass.vhd] - Blame information for rev 2

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1 2 atalla
--------------------------------------------------------
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        LIBRARY IEEE;
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        USE IEEE.STD_LOGIC_1164.ALL;
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        use IEEE.std_logic_arith.all;
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-------------------------------
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        ENTITY pass IS
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        GENERIC(DATA_WIDTH :INTEGER := 64;
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                        CTRL_WIDTH :INTEGER := 8);
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        PORT(
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        SIGNAL          in_data                         :       IN      STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
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        SIGNAL          in_ctrl                         :       IN      STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
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    SIGNAL              in_wr                           :       IN              STD_LOGIC       ;
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        SIGNAL          in_rdy                          :       OUT     STD_LOGIC       ;
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        SIGNAL          out_data                        :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
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        SIGNAL          out_ctrl                        :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
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        SIGNAL          out_wr                          :       OUT     STD_LOGIC       ;
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        SIGNAL          out_rdy                         :       IN              STD_LOGIC       ;
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    --- Misc
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    SIGNAL     en : IN STD_LOGIC;
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    SIGNAL              reset                           :       IN              STD_LOGIC       ;
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    SIGNAL              clk                             :       IN              STD_LOGIC
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        );
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        END ENTITY;
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 ------------------------------------------------------
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        ARCHITECTURE behavior OF pass IS
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-------COMPONENET SMALL FIFO
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                COMPONENT  small_fifo IS
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        GENERIC(WIDTH :INTEGER := 72;
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                        MAX_DEPTH_BITS :INTEGER := 3);
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        PORT(
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     SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din,     // Data in
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     SIGNAL wr_en : IN STD_LOGIC;--input          wr_en,   // Write enable
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     SIGNAL rd_en : IN STD_LOGIC;--input          rd_en,   // Read the next word 
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     SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
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     SIGNAL full : OUT STD_LOGIC;--output         full,
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     SIGNAL nearly_full : OUT STD_LOGIC;--output         nearly_full,
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     SIGNAL empty : OUT STD_LOGIC;--output         empty,
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    SIGNAL reset :IN STD_LOGIC;
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    SIGNAL clk   :IN STD_LOGIC
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        );
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        END COMPONENT;
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-------COMPONENET SMALL FIFO
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------------ one hot encoding state definition
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        TYPE state_type IS (IDLE, IN_MODULE_HDRS,SKIP_HDRS, IN_PACKET, DUMP_1,DUMP_2,DUMP_3);
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        ATTRIBUTE enum_encoding: STRING;
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        ATTRIBUTE enum_encoding of state_type : type is "onehot";
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        SIGNAL state, state_NEXT : state_type;
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------------end state machine definition
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----------------------FIFO        
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          SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
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          SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);
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          SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
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      SIGNAL in_fifo_rd_en : STD_LOGIC;
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          SIGNAL in_fifo_rd_en_p : STD_LOGIC;
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          SIGNAL in_fifo_go : STD_LOGIC;
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          SIGNAL in_fifo_go_i : STD_LOGIC;
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      SIGNAL in_fifo_dout  : STD_LOGIC_VECTOR(71 DOWNTO 0);
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      SIGNAL in_fifo_full : STD_LOGIC;
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      SIGNAL in_fifo_nearly_full : STD_LOGIC;
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      SIGNAL in_fifo_empty : STD_LOGIC;
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                 SIGNAL wr_en : STD_LOGIC;
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          SIGNAL                out_data_i                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
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          SIGNAL                out_ctrl_i                      :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
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          SIGNAL                out_wr_i                        :               STD_LOGIC       ;
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---------------------------------------------------
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        BEGIN
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        ------PORT MAP open_header
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                -------PORT MAP SMALL FIFO DATA
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                small_fifo_Inst :  small_fifo
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        GENERIC MAP(WIDTH  => 72,
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                        MAX_DEPTH_BITS  => 5)
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        PORT MAP(
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      din =>(in_fifo_in),
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      wr_en =>wr_en,
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      rd_en => in_fifo_rd_en,
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      dout =>in_fifo_dout,
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      full =>in_fifo_full,
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      nearly_full =>in_fifo_nearly_full,
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      empty => in_fifo_empty,
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     reset => reset ,
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     clk  => clk
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        );
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-------PORT MAP SMALL FIFO
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-----------------------
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      in_fifo_in <=     in_data & in_ctrl ;
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                wr_en <= en and in_wr;
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                fifo_data       <=         in_fifo_dout(71 DOWNTO 8)    ;
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                fifo_ctrl       <=      in_fifo_dout(7 DOWNTO 0) ;
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                in_fifo_rd_en <=  out_rdy and(not in_fifo_empty) ;
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                  in_rdy        <=      (NOT in_fifo_nearly_full) ;--or (not en)        ;
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PROCESS(clk,reset)
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BEGIN
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                IF clk'EVENT AND clk ='1' THEN
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                                IF (reset ='1') THEN
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                                        out_wr_i <='0';
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                                else
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                                out_wr_i <= in_fifo_rd_en;
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                                end if;
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        END IF;
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END PROCESS;
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                                                                        out_data_i                              <=      fifo_data;
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                                                                        out_ctrl_i                              <=      fifo_ctrl;
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---------------Register output
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--              PROCESS(clk,reset)
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--              BEGIN
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--                      
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--                      IF clk'EVENT AND clk ='1' THEN
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                                                                        out_data                                <=      out_data_i;
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                                                                        out_ctrl                                <=      out_ctrl_i;
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                                                                        out_wr                              <=  out_wr_i;
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--                                                                      
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--                      END IF;
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--              END PROCESS;    
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END behavior;
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