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[/] [loadbalancer/] [trunk/] [Router/] [router.vhd] - Blame information for rev 2

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1 2 atalla
--------------------------------------------------------
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        LIBRARY IEEE;
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        USE IEEE.STD_LOGIC_1164.ALL;
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        USE WORK.CONFIG.ALL;
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-------------------------------
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        ENTITY  router  IS
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        GENERIC(DATA_WIDTH :INTEGER := 64;
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                        CTRL_WIDTH :INTEGER := 8);
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        PORT(
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         SIGNAL in_data :IN   STD_LOGIC_VECTOR(63 DOWNTO 0);
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         SIGNAL in_ctrl : IN   STD_LOGIC_VECTOR(7 DOWNTO 0);
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    SIGNAL in_wr :IN STD_LOGIC;
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         SIGNAL in_rdy : OUT STD_LOGIC;
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        ----------------
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        -------------------
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         SIGNAL out_data : OUT   STD_LOGIC_VECTOR(63 DOWNTO 0);
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         SIGNAL out_ctrl : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
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    SIGNAL out_wr : OUT STD_LOGIC;
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         SIGNAL out_rdy : IN STD_LOGIC;
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         SIGNAL     en : IN STD_LOGIC;
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    SIGNAL reset :IN STD_LOGIC;
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    SIGNAL clk   :IN STD_LOGIC
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        );
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        END ENTITY router ;
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 ------------------------------------------------------
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        ARCHITECTURE behavior OF router  IS
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        -------COMPONENET SMALL FIFO
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                COMPONENT  small_fifo IS
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        GENERIC(WIDTH :INTEGER := 72;
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                        MAX_DEPTH_BITS :INTEGER := 3);
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        PORT(
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     SIGNAL din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);--input [WIDTH-1:0] din,     // Data in
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     SIGNAL wr_en : IN STD_LOGIC;--input          wr_en,   // Write enable
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     SIGNAL rd_en : IN STD_LOGIC;--input          rd_en,   // Read the next word 
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     SIGNAL dout :OUT STD_LOGIC_VECTOR(71 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
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     SIGNAL full : OUT STD_LOGIC;--output         full,
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     SIGNAL nearly_full : OUT STD_LOGIC;--output         nearly_full,
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     SIGNAL empty : OUT STD_LOGIC;--output         empty,
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    SIGNAL reset :IN STD_LOGIC;
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    SIGNAL clk   :IN STD_LOGIC
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        );
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        END COMPONENT;
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------------ one hot encoding state definition
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        TYPE state_type IS (IDLE , IN_MODULE_HDRS, READ_WORD1, IN_PACKET);
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        ATTRIBUTE enum_encoding: STRING;
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        ATTRIBUTE enum_encoding of state_type : type is "onehot";
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        SIGNAL state, state_next : state_type;
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--------------------------------------------------------------
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-------------------------------------------
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     SIGNAL data_in :STD_LOGIC_VECTOR(71 DOWNTO 0);
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          SIGNAL rd_en : STD_LOGIC;
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     SIGNAL dout : STD_LOGIC_VECTOR(71 DOWNTO 0);
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     SIGNAL fifo_data :STD_LOGIC_VECTOR(63 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
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          SIGNAL fifo_ctrl :STD_LOGIC_VECTOR(7 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
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     SIGNAL full : STD_LOGIC;--output         full,
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     SIGNAL nearly_full : STD_LOGIC;--output         nearly_full,
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     SIGNAL empty : STD_LOGIC;--output         empty,
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        -----------------------------------------
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         SIGNAL                 in_data_int                     :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
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         SIGNAL                 in_ctrl_int             :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
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         SIGNAL                 in_wr_int                       :                       STD_LOGIC       ;
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         SIGNAL                 in_rdy_int                      :                       STD_LOGIC       ;
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                 SIGNAL                 wr_en                   :                       STD_LOGIC       ;
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        BEGIN
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        -------PORT MAP SMALL FIFO
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                small_fifo_Inst :  small_fifo
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        GENERIC MAP(WIDTH  => 72,
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                        MAX_DEPTH_BITS  => 3)
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        PORT MAP(
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      din =>(data_in),
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      wr_en =>wr_en,
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      rd_en => rd_en,
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      dout =>dout,
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      full =>full,
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      nearly_full =>nearly_full,
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      empty => empty,
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     reset => reset ,
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     clk  => clk
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        );
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-------PORT MAP SMALL FIFO
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                wr_en <= en and in_wr;
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                in_rdy <=  NOT nearly_full;
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--              rd_en <= out_rdy AND (NOT empty) AND fifo_go;
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                fifo_data <=dout(71 DOWNTO 8);
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                fifo_ctrl <=DOUT(7 DOWNTO 0);
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                data_in<=in_data & in_ctrl;
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                PROCESS(reset,clk)
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                BEGIN
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                        IF (reset ='1') THEN
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                                state <=IDLE;
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                        ELSIF clk'EVENT AND clk ='1' THEN
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                                state<=state_next;
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                        END IF;
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                END PROCESS;
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                PROCESS(state, fifo_data, fifo_ctrl )
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                        BEGIN
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                            in_data_int <= fifo_data;
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                                 in_ctrl_int <= fifo_ctrl;
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                                 in_wr_int   <= '0';
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                                 rd_en           <= '0';
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                                state_next <= state;
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                                CASE state IS
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                                        WHEN IDLE =>
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                                                   IF(empty = '0') THEN
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                                                                                           rd_en                                        <= '1';
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                                                                                           state_next                           <= IN_MODULE_HDRS;
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                                                END IF;
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                                        WHEN IN_MODULE_HDRS =>
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                                                IF (out_rdy='1'  ) THEN
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--                                                      IF (out_rdy='1'  ) THEN
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                                                                        in_data_int(63 DOWNTO 48)<= DEFAULT_INT_PORT;
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                                                                        in_wr_int   <= '1';
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                                                                    rd_en               <= '1';
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                                                                    state_next  <= READ_WORD1;
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                                                END IF;
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                                        WHEN READ_WORD1 =>
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                                                                        in_data_int(63 DOWNTO 16)<= VC_MAC;
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                                                        IF (out_rdy='1'  ) THEN
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                                                                         in_wr_int   <= '1';
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                                                                    rd_en               <= '1';
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                                                                    state_next  <= IN_PACKET;
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                                                END IF;
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                                        WHEN IN_PACKET          =>
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                                                IF ( fifo_ctrl /= X"00" ) THEN
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                                                                        IF ( out_rdy ='1' ) THEN
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                                                                        state_next               <= IDLE;
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                                                                        in_wr_int                               <=      '1' ;
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                                                                        END IF;
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                                                ELSIF(empty = '0' AND out_rdy ='1')THEN
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                                                                        rd_en                                   <=      '1'     ;
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                                                                        in_wr_int                       <=      '1' ;
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                                                END IF;
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                                END CASE;
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                        END PROCESS;
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 PROCESS(clk,reset)
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                BEGIN
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                        IF clk'EVENT AND clk ='1' THEN
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                                 out_data  <=   in_data_int ;
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                                 out_ctrl  <=   in_ctrl_int ;
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                                 out_wr   <=    in_wr_int ;
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                        END IF;
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                END PROCESS;
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END behavior;
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