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atalla |
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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USE IEEE.STD_LOGIC_MISC.ALL;
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USE WORK.CONFIG.ALL;
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entity mac_ram_table is
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generic (
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ADDR_WIDTH :integer := 10
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);
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port (
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clk: IN std_logic;
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reset : IN STD_LOGIC;
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in_mac_no_prt: IN std_logic_VECTOR(63 downto 0);--MAC NUMBER internal port
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in_address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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in_wr: IN std_logic;
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in_check : IN STD_LOGIC;
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match_address : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
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match: OUT STD_LOGIC;
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unmatch: OUT STD_LOGIC;
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in_rd : IN STD_LOGIC;
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in_key : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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last_address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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out_rd_rdy : OUT std_logic;
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-- vd_add_rm_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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-- vd_rm_out : OUT STD_LOGIC;
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out_port : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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out_mac : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
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);
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end mac_ram_table;
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architecture Behavioral of mac_ram_table is
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----------------------------------------------------------------
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COMPONENT valid_address is
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generic (
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ADDR_WIDTH :integer := ADDR_WIDTH
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);
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port (
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clk: IN std_logic;
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reset : IN STD_LOGIC;
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in_wr_address : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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in_wr: IN std_logic;
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in_key : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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in_rd : IN STD_LOGIC;
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in_rm_address_no : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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in_rm : IN STD_LOGIC;
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out_address : OUT STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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out_rdy : OUT std_logic
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);
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end COMPONENT valid_address;
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------------------------
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COMPONENT Aging_Timer is
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generic(
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N: integer := 32; -- 32 bits couter
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M: integer := 125000 -- 125000 = 1 miliscond
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);
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port(
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clk, reset: in std_logic;
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timeout: out std_logic;
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timer_aging_bit: out std_logic;
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count_out: out std_logic_vector(31 downto 0)--N-1
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);
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end COMPONENT Aging_Timer;
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----------------------------------------------------------------------------
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-------COMPONENET SMALL FIFO
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COMPONENT small_fifo IS
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GENERIC(WIDTH :INTEGER := 8;
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MAX_DEPTH_BITS :INTEGER := 5);
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PORT(
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SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din, // Data in
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SIGNAL wr_en : IN STD_LOGIC;--input wr_en, // Write enable
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SIGNAL rd_en : IN STD_LOGIC;--input rd_en, // Read the next word
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SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0] dout, // Data out
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SIGNAL full : OUT STD_LOGIC;--output full,
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SIGNAL nearly_full : OUT STD_LOGIC;--output nearly_full,
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SIGNAL empty : OUT STD_LOGIC;--output empty,
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SIGNAL reset :IN STD_LOGIC;
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SIGNAL clk :IN STD_LOGIC
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);
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END COMPONENT;
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-------COMPONENET SMALL FIFO
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------------------------------------------------------
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------------------------------------------------------------
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COMPONENT ram_256x48 is
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generic
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(
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DATA_WIDTH : natural := 48;
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ADDR_WIDTH : natural := ADDR_WIDTH
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);
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port
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(
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clk : in std_logic;
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raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
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waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
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data : in std_logic_vector((DATA_WIDTH-1) downto 0);
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we : in std_logic := '1';
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q : out std_logic_vector((DATA_WIDTH -1) downto 0)
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);
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end COMPONENT ram_256x48;
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TYPE state_type IS(IDLE, ADD_1, ADD_2, SCAN_1, SCAN_2);
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SIGNAL state, state_next : state_type;
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TYPE state_search_type IS(IDLE, CHECK, FOUND, UNFOUND);
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SIGNAL state_search : state_search_type;
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SIGNAL state_next_search : state_search_type;
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attribute enum_encoding : string;
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attribute enum_encoding of state_type : type is "onehot";
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------------------------------------------------------
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SIGNAL in_mac_no_prt_i : STD_LOGIC_VECTOR(55 DOWNTO 0);
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SIGNAL mac_prt : STD_LOGIC_VECTOR(55 DOWNTO 0);
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SIGNAL q_mac_prt : STD_LOGIC_VECTOR(55 DOWNTO 0);
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SIGNAL cnt : INTEGER ;
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SIGNAL in_check_p : STD_LOGIC;
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SIGNAL match_i : STD_LOGIC;
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SIGNAL unmatch_i : STD_LOGIC;
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---------------------------------------------------------------------------
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SIGNAL time_out : STD_LOGIC;
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SIGNAL timer_aging_bit : STD_LOGIC;
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---------------------------------------------------------------------------
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--------- Signals to connect with Valid Address Module-------------
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SIGNAL vd_add : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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SIGNAL vd_add_wr : STD_LOGIC;
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SIGNAL vd_in_rd : STD_LOGIC;
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SIGNAL vd_add_rm : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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SIGNAL vd_rm : STD_LOGIC;
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SIGNAL vd_out_add : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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SIGNAL vd_out_rdy : STD_LOGIC;
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SIGNAL out_rd_rdy_i : STD_LOGIC;
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---------------------------------------------------------------------------
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--------- Signals to connect with Fifo Module---------------------
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SIGNAL write_cmd_rd : STD_LOGIC;
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SIGNAL write_cmd_address : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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SIGNAL write_cmd_empty : STD_LOGIC;
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SIGNAL time_out_cmd_rd : STD_LOGIC;
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SIGNAL time_out_cmd_empty : STD_LOGIC;
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SIGNAL time_out_fifo_wr : STD_LOGIC;
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---------------------------------------------------------------------------
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--------- Signals to connect with VALID AGING Ram ----------------
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SIGNAL raddr_av : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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SIGNAL waddr_av : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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SIGNAL data_av : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL we_av : STD_LOGIC;
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SIGNAL ag_vd_q : STD_LOGIC_VECTOR(1 DOWNTO 0);
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---------------------------------------------------------------------------
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--------- Signals to connect with MAC reading Ram ----------------
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SIGNAL ram_mac_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
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-------------------------------------------------
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--------- Signals to connect with MAC Searching Ram ----------------
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SIGNAL ram_q : STD_LOGIC_VECTOR(55 DOWNTO 0);
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---------------------------------------------------------------------------
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SIGNAL cnt_1 : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
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SIGNAL cnt_1_restart : STD_LOGIC;
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SIGNAL cnt_1_up : STD_LOGIC;
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---------------------------------------------------------------------------
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begin
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---------------------------------------------------------------------------
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-------PORT MAP SMALL FIFO DATA
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------------------------
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Aging_Timer_Inst : Aging_Timer
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GENERIC MAP (
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N => 32 ,
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M => 1025000 -- = 1 --miliscond
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)
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port MAP(
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clk => clk,
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reset => reset,
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timeout =>open ,
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timer_aging_bit =>timer_aging_bit,
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count_out => open
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);
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time_out<='0';--testing without aging bit
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--Search new MAC inside the table the address
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ram_256x48_search_Inst : ram_256x48
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GENERIC MAP (
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DATA_WIDTH => 56, ADDR_WIDTH => ADDR_WIDTH)
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port MAP (
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clk => clk ,
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raddr => CONV_INTEGER(cnt) ,
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waddr => CONV_INTEGER(in_address) ,
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data => in_mac_no_prt(63 DOWNTO 8) ,
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we => in_wr ,
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q => ram_q
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);
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-----------------------------------------------------------------------
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PROCESS(clk, reset)
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BEGIN
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IF reset= '1' THEN
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state_search <= IDLE ;
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ELSIF clk'EVENT AND clk = '1' THEN
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state_search <= state_next_search ;
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IF(in_check = '1') THEN
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in_mac_no_prt_i <= in_mac_no_prt(63 DOWNTO 8);
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END IF;
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IF(match_i = '1') THEN
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match_address <= std_logic_vector(to_unsigned(cnt - 1, ADDR_WIDTH));
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END IF;
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END IF;
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END PROCESS;
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PROCESS(state_search, in_check, ram_q, in_mac_no_prt_i, cnt, last_address)
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BEGIN
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state_next_search <= state_search ;
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match_i <= '0' ;
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unmatch_i <= '0' ;
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| 222 |
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CASE state_search IS
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| 223 |
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WHEN IDLE =>
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| 224 |
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IF(in_check = '1' ) THEN
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| 225 |
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state_next_search <= CHECK ;
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| 226 |
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END IF;
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| 227 |
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WHEN CHECK =>
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| 228 |
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IF (ram_q = in_mac_no_prt_i )THEN
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match_i <= '1' ;
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state_next_search <= IDLE ;
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ELSIF (cnt = CONV_INTEGER(last_address)) THEN
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unmatch_i <= '1';
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state_next_search <= IDLE ;
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END IF;
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| 236 |
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WHEN OTHERS=>
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state_next_search <= IDLE ;
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| 239 |
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END CASE;
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| 240 |
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END PROCESS;
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| 242 |
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---------Register Out put--------------
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process (clk)
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| 244 |
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begin
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| 245 |
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if (rising_edge(clk)) then
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| 246 |
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match <= match_i;
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| 247 |
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unmatch <= unmatch_i;
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| 248 |
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end if;
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| 249 |
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end process;
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| 250 |
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| 251 |
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-----------------------------------------
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| 252 |
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| 253 |
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process (clk)
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| 254 |
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variable cnt1 : integer range 0 to 2**ADDR_WIDTH-1;
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| 255 |
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begin
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| 256 |
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if (rising_edge(clk)) then
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| 257 |
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| 258 |
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if reset = '1' then
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| 259 |
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cnt1 := 0;
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| 260 |
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elsIF(in_check = '1' ) THEN
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| 261 |
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cnt1 := 0;
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| 262 |
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else
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| 263 |
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cnt1 := cnt1 + 1;
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| 264 |
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end if;
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| 265 |
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end if;
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| 266 |
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cnt <= cnt1;
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| 267 |
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end process;
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| 269 |
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-------------------------------------------------------------------
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| 270 |
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-------------------------------------------------------------------
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| 271 |
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-------------------------------------------------------------------
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| 272 |
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--Write new MAC inside the table the address is provided by out side
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| 273 |
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ram_256x48_Inst : ram_256x48
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| 274 |
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| 275 |
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GENERIC MAP (
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| 276 |
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DATA_WIDTH => 56, ADDR_WIDTH => ADDR_WIDTH)
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| 277 |
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| 278 |
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port MAP (
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| 279 |
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clk => clk ,
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| 280 |
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raddr => CONV_INTEGER(vd_out_add) ,--this is coming from the valid address
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| 281 |
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waddr => CONV_INTEGER(in_address) ,
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| 282 |
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data => mac_prt ,--MAC=>PORT
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| 283 |
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we => in_wr ,
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| 284 |
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q => q_mac_prt --Next MAC address
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| 285 |
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);
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| 286 |
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mac_prt(55 DOWNTO 8) <= in_mac_no_prt(63 DOWNTO 16);
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| 287 |
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mac_prt(7 DOWNTO 0) <= in_mac_no_prt(7 DOWNTO 0);
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| 288 |
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out_mac <=q_mac_prt(55 DOWNTO 8);
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| 289 |
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out_port <=q_mac_prt(7 DOWNTO 0);
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| 290 |
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WRITE_command_Inst : small_fifo
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| 291 |
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GENERIC MAP(WIDTH => ADDR_WIDTH,
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| 292 |
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MAX_DEPTH_BITS => 5)
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| 293 |
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PORT MAP(
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| 294 |
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din => in_address,
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| 295 |
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wr_en => in_wr,
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| 296 |
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rd_en => write_cmd_rd,
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| 297 |
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dout => write_cmd_address,
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| 298 |
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full => open,
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| 299 |
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nearly_full => open,
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| 300 |
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empty => write_cmd_empty,
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| 301 |
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reset => reset ,
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| 302 |
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clk => clk
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| 303 |
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);
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| 304 |
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time_command_Inst : small_fifo
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| 305 |
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GENERIC MAP(WIDTH => 1,
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| 306 |
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MAX_DEPTH_BITS => 2)
|
| 307 |
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PORT MAP(
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| 308 |
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din => "1",
|
| 309 |
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wr_en => time_out_fifo_wr,
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| 310 |
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rd_en => time_out_cmd_rd,
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| 311 |
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dout => open,
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| 312 |
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full => open,
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| 313 |
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nearly_full => open,
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| 314 |
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empty => time_out_cmd_empty,
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| 315 |
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reset => reset ,
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| 316 |
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clk => clk
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| 317 |
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);
|
| 318 |
|
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time_out_fifo_wr <= time_out AND (time_out_cmd_empty);--onòy one element can be sotred in this
|
| 319 |
|
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-------------------------------------------------------------------
|
| 320 |
|
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------------------------------------------------------------
|
| 321 |
|
|
--Write new MAC inside the table the address is provided by out side
|
| 322 |
|
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Aging_Valid_256x48_Inst : ram_256x48
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| 323 |
|
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|
| 324 |
|
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GENERIC MAP (
|
| 325 |
|
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DATA_WIDTH => 2, ADDR_WIDTH => ADDR_WIDTH)
|
| 326 |
|
|
|
| 327 |
|
|
port MAP (
|
| 328 |
|
|
clk => clk ,
|
| 329 |
|
|
raddr => CONV_INTEGER(raddr_av) ,
|
| 330 |
|
|
waddr => CONV_INTEGER(waddr_av) ,
|
| 331 |
|
|
data => data_av ,
|
| 332 |
|
|
we => we_av ,
|
| 333 |
|
|
q => ag_vd_q
|
| 334 |
|
|
);
|
| 335 |
|
|
-------------------------------------------------------------------------------------
|
| 336 |
|
|
valid_address_Inst : valid_address
|
| 337 |
|
|
GENERIC MAP (ADDR_WIDTH =>ADDR_WIDTH)
|
| 338 |
|
|
PORT MAP (
|
| 339 |
|
|
clk => clk ,
|
| 340 |
|
|
reset => reset ,
|
| 341 |
|
|
in_wr_address => vd_add ,
|
| 342 |
|
|
in_wr => vd_add_wr ,
|
| 343 |
|
|
in_rd => in_rd ,
|
| 344 |
|
|
in_key => in_key ,
|
| 345 |
|
|
in_rm_address_no => vd_add_rm ,
|
| 346 |
|
|
in_rm => vd_rm ,
|
| 347 |
|
|
out_address => vd_out_add ,
|
| 348 |
|
|
out_rdy => vd_out_rdy
|
| 349 |
|
|
|
| 350 |
|
|
);
|
| 351 |
|
|
|
| 352 |
|
|
-------------------------------------------------------------------------------------
|
| 353 |
|
|
PROCESS(clk, reset)
|
| 354 |
|
|
BEGIN
|
| 355 |
|
|
IF reset= '1' THEN
|
| 356 |
|
|
state <= IDLE ;
|
| 357 |
|
|
ELSIF clk'EVENT AND clk = '1' THEN
|
| 358 |
|
|
state <= state_next ;
|
| 359 |
|
|
out_rd_rdy_i <= vd_out_rdy;
|
| 360 |
|
|
out_rd_rdy <= out_rd_rdy_i ;
|
| 361 |
|
|
END IF;
|
| 362 |
|
|
END PROCESS;
|
| 363 |
|
|
|
| 364 |
|
|
PROCESS(state, write_cmd_empty, time_out_cmd_empty,
|
| 365 |
|
|
write_cmd_address, timer_aging_bit, write_cmd_address, ag_vd_q, cnt_1)
|
| 366 |
|
|
BEGIN
|
| 367 |
|
|
vd_add_rm <= (OTHERS=>'0');
|
| 368 |
|
|
vd_rm <= '0';
|
| 369 |
|
|
vd_add <= (OTHERS=>'0');
|
| 370 |
|
|
vd_add_wr <= '0';
|
| 371 |
|
|
raddr_av <= (OTHERS=>'0');
|
| 372 |
|
|
waddr_av <= (OTHERS=>'0');
|
| 373 |
|
|
data_av <= (OTHERS=>'0');
|
| 374 |
|
|
we_av <= '0';
|
| 375 |
|
|
write_cmd_rd <= '0';
|
| 376 |
|
|
time_out_cmd_rd <= '0';
|
| 377 |
|
|
cnt_1_restart <= '0';
|
| 378 |
|
|
cnt_1_up <= '0';
|
| 379 |
|
|
state_next <= state ;
|
| 380 |
|
|
|
| 381 |
|
|
|
| 382 |
|
|
CASE state IS
|
| 383 |
|
|
|
| 384 |
|
|
WHEN IDLE =>
|
| 385 |
|
|
cnt_1_restart <= '1';
|
| 386 |
|
|
IF write_cmd_empty = '0' THEN
|
| 387 |
|
|
write_cmd_rd<= '1';
|
| 388 |
|
|
state_next <= ADD_1 ;
|
| 389 |
|
|
ELSIF(time_out_cmd_empty = '0' ) THEN
|
| 390 |
|
|
|
| 391 |
|
|
time_out_cmd_rd <= '1';
|
| 392 |
|
|
state_next <= SCAN_1 ;
|
| 393 |
|
|
END IF;
|
| 394 |
|
|
WHEN ADD_1 =>
|
| 395 |
|
|
---Read the Valid and Aging bit
|
| 396 |
|
|
raddr_av <= write_cmd_address ;
|
| 397 |
|
|
state_next <= ADD_2 ;
|
| 398 |
|
|
WHEN ADD_2 =>
|
| 399 |
|
|
---Write the Valid and Aging bit
|
| 400 |
|
|
data_av <= '1' & timer_aging_bit ;
|
| 401 |
|
|
waddr_av <= write_cmd_address ;
|
| 402 |
|
|
we_av <= '1' ;
|
| 403 |
|
|
--Write the Valid Address
|
| 404 |
|
|
vd_add <= write_cmd_address ;
|
| 405 |
|
|
vd_add_wr <= NOT ag_vd_q(1) ;
|
| 406 |
|
|
state_next <= IDLE ;
|
| 407 |
|
|
WHEN SCAN_1 =>
|
| 408 |
|
|
|
| 409 |
|
|
raddr_av <= cnt_1 ;
|
| 410 |
|
|
state_next <= SCAN_2 ;
|
| 411 |
|
|
|
| 412 |
|
|
WHEN SCAN_2 => cnt_1_up <= '1';
|
| 413 |
|
|
|
| 414 |
|
|
-- ELSIF cnt_1 = CONV_INTEGER(last_address)THEN --LAST ELEMNET REACHED
|
| 415 |
|
|
IF cnt_1 = CONV_INTEGER(last_address) THEN --LAST ELEMNET REACHED
|
| 416 |
|
|
state_next <= IDLE ;
|
| 417 |
|
|
|
| 418 |
|
|
ELSIF ( ag_vd_q(1) = '1' AND ( ag_vd_q(0) /= timer_aging_bit ) )THEN
|
| 419 |
|
|
-- data_av(1) <= '1';
|
| 420 |
|
|
-- data_av(0) <= ag_vd_q(0); --do not change it
|
| 421 |
|
|
-- we_av <= '1' ;
|
| 422 |
|
|
state_next <= SCAN_1 ;
|
| 423 |
|
|
|
| 424 |
|
|
ELSIF ( ag_vd_q(1) = '1' AND ( ag_vd_q(0) = timer_aging_bit ) )THEN
|
| 425 |
|
|
---delete this valid address
|
| 426 |
|
|
vd_add_rm <= cnt_1 ;
|
| 427 |
|
|
vd_rm <= '1';
|
| 428 |
|
|
-----------------------------
|
| 429 |
|
|
data_av(1) <= '0';
|
| 430 |
|
|
data_av(0) <= timer_aging_bit;
|
| 431 |
|
|
waddr_av <= cnt_1 ;
|
| 432 |
|
|
we_av <= '1' ;
|
| 433 |
|
|
state_next <= SCAN_1 ;
|
| 434 |
|
|
ELSE
|
| 435 |
|
|
state_next <= SCAN_1 ;
|
| 436 |
|
|
END IF;
|
| 437 |
|
|
|
| 438 |
|
|
WHEN OTHERS=>
|
| 439 |
|
|
state_next <= IDLE ;
|
| 440 |
|
|
END CASE;
|
| 441 |
|
|
END PROCESS;
|
| 442 |
|
|
|
| 443 |
|
|
-- vd_add_rm_out <= vd_add_rm ;
|
| 444 |
|
|
-- vd_rm_out <=time_out_cmd_rd;
|
| 445 |
|
|
-- vd_rm_out <=vd_rm;
|
| 446 |
|
|
process (clk)
|
| 447 |
|
|
variable cnt1 : integer range 0 to 2**ADDR_WIDTH-1;
|
| 448 |
|
|
begin
|
| 449 |
|
|
if (rising_edge(clk)) then
|
| 450 |
|
|
|
| 451 |
|
|
if reset = '1' then
|
| 452 |
|
|
cnt1 := 0;
|
| 453 |
|
|
elsIF(cnt_1_restart = '1' ) THEN
|
| 454 |
|
|
cnt1 := 0;
|
| 455 |
|
|
elsif cnt_1_up = '1' then
|
| 456 |
|
|
cnt1 := cnt1 + 1;
|
| 457 |
|
|
end if;
|
| 458 |
|
|
end if;
|
| 459 |
|
|
cnt_1 <= std_logic_vector(to_unsigned(cnt1 , ADDR_WIDTH));
|
| 460 |
|
|
end process;
|
| 461 |
|
|
|
| 462 |
|
|
|
| 463 |
|
|
|
| 464 |
|
|
|
| 465 |
|
|
end Behavioral;
|
| 466 |
|
|
|
