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[/] [loadbalancer/] [trunk/] [TABLE/] [mac_ram_table.vhd.bak] - Blame information for rev 2

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library IEEE;
2
use IEEE.STD_LOGIC_1164.ALL;
3
use IEEE.STD_LOGIC_ARITH.ALL;
4
use IEEE.STD_LOGIC_UNSIGNED.ALL;
5
use ieee.numeric_std.all;
6
USE IEEE.STD_LOGIC_MISC.ALL;
7
USE WORK.CONFIG.ALL;
8
entity mac_ram_table is
9
generic (
10
        ADDR_WIDTH :integer := 12
11
    );
12
        port (
13
        clk: IN std_logic;
14
        reset : IN STD_LOGIC;
15
        in_mac_no_prt: IN std_logic_VECTOR(63 downto 0);--MAC NUMBER internal port
16
        in_address   : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
17
        in_wr: IN std_logic;
18
        in_check : IN STD_LOGIC;
19
        match_address : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
20
        match:  OUT STD_LOGIC;
21
        unmatch:  OUT STD_LOGIC;
22
        in_rd : IN STD_LOGIC;
23
        in_key : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
24
        last_address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
25
        out_rd_rdy : OUT std_logic;
26
--      vd_add_rm_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
27
--      vd_rm_out :  OUT STD_LOGIC;
28
        out_port : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
29
    out_mac : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
30
        );
31
end mac_ram_table;
32
 
33
architecture Behavioral of mac_ram_table is
34
 
35
        ----------------------------------------------------------------
36
        COMPONENT valid_address is
37
                generic (
38
                                ADDR_WIDTH :integer := ADDR_WIDTH
39
                        );
40
                        port (
41
                                        clk: IN std_logic;
42
                                        reset : IN STD_LOGIC;
43
                                        in_wr_address : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
44
                                        in_wr: IN std_logic;
45
                                        in_key : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
46
                                        in_rd : IN STD_LOGIC;
47
                                        in_rm_address_no : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
48
                                        in_rm : IN STD_LOGIC;
49
                                        out_address : OUT STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
50
                                        out_rdy : OUT std_logic
51
 
52
                        );
53
        end COMPONENT valid_address;
54
        ------------------------
55
        COMPONENT Aging_Timer is
56
           generic(
57
                  N: integer := 32;  -- 32 bits couter
58
                  M: integer := 125000  -- 125000  = 1 miliscond
59
           );
60
           port(
61
                  clk, reset: in std_logic;
62
                  timeout: out std_logic;
63
                  timer_aging_bit: out std_logic;
64
                  count_out: out std_logic_vector(31 downto 0)--N-1
65
           );
66
        end COMPONENT Aging_Timer;
67
 
68
 
69
----------------------------------------------------------------------------
70
        -------COMPONENET SMALL FIFO
71
        COMPONENT  small_fifo IS
72
        GENERIC(WIDTH :INTEGER := 8;
73
                        MAX_DEPTH_BITS :INTEGER := 5);
74
         PORT(
75
     SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--input [WIDTH-1:0] din,     // Data in
76
     SIGNAL wr_en : IN STD_LOGIC;--input          wr_en,   // Write enable
77
     SIGNAL rd_en : IN STD_LOGIC;--input          rd_en,   // Read the next word
78
     SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);--output reg [WIDTH-1:0]  dout,    // Data out
79
     SIGNAL full : OUT STD_LOGIC;--output         full,
80
     SIGNAL nearly_full : OUT STD_LOGIC;--output         nearly_full,
81
     SIGNAL empty : OUT STD_LOGIC;--output         empty,
82
     SIGNAL reset :IN STD_LOGIC;
83
     SIGNAL clk   :IN STD_LOGIC
84
         );
85
        END COMPONENT;
86
-------COMPONENET SMALL FIFO
87
------------------------------------------------------
88
 
89
------------------------------------------------------------
90
COMPONENT ram_256x48 is
91
 
92
        generic
93
        (
94
                DATA_WIDTH : natural := 48;
95
                ADDR_WIDTH : natural := ADDR_WIDTH
96
        );
97
 
98
        port
99
        (
100
                clk             : in std_logic;
101
                raddr   : in natural range 0 to 2**ADDR_WIDTH - 1;
102
                waddr   : in natural range 0 to 2**ADDR_WIDTH - 1;
103
                data    : in std_logic_vector((DATA_WIDTH-1) downto 0);
104
                we              : in std_logic := '1';
105
                q               : out std_logic_vector((DATA_WIDTH -1) downto 0)
106
        );
107
 
108
end COMPONENT ram_256x48;
109
        TYPE            state_type                              IS(IDLE, ADD_1, ADD_2, SCAN_1, SCAN_2);
110
        SIGNAL          state, state_next        :      state_type;
111
        TYPE            state_search_type               IS(IDLE,  CHECK, FOUND, UNFOUND);
112
        SIGNAL          state_search             :  state_search_type;
113
        SIGNAL          state_next_search        :  state_search_type;
114
        attribute       enum_encoding            :  string;
115
        attribute       enum_encoding of state_type : type is "onehot";
116
        ------------------------------------------------------
117
        SIGNAL          in_mac_no_prt_i         :  STD_LOGIC_VECTOR(55 DOWNTO 0);
118
        SIGNAL          mac_prt                         :  STD_LOGIC_VECTOR(55 DOWNTO 0);
119
        SIGNAL          q_mac_prt                       :  STD_LOGIC_VECTOR(55 DOWNTO 0);
120
        SIGNAL          cnt                             :  INTEGER ;
121
        SIGNAL          in_check_p                      :  STD_LOGIC;
122
        SIGNAL          match_i                         :  STD_LOGIC;
123
        SIGNAL          unmatch_i                               :  STD_LOGIC;
124
        ---------------------------------------------------------------------------
125
        SIGNAL          time_out                        :  STD_LOGIC;
126
        SIGNAL          timer_aging_bit         :  STD_LOGIC;
127
        ---------------------------------------------------------------------------
128
        --------- Signals to connect with Valid Address Module-------------
129
        SIGNAL          vd_add                          :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
130
        SIGNAL          vd_add_wr                       :  STD_LOGIC;
131
        SIGNAL          vd_in_rd                        :  STD_LOGIC;
132
        SIGNAL          vd_add_rm                       :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
133
        SIGNAL          vd_rm                           :  STD_LOGIC;
134
        SIGNAL          vd_out_add              :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
135
        SIGNAL          vd_out_rdy                      :  STD_LOGIC;
136
        SIGNAL          out_rd_rdy_i            :  STD_LOGIC;
137
        ---------------------------------------------------------------------------
138
        --------- Signals to connect with Fifo Module---------------------
139
        SIGNAL          write_cmd_rd            :  STD_LOGIC;
140
        SIGNAL          write_cmd_address       :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
141
        SIGNAL          write_cmd_empty         :  STD_LOGIC;
142
        SIGNAL          time_out_cmd_rd         :  STD_LOGIC;
143
        SIGNAL          time_out_cmd_empty      :  STD_LOGIC;
144
        SIGNAL          time_out_fifo_wr        :  STD_LOGIC;
145
        ---------------------------------------------------------------------------
146
        --------- Signals to connect with VALID AGING Ram ----------------
147
        SIGNAL          raddr_av                        :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
148
        SIGNAL          waddr_av                        :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
149
        SIGNAL          data_av                         :  STD_LOGIC_VECTOR(1 DOWNTO 0);
150
        SIGNAL          we_av                           :  STD_LOGIC;
151
        SIGNAL          ag_vd_q                         :  STD_LOGIC_VECTOR(1 DOWNTO 0);
152
        ---------------------------------------------------------------------------
153
        --------- Signals to connect with MAC reading Ram ----------------
154
        SIGNAL          ram_mac_out             :  STD_LOGIC_VECTOR(47 DOWNTO 0);
155
        -------------------------------------------------
156
        --------- Signals to connect with MAC Searching Ram ----------------
157
        SIGNAL          ram_q                           :  STD_LOGIC_VECTOR(55 DOWNTO 0);
158
        ---------------------------------------------------------------------------
159
        SIGNAL          cnt_1                           :  STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
160
        SIGNAL          cnt_1_restart           :  STD_LOGIC;
161
        SIGNAL          cnt_1_up                        :  STD_LOGIC;
162
        ---------------------------------------------------------------------------
163
begin
164
        ---------------------------------------------------------------------------
165
 
166
        -------PORT MAP SMALL FIFO DATA
167
                ------------------------
168
                        Aging_Timer_Inst :  Aging_Timer
169
                           GENERIC MAP (
170
                                                                N => 32 ,
171
                                                                M => 1025000 -- = 1 --miliscond
172
                                                        )
173
                                   port MAP(
174
                                          clk => clk,
175
                                          reset => reset,
176
                                          timeout =>open ,
177
                                          timer_aging_bit =>timer_aging_bit,
178
                                          count_out => open
179
                                   );
180
 
181
                                        time_out<='0';--testing without aging bit
182
--Search  new MAC inside the table the address
183
                ram_256x48_search_Inst : ram_256x48
184
 
185
                        GENERIC MAP     (
186
                                        DATA_WIDTH => 56, ADDR_WIDTH => ADDR_WIDTH)
187
 
188
                                port MAP (
189
                                        clk                     =>       clk            ,
190
                                        raddr       =>    CONV_INTEGER(cnt)                     ,
191
                                        waddr       =>    CONV_INTEGER(in_address)                      ,
192
                                        data        =>    in_mac_no_prt(63 DOWNTO 8)            ,
193
                                        we                  =>   in_wr          ,
194
                                        q                   =>   ram_q
195
                                );
196
 
197
-----------------------------------------------------------------------
198
 
199
                PROCESS(clk, reset)
200
                                BEGIN
201
                                        IF reset= '1' THEN
202
                                                                state_search    <=        IDLE    ;
203
                                        ELSIF clk'EVENT AND clk = '1' THEN
204
                                                                state_search            <=        state_next_search       ;
205
                                                IF(in_check = '1') THEN
206
                                                                in_mac_no_prt_i <= in_mac_no_prt(63 DOWNTO 8);
207
 
208
                                                END IF;
209
                                                IF(match_i = '1') THEN
210
                                                                match_address           <= std_logic_vector(to_unsigned(cnt - 1, ADDR_WIDTH));
211
 
212
                                                END IF;
213
                                        END IF;
214
        END PROCESS;
215
 
216
        PROCESS(state_search, in_check, ram_q, in_mac_no_prt_i, cnt, last_address)
217
                BEGIN
218
                                                                state_next_search       <=        state_search    ;
219
                                                                match_i                         <=  '0'        ;
220
                                                                unmatch_i                       <=  '0'        ;
221
 
222
                CASE state_search IS
223
                WHEN IDLE =>
224
                                        IF(in_check = '1' ) THEN
225
                                                                state_next_search       <= CHECK        ;
226
                                        END IF;
227
                WHEN CHECK =>
228
                                        IF (ram_q = in_mac_no_prt_i )THEN
229
                                                                match_i                         <=  '1'        ;
230
                                                                state_next_search       <=        IDLE    ;
231
                                        ELSIF (cnt = CONV_INTEGER(last_address))        THEN
232
                                                                unmatch_i <=  '1';
233
                                                                state_next_search       <=        IDLE    ;
234
                                        END IF;
235
 
236
                WHEN OTHERS=>
237
                                                                state_next_search       <=        IDLE    ;
238
 
239
                END CASE;
240
        END PROCESS;
241
 
242
---------Register Out put--------------
243
        process (clk)
244
        begin
245
                if (rising_edge(clk)) then
246
                        match   <= match_i;
247
                        unmatch <= unmatch_i;
248
                end if;
249
        end process;
250
 
251
-----------------------------------------
252
 
253
        process (clk)
254
                variable   cnt1            : integer range 0 to 2**ADDR_WIDTH-1;
255
        begin
256
                if (rising_edge(clk)) then
257
 
258
                        if reset = '1' then
259
                                cnt1 := 0;
260
                        elsIF(in_check = '1'  ) THEN
261
                                        cnt1 := 0;
262
                        else
263
                                cnt1 := cnt1 + 1;
264
                        end if;
265
                end if;
266
                cnt <= cnt1;
267
        end process;
268
 
269
 -------------------------------------------------------------------
270
 -------------------------------------------------------------------
271
 -------------------------------------------------------------------
272
--Write new MAC inside the table the address is provided by out side
273
                ram_256x48_Inst : ram_256x48
274
 
275
                        GENERIC MAP     (
276
                                        DATA_WIDTH => 56, ADDR_WIDTH => ADDR_WIDTH)
277
 
278
                                port MAP (
279
                                        clk                                 =>   clk            ,
280
                                        raddr                       =>  CONV_INTEGER(vd_out_add)                ,--this is coming from the valid address
281
                                        waddr               =>   CONV_INTEGER(in_address)               ,
282
                                        data                =>   mac_prt                ,--MAC=>PORT
283
                                        we                          =>   in_wr  ,
284
                                        q                           =>   q_mac_prt --Next MAC address
285
                                );
286
                                mac_prt(55 DOWNTO 8) <= in_mac_no_prt(63 DOWNTO 16);
287
                                mac_prt(7 DOWNTO 0) <= in_mac_no_prt(7 DOWNTO 0);
288
                                out_mac                         <=q_mac_prt(55 DOWNTO 8);
289
                                out_port                        <=q_mac_prt(7 DOWNTO 0);
290
        WRITE_command_Inst :  small_fifo
291
                GENERIC MAP(WIDTH  => ADDR_WIDTH,
292
                                MAX_DEPTH_BITS  => 5)
293
                PORT MAP(
294
                                   din                                  =>      in_address,
295
                                   wr_en                                =>      in_wr,
296
                                   rd_en                                =>      write_cmd_rd,
297
                                   dout                                 =>      write_cmd_address,
298
                                   full                                 =>      open,
299
                                   nearly_full                  =>      open,
300
                                   empty                                =>      write_cmd_empty,
301
                                   reset                                =>      reset ,
302
                                   clk                                  =>      clk
303
                );
304
        time_command_Inst :  small_fifo
305
                GENERIC MAP(WIDTH  => 1,
306
                                MAX_DEPTH_BITS  => 2)
307
                PORT MAP(
308
                                   din                                  =>      "1",
309
                                   wr_en                                =>      time_out_fifo_wr,
310
                                   rd_en                                =>      time_out_cmd_rd,
311
                                   dout                                 =>      open,
312
                                   full                                 =>      open,
313
                                   nearly_full                  =>      open,
314
                                   empty                                =>      time_out_cmd_empty,
315
                                   reset                                =>      reset ,
316
                                   clk                                  =>      clk
317
                );
318
                time_out_fifo_wr <= time_out AND  (time_out_cmd_empty);--onòy one element can be sotred in this
319
-------------------------------------------------------------------
320
------------------------------------------------------------
321
        --Write new MAC inside the table the address is provided by out side
322
                Aging_Valid_256x48_Inst : ram_256x48
323
 
324
                        GENERIC MAP     (
325
                                        DATA_WIDTH => 2, ADDR_WIDTH => ADDR_WIDTH)
326
 
327
                                port MAP (
328
                                        clk                                     =>       clk            ,
329
                                        raddr                           =>       CONV_INTEGER(raddr_av)         ,
330
                                        waddr                   =>       CONV_INTEGER(waddr_av)         ,
331
                                        data                    =>       data_av        ,
332
                                        we                              =>       we_av          ,
333
                                        q                               =>       ag_vd_q
334
                                );
335
-------------------------------------------------------------------------------------
336
        valid_address_Inst : valid_address
337
                GENERIC MAP (ADDR_WIDTH =>ADDR_WIDTH)
338
                PORT MAP    (
339
                                        clk                                     =>       clk            ,
340
                                        reset                           =>       reset          ,
341
                                        in_wr_address           =>       vd_add         ,
342
                                        in_wr                           =>       vd_add_wr      ,
343
                                        in_rd                           =>       in_rd  ,
344
                                        in_key                          =>       in_key ,
345
                                        in_rm_address_no        =>       vd_add_rm      ,
346
                                        in_rm                           =>       vd_rm          ,
347
                                        out_address             =>   vd_out_add ,
348
                                        out_rdy                         =>   vd_out_rdy
349
 
350
                        );
351
 
352
-------------------------------------------------------------------------------------
353
                PROCESS(clk, reset)
354
                                BEGIN
355
                                IF reset= '1' THEN
356
                                        state                           <=        IDLE    ;
357
                                ELSIF clk'EVENT AND clk = '1' THEN
358
                                        state                           <=        state_next      ;
359
                                        out_rd_rdy_i                <=  vd_out_rdy;
360
                                        out_rd_rdy                  <=  out_rd_rdy_i ;
361
                                END IF;
362
                END PROCESS;
363
 
364
                PROCESS(state, write_cmd_empty, time_out_cmd_empty,
365
                                write_cmd_address, timer_aging_bit, write_cmd_address, ag_vd_q, cnt_1)
366
                BEGIN
367
                                        vd_add_rm                   <=  (OTHERS=>'0');
368
                                        vd_rm                       <=  '0';
369
                                        vd_add                      <=  (OTHERS=>'0');
370
                                        vd_add_wr                   <=  '0';
371
                                        raddr_av                    <=	(OTHERS=>'0');
372
                                        waddr_av                    <=	(OTHERS=>'0');
373
                                        data_av                     <=	(OTHERS=>'0');
374
                                        we_av                       <=  '0';
375
                                        write_cmd_rd        <=  '0';
376
                                        time_out_cmd_rd         <=  '0';
377
                                        cnt_1_restart           <=  '0';
378
                                        cnt_1_up                        <=  '0';
379
                                        state_next                  <=  state   ;
380
 
381
 
382
                CASE state IS
383
 
384
                WHEN IDLE =>
385
                                                        cnt_1_restart   <= '1';
386
                                        IF write_cmd_empty = '0' THEN
387
                                                        write_cmd_rd<=  '1';
388
                                                        state_next      <=  ADD_1        ;
389
                                        ELSIF(time_out_cmd_empty = '0' ) THEN
390
 
391
                                                        time_out_cmd_rd         <=  '1';
392
                                                        state_next      <=  SCAN_1        ;
393
                                        END IF;
394
                WHEN ADD_1 =>
395
                                                        ---Read the Valid and  Aging bit
396
                                                        raddr_av        <=        write_cmd_address       ;
397
                                                        state_next      <=        ADD_2   ;
398
                WHEN ADD_2 =>
399
                                                        ---Write the Valid and  Aging bit
400
                                                        data_av         <=         '1' & timer_aging_bit ;
401
                                                        waddr_av        <=        write_cmd_address       ;
402
                                                        we_av           <=        '1'     ;
403
                                                        --Write the Valid Address
404
                                                        vd_add          <=  write_cmd_address        ;
405
                                                        vd_add_wr       <=  NOT ag_vd_q(1)        ;
406
                                                        state_next      <=        IDLE    ;
407
                WHEN SCAN_1 =>
408
 
409
                                                        raddr_av        <=        cnt_1 ;
410
                                                        state_next      <=        SCAN_2  ;
411
 
412
                WHEN SCAN_2 =>          cnt_1_up        <= '1';
413
 
414
                --              ELSIF cnt_1 = CONV_INTEGER(last_address)THEN            --LAST ELEMNET REACHED
415
                IF cnt_1 = CONV_INTEGER(last_address) THEN              --LAST ELEMNET REACHED
416
                                                        state_next      <=        IDLE    ;
417
 
418
                ELSIF ( ag_vd_q(1) = '1' AND ( ag_vd_q(0) /= timer_aging_bit )  )THEN
419
--                                                      data_av(1)      <=        '1';
420
--                                                      data_av(0)      <=        ag_vd_q(0); --do not change it
421
--                                                      we_av           <=        '1'     ;
422
                                                        state_next      <=        SCAN_1  ;
423
 
424
            ELSIF ( ag_vd_q(1)  = '1' AND ( ag_vd_q(0) = timer_aging_bit ) )THEN
425
                                                        ---delete this valid address
426
                                                        vd_add_rm       <=  cnt_1 ;
427
                                                        vd_rm           <=  '1';
428
                                                        -----------------------------
429
                                                        data_av(1)      <=        '0';
430
                                                        data_av(0)      <=        timer_aging_bit;
431
                                                        waddr_av        <=        cnt_1 ;
432
                                                        we_av           <=        '1'     ;
433
                                                        state_next      <=        SCAN_1  ;
434
                ELSE
435
                                                        state_next      <=        SCAN_1  ;
436
                                                        END IF;
437
 
438
                WHEN OTHERS=>
439
                                                        state_next      <=        IDLE    ;
440
                END CASE;
441
        END PROCESS;
442
 
443
--      vd_add_rm_out <= vd_add_rm       ;
444
--      vd_rm_out <=time_out_cmd_rd;
445
--      vd_rm_out <=vd_rm;
446
        process (clk)
447
                variable   cnt1            : integer range 0 to 2**ADDR_WIDTH-1;
448
        begin
449
                if (rising_edge(clk)) then
450
 
451
                        if reset = '1' then
452
                                cnt1 := 0;
453
                        elsIF(cnt_1_restart = '1'  ) THEN
454
                                        cnt1 := 0;
455
                        elsif cnt_1_up = '1' then
456
                                cnt1 := cnt1 + 1;
457
                        end if;
458
                end if;
459
                cnt_1 <= std_logic_vector(to_unsigned(cnt1 , ADDR_WIDTH));
460
        end process;
461
 
462
 
463
 
464
 
465
end Behavioral;
466
 

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