1 |
2 |
atalla |
|LB
|
2 |
|
|
in_rdy <= manager:inst.in_rdy
|
3 |
|
|
in_wr => manager:inst.in_wr
|
4 |
|
|
in_rd => manager:inst.in_rd
|
5 |
|
|
out_rdy => manager:inst.out_rdy
|
6 |
|
|
reset => manager:inst.reset
|
7 |
|
|
clk => manager:inst.clk
|
8 |
|
|
in_ctrl[0] => manager:inst.in_ctrl[0]
|
9 |
|
|
in_ctrl[1] => manager:inst.in_ctrl[1]
|
10 |
|
|
in_ctrl[2] => manager:inst.in_ctrl[2]
|
11 |
|
|
in_ctrl[3] => manager:inst.in_ctrl[3]
|
12 |
|
|
in_ctrl[4] => manager:inst.in_ctrl[4]
|
13 |
|
|
in_ctrl[5] => manager:inst.in_ctrl[5]
|
14 |
|
|
in_ctrl[6] => manager:inst.in_ctrl[6]
|
15 |
|
|
in_ctrl[7] => manager:inst.in_ctrl[7]
|
16 |
|
|
in_data[0] => manager:inst.in_data[0]
|
17 |
|
|
in_data[1] => manager:inst.in_data[1]
|
18 |
|
|
in_data[2] => manager:inst.in_data[2]
|
19 |
|
|
in_data[3] => manager:inst.in_data[3]
|
20 |
|
|
in_data[4] => manager:inst.in_data[4]
|
21 |
|
|
in_data[5] => manager:inst.in_data[5]
|
22 |
|
|
in_data[6] => manager:inst.in_data[6]
|
23 |
|
|
in_data[7] => manager:inst.in_data[7]
|
24 |
|
|
in_data[8] => manager:inst.in_data[8]
|
25 |
|
|
in_data[9] => manager:inst.in_data[9]
|
26 |
|
|
in_data[10] => manager:inst.in_data[10]
|
27 |
|
|
in_data[11] => manager:inst.in_data[11]
|
28 |
|
|
in_data[12] => manager:inst.in_data[12]
|
29 |
|
|
in_data[13] => manager:inst.in_data[13]
|
30 |
|
|
in_data[14] => manager:inst.in_data[14]
|
31 |
|
|
in_data[15] => manager:inst.in_data[15]
|
32 |
|
|
in_data[16] => manager:inst.in_data[16]
|
33 |
|
|
in_data[17] => manager:inst.in_data[17]
|
34 |
|
|
in_data[18] => manager:inst.in_data[18]
|
35 |
|
|
in_data[19] => manager:inst.in_data[19]
|
36 |
|
|
in_data[20] => manager:inst.in_data[20]
|
37 |
|
|
in_data[21] => manager:inst.in_data[21]
|
38 |
|
|
in_data[22] => manager:inst.in_data[22]
|
39 |
|
|
in_data[23] => manager:inst.in_data[23]
|
40 |
|
|
in_data[24] => manager:inst.in_data[24]
|
41 |
|
|
in_data[25] => manager:inst.in_data[25]
|
42 |
|
|
in_data[26] => manager:inst.in_data[26]
|
43 |
|
|
in_data[27] => manager:inst.in_data[27]
|
44 |
|
|
in_data[28] => manager:inst.in_data[28]
|
45 |
|
|
in_data[29] => manager:inst.in_data[29]
|
46 |
|
|
in_data[30] => manager:inst.in_data[30]
|
47 |
|
|
in_data[31] => manager:inst.in_data[31]
|
48 |
|
|
in_data[32] => manager:inst.in_data[32]
|
49 |
|
|
in_data[33] => manager:inst.in_data[33]
|
50 |
|
|
in_data[34] => manager:inst.in_data[34]
|
51 |
|
|
in_data[35] => manager:inst.in_data[35]
|
52 |
|
|
in_data[36] => manager:inst.in_data[36]
|
53 |
|
|
in_data[37] => manager:inst.in_data[37]
|
54 |
|
|
in_data[38] => manager:inst.in_data[38]
|
55 |
|
|
in_data[39] => manager:inst.in_data[39]
|
56 |
|
|
in_data[40] => manager:inst.in_data[40]
|
57 |
|
|
in_data[41] => manager:inst.in_data[41]
|
58 |
|
|
in_data[42] => manager:inst.in_data[42]
|
59 |
|
|
in_data[43] => manager:inst.in_data[43]
|
60 |
|
|
in_data[44] => manager:inst.in_data[44]
|
61 |
|
|
in_data[45] => manager:inst.in_data[45]
|
62 |
|
|
in_data[46] => manager:inst.in_data[46]
|
63 |
|
|
in_data[47] => manager:inst.in_data[47]
|
64 |
|
|
in_data[48] => manager:inst.in_data[48]
|
65 |
|
|
in_data[49] => manager:inst.in_data[49]
|
66 |
|
|
in_data[50] => manager:inst.in_data[50]
|
67 |
|
|
in_data[51] => manager:inst.in_data[51]
|
68 |
|
|
in_data[52] => manager:inst.in_data[52]
|
69 |
|
|
in_data[53] => manager:inst.in_data[53]
|
70 |
|
|
in_data[54] => manager:inst.in_data[54]
|
71 |
|
|
in_data[55] => manager:inst.in_data[55]
|
72 |
|
|
in_data[56] => manager:inst.in_data[56]
|
73 |
|
|
in_data[57] => manager:inst.in_data[57]
|
74 |
|
|
in_data[58] => manager:inst.in_data[58]
|
75 |
|
|
in_data[59] => manager:inst.in_data[59]
|
76 |
|
|
in_data[60] => manager:inst.in_data[60]
|
77 |
|
|
in_data[61] => manager:inst.in_data[61]
|
78 |
|
|
in_data[62] => manager:inst.in_data[62]
|
79 |
|
|
in_data[63] => manager:inst.in_data[63]
|
80 |
|
|
in_key[0] => manager:inst.in_key[0]
|
81 |
|
|
in_key[1] => manager:inst.in_key[1]
|
82 |
|
|
in_key[2] => manager:inst.in_key[2]
|
83 |
|
|
in_key[3] => manager:inst.in_key[3]
|
84 |
|
|
in_key[4] => manager:inst.in_key[4]
|
85 |
|
|
in_key[5] => manager:inst.in_key[5]
|
86 |
|
|
in_key[6] => manager:inst.in_key[6]
|
87 |
|
|
in_key[7] => manager:inst.in_key[7]
|
88 |
|
|
in_key[8] => manager:inst.in_key[8]
|
89 |
|
|
in_key[9] => manager:inst.in_key[9]
|
90 |
|
|
out_rd_rdy <= manager:inst.out_rd_rdy
|
91 |
|
|
out_mac[0] <= manager:inst.out_mac[0]
|
92 |
|
|
out_mac[1] <= manager:inst.out_mac[1]
|
93 |
|
|
out_mac[2] <= manager:inst.out_mac[2]
|
94 |
|
|
out_mac[3] <= manager:inst.out_mac[3]
|
95 |
|
|
out_mac[4] <= manager:inst.out_mac[4]
|
96 |
|
|
out_mac[5] <= manager:inst.out_mac[5]
|
97 |
|
|
out_mac[6] <= manager:inst.out_mac[6]
|
98 |
|
|
out_mac[7] <= manager:inst.out_mac[7]
|
99 |
|
|
out_mac[8] <= manager:inst.out_mac[8]
|
100 |
|
|
out_mac[9] <= manager:inst.out_mac[9]
|
101 |
|
|
out_mac[10] <= manager:inst.out_mac[10]
|
102 |
|
|
out_mac[11] <= manager:inst.out_mac[11]
|
103 |
|
|
out_mac[12] <= manager:inst.out_mac[12]
|
104 |
|
|
out_mac[13] <= manager:inst.out_mac[13]
|
105 |
|
|
out_mac[14] <= manager:inst.out_mac[14]
|
106 |
|
|
out_mac[15] <= manager:inst.out_mac[15]
|
107 |
|
|
out_mac[16] <= manager:inst.out_mac[16]
|
108 |
|
|
out_mac[17] <= manager:inst.out_mac[17]
|
109 |
|
|
out_mac[18] <= manager:inst.out_mac[18]
|
110 |
|
|
out_mac[19] <= manager:inst.out_mac[19]
|
111 |
|
|
out_mac[20] <= manager:inst.out_mac[20]
|
112 |
|
|
out_mac[21] <= manager:inst.out_mac[21]
|
113 |
|
|
out_mac[22] <= manager:inst.out_mac[22]
|
114 |
|
|
out_mac[23] <= manager:inst.out_mac[23]
|
115 |
|
|
out_mac[24] <= manager:inst.out_mac[24]
|
116 |
|
|
out_mac[25] <= manager:inst.out_mac[25]
|
117 |
|
|
out_mac[26] <= manager:inst.out_mac[26]
|
118 |
|
|
out_mac[27] <= manager:inst.out_mac[27]
|
119 |
|
|
out_mac[28] <= manager:inst.out_mac[28]
|
120 |
|
|
out_mac[29] <= manager:inst.out_mac[29]
|
121 |
|
|
out_mac[30] <= manager:inst.out_mac[30]
|
122 |
|
|
out_mac[31] <= manager:inst.out_mac[31]
|
123 |
|
|
out_mac[32] <= manager:inst.out_mac[32]
|
124 |
|
|
out_mac[33] <= manager:inst.out_mac[33]
|
125 |
|
|
out_mac[34] <= manager:inst.out_mac[34]
|
126 |
|
|
out_mac[35] <= manager:inst.out_mac[35]
|
127 |
|
|
out_mac[36] <= manager:inst.out_mac[36]
|
128 |
|
|
out_mac[37] <= manager:inst.out_mac[37]
|
129 |
|
|
out_mac[38] <= manager:inst.out_mac[38]
|
130 |
|
|
out_mac[39] <= manager:inst.out_mac[39]
|
131 |
|
|
out_mac[40] <= manager:inst.out_mac[40]
|
132 |
|
|
out_mac[41] <= manager:inst.out_mac[41]
|
133 |
|
|
out_mac[42] <= manager:inst.out_mac[42]
|
134 |
|
|
out_mac[43] <= manager:inst.out_mac[43]
|
135 |
|
|
out_mac[44] <= manager:inst.out_mac[44]
|
136 |
|
|
out_mac[45] <= manager:inst.out_mac[45]
|
137 |
|
|
out_mac[46] <= manager:inst.out_mac[46]
|
138 |
|
|
out_mac[47] <= manager:inst.out_mac[47]
|
139 |
|
|
out_port[0] <= manager:inst.out_port[0]
|
140 |
|
|
out_port[1] <= manager:inst.out_port[1]
|
141 |
|
|
out_port[2] <= manager:inst.out_port[2]
|
142 |
|
|
out_port[3] <= manager:inst.out_port[3]
|
143 |
|
|
out_port[4] <= manager:inst.out_port[4]
|
144 |
|
|
out_port[5] <= manager:inst.out_port[5]
|
145 |
|
|
out_port[6] <= manager:inst.out_port[6]
|
146 |
|
|
out_port[7] <= manager:inst.out_port[7]
|
147 |
|
|
|
148 |
|
|
|
149 |
|
|
|LB|manager:inst
|
150 |
|
|
in_data[0] => mac_exit_port[0].DATAIN
|
151 |
|
|
in_data[1] => mac_exit_port[1].DATAIN
|
152 |
|
|
in_data[2] => mac_exit_port[2].DATAIN
|
153 |
|
|
in_data[3] => mac_exit_port[3].DATAIN
|
154 |
|
|
in_data[4] => mac_exit_port[4].DATAIN
|
155 |
|
|
in_data[5] => mac_exit_port[5].DATAIN
|
156 |
|
|
in_data[6] => mac_exit_port[6].DATAIN
|
157 |
|
|
in_data[7] => mac_exit_port[7].DATAIN
|
158 |
|
|
in_data[8] => mac_weight[0].DATAIN
|
159 |
|
|
in_data[9] => mac_weight[1].DATAIN
|
160 |
|
|
in_data[10] => mac_weight[2].DATAIN
|
161 |
|
|
in_data[11] => mac_weight[3].DATAIN
|
162 |
|
|
in_data[12] => mac_weight[4].DATAIN
|
163 |
|
|
in_data[13] => mac_weight[5].DATAIN
|
164 |
|
|
in_data[14] => mac_weight[6].DATAIN
|
165 |
|
|
in_data[15] => mac_weight[7].DATAIN
|
166 |
|
|
in_data[16] => mac[0].DATAIN
|
167 |
|
|
in_data[17] => mac[1].DATAIN
|
168 |
|
|
in_data[18] => mac[2].DATAIN
|
169 |
|
|
in_data[19] => mac[3].DATAIN
|
170 |
|
|
in_data[20] => mac[4].DATAIN
|
171 |
|
|
in_data[21] => mac[5].DATAIN
|
172 |
|
|
in_data[22] => mac[6].DATAIN
|
173 |
|
|
in_data[23] => mac[7].DATAIN
|
174 |
|
|
in_data[24] => mac_cnt~31.DATAB
|
175 |
|
|
in_data[24] => mac[8].DATAIN
|
176 |
|
|
in_data[25] => mac_cnt~30.DATAB
|
177 |
|
|
in_data[25] => mac[9].DATAIN
|
178 |
|
|
in_data[26] => mac_cnt~29.DATAB
|
179 |
|
|
in_data[26] => mac[10].DATAIN
|
180 |
|
|
in_data[27] => mac_cnt~28.DATAB
|
181 |
|
|
in_data[27] => mac[11].DATAIN
|
182 |
|
|
in_data[28] => mac_cnt~27.DATAB
|
183 |
|
|
in_data[28] => mac[12].DATAIN
|
184 |
|
|
in_data[29] => mac_cnt~26.DATAB
|
185 |
|
|
in_data[29] => mac[13].DATAIN
|
186 |
|
|
in_data[30] => mac_cnt~25.DATAB
|
187 |
|
|
in_data[30] => mac[14].DATAIN
|
188 |
|
|
in_data[31] => mac_cnt~24.DATAB
|
189 |
|
|
in_data[31] => mac[15].DATAIN
|
190 |
|
|
in_data[32] => mac[16].DATAIN
|
191 |
|
|
in_data[33] => mac[17].DATAIN
|
192 |
|
|
in_data[34] => mac[18].DATAIN
|
193 |
|
|
in_data[35] => mac[19].DATAIN
|
194 |
|
|
in_data[36] => mac[20].DATAIN
|
195 |
|
|
in_data[37] => mac[21].DATAIN
|
196 |
|
|
in_data[38] => mac[22].DATAIN
|
197 |
|
|
in_data[39] => mac[23].DATAIN
|
198 |
|
|
in_data[40] => mac[24].DATAIN
|
199 |
|
|
in_data[41] => mac[25].DATAIN
|
200 |
|
|
in_data[42] => mac[26].DATAIN
|
201 |
|
|
in_data[43] => mac[27].DATAIN
|
202 |
|
|
in_data[44] => mac[28].DATAIN
|
203 |
|
|
in_data[45] => mac[29].DATAIN
|
204 |
|
|
in_data[46] => mac[30].DATAIN
|
205 |
|
|
in_data[47] => mac[31].DATAIN
|
206 |
|
|
in_data[48] => mac[32].DATAIN
|
207 |
|
|
in_data[49] => mac[33].DATAIN
|
208 |
|
|
in_data[50] => mac[34].DATAIN
|
209 |
|
|
in_data[51] => mac[35].DATAIN
|
210 |
|
|
in_data[52] => mac[36].DATAIN
|
211 |
|
|
in_data[53] => mac[37].DATAIN
|
212 |
|
|
in_data[54] => mac[38].DATAIN
|
213 |
|
|
in_data[55] => mac[39].DATAIN
|
214 |
|
|
in_data[56] => mac[40].DATAIN
|
215 |
|
|
in_data[57] => mac[41].DATAIN
|
216 |
|
|
in_data[58] => mac[42].DATAIN
|
217 |
|
|
in_data[59] => mac[43].DATAIN
|
218 |
|
|
in_data[60] => mac[44].DATAIN
|
219 |
|
|
in_data[61] => mac[45].DATAIN
|
220 |
|
|
in_data[62] => mac[46].DATAIN
|
221 |
|
|
in_data[63] => mac[47].DATAIN
|
222 |
|
|
in_ctrl[0] => Equal1.IN15
|
223 |
|
|
in_ctrl[0] => Equal0.IN15
|
224 |
|
|
in_ctrl[1] => Equal1.IN14
|
225 |
|
|
in_ctrl[1] => Equal0.IN14
|
226 |
|
|
in_ctrl[2] => Equal1.IN13
|
227 |
|
|
in_ctrl[2] => Equal0.IN13
|
228 |
|
|
in_ctrl[3] => Equal1.IN12
|
229 |
|
|
in_ctrl[3] => Equal0.IN12
|
230 |
|
|
in_ctrl[4] => Equal1.IN11
|
231 |
|
|
in_ctrl[4] => Equal0.IN11
|
232 |
|
|
in_ctrl[5] => Equal1.IN10
|
233 |
|
|
in_ctrl[5] => Equal0.IN10
|
234 |
|
|
in_ctrl[6] => Equal1.IN9
|
235 |
|
|
in_ctrl[6] => Equal0.IN9
|
236 |
|
|
in_ctrl[7] => Equal1.IN8
|
237 |
|
|
in_ctrl[7] => Equal0.IN8
|
238 |
|
|
in_wr => wr_en.IN0
|
239 |
|
|
in_rdy <=
|
240 |
|
|
in_rd => table:table_Inst.in_rd
|
241 |
|
|
in_key[0] => table:table_Inst.in_key[0]
|
242 |
|
|
in_key[1] => table:table_Inst.in_key[1]
|
243 |
|
|
in_key[2] => table:table_Inst.in_key[2]
|
244 |
|
|
in_key[3] => table:table_Inst.in_key[3]
|
245 |
|
|
in_key[4] => table:table_Inst.in_key[4]
|
246 |
|
|
in_key[5] => table:table_Inst.in_key[5]
|
247 |
|
|
in_key[6] => table:table_Inst.in_key[6]
|
248 |
|
|
in_key[7] => table:table_Inst.in_key[7]
|
249 |
|
|
in_key[8] => table:table_Inst.in_key[8]
|
250 |
|
|
in_key[9] => table:table_Inst.in_key[9]
|
251 |
|
|
out_mac[0] <= table:table_Inst.out_mac[0]
|
252 |
|
|
out_mac[1] <= table:table_Inst.out_mac[1]
|
253 |
|
|
out_mac[2] <= table:table_Inst.out_mac[2]
|
254 |
|
|
out_mac[3] <= table:table_Inst.out_mac[3]
|
255 |
|
|
out_mac[4] <= table:table_Inst.out_mac[4]
|
256 |
|
|
out_mac[5] <= table:table_Inst.out_mac[5]
|
257 |
|
|
out_mac[6] <= table:table_Inst.out_mac[6]
|
258 |
|
|
out_mac[7] <= table:table_Inst.out_mac[7]
|
259 |
|
|
out_mac[8] <= table:table_Inst.out_mac[8]
|
260 |
|
|
out_mac[9] <= table:table_Inst.out_mac[9]
|
261 |
|
|
out_mac[10] <= table:table_Inst.out_mac[10]
|
262 |
|
|
out_mac[11] <= table:table_Inst.out_mac[11]
|
263 |
|
|
out_mac[12] <= table:table_Inst.out_mac[12]
|
264 |
|
|
out_mac[13] <= table:table_Inst.out_mac[13]
|
265 |
|
|
out_mac[14] <= table:table_Inst.out_mac[14]
|
266 |
|
|
out_mac[15] <= table:table_Inst.out_mac[15]
|
267 |
|
|
out_mac[16] <= table:table_Inst.out_mac[16]
|
268 |
|
|
out_mac[17] <= table:table_Inst.out_mac[17]
|
269 |
|
|
out_mac[18] <= table:table_Inst.out_mac[18]
|
270 |
|
|
out_mac[19] <= table:table_Inst.out_mac[19]
|
271 |
|
|
out_mac[20] <= table:table_Inst.out_mac[20]
|
272 |
|
|
out_mac[21] <= table:table_Inst.out_mac[21]
|
273 |
|
|
out_mac[22] <= table:table_Inst.out_mac[22]
|
274 |
|
|
out_mac[23] <= table:table_Inst.out_mac[23]
|
275 |
|
|
out_mac[24] <= table:table_Inst.out_mac[24]
|
276 |
|
|
out_mac[25] <= table:table_Inst.out_mac[25]
|
277 |
|
|
out_mac[26] <= table:table_Inst.out_mac[26]
|
278 |
|
|
out_mac[27] <= table:table_Inst.out_mac[27]
|
279 |
|
|
out_mac[28] <= table:table_Inst.out_mac[28]
|
280 |
|
|
out_mac[29] <= table:table_Inst.out_mac[29]
|
281 |
|
|
out_mac[30] <= table:table_Inst.out_mac[30]
|
282 |
|
|
out_mac[31] <= table:table_Inst.out_mac[31]
|
283 |
|
|
out_mac[32] <= table:table_Inst.out_mac[32]
|
284 |
|
|
out_mac[33] <= table:table_Inst.out_mac[33]
|
285 |
|
|
out_mac[34] <= table:table_Inst.out_mac[34]
|
286 |
|
|
out_mac[35] <= table:table_Inst.out_mac[35]
|
287 |
|
|
out_mac[36] <= table:table_Inst.out_mac[36]
|
288 |
|
|
out_mac[37] <= table:table_Inst.out_mac[37]
|
289 |
|
|
out_mac[38] <= table:table_Inst.out_mac[38]
|
290 |
|
|
out_mac[39] <= table:table_Inst.out_mac[39]
|
291 |
|
|
out_mac[40] <= table:table_Inst.out_mac[40]
|
292 |
|
|
out_mac[41] <= table:table_Inst.out_mac[41]
|
293 |
|
|
out_mac[42] <= table:table_Inst.out_mac[42]
|
294 |
|
|
out_mac[43] <= table:table_Inst.out_mac[43]
|
295 |
|
|
out_mac[44] <= table:table_Inst.out_mac[44]
|
296 |
|
|
out_mac[45] <= table:table_Inst.out_mac[45]
|
297 |
|
|
out_mac[46] <= table:table_Inst.out_mac[46]
|
298 |
|
|
out_mac[47] <= table:table_Inst.out_mac[47]
|
299 |
|
|
out_port[0] <= table:table_Inst.out_port[0]
|
300 |
|
|
out_port[1] <= table:table_Inst.out_port[1]
|
301 |
|
|
out_port[2] <= table:table_Inst.out_port[2]
|
302 |
|
|
out_port[3] <= table:table_Inst.out_port[3]
|
303 |
|
|
out_port[4] <= table:table_Inst.out_port[4]
|
304 |
|
|
out_port[5] <= table:table_Inst.out_port[5]
|
305 |
|
|
out_port[6] <= table:table_Inst.out_port[6]
|
306 |
|
|
out_port[7] <= table:table_Inst.out_port[7]
|
307 |
|
|
out_rd_rdy <= table:table_Inst.out_rd_rdy
|
308 |
|
|
out_rdy => ~NO_FANOUT~
|
309 |
|
|
en => wr_en.IN1
|
310 |
|
|
reset => table:table_Inst.reset
|
311 |
|
|
reset => mac_cnt[31].ENA
|
312 |
|
|
reset => mac_cnt[30].ENA
|
313 |
|
|
reset => mac_cnt[29].ENA
|
314 |
|
|
reset => mac_cnt[28].ENA
|
315 |
|
|
reset => mac_cnt[27].ENA
|
316 |
|
|
reset => mac_cnt[26].ENA
|
317 |
|
|
reset => mac_cnt[25].ENA
|
318 |
|
|
reset => mac_cnt[24].ENA
|
319 |
|
|
reset => mac_cnt[23].ENA
|
320 |
|
|
reset => mac_cnt[22].ENA
|
321 |
|
|
reset => mac_cnt[21].ENA
|
322 |
|
|
reset => mac_cnt[20].ENA
|
323 |
|
|
reset => mac_cnt[19].ENA
|
324 |
|
|
reset => mac_cnt[18].ENA
|
325 |
|
|
reset => mac_cnt[17].ENA
|
326 |
|
|
reset => mac_cnt[16].ENA
|
327 |
|
|
reset => mac_cnt[15].ENA
|
328 |
|
|
reset => mac_cnt[14].ENA
|
329 |
|
|
reset => mac_cnt[13].ENA
|
330 |
|
|
reset => mac_cnt[12].ENA
|
331 |
|
|
reset => mac_cnt[11].ENA
|
332 |
|
|
reset => mac_cnt[10].ENA
|
333 |
|
|
reset => mac_cnt[9].ENA
|
334 |
|
|
reset => mac_cnt[8].ENA
|
335 |
|
|
reset => mac_cnt[7].ENA
|
336 |
|
|
reset => mac_cnt[6].ENA
|
337 |
|
|
reset => mac_cnt[5].ENA
|
338 |
|
|
reset => mac_cnt[4].ENA
|
339 |
|
|
reset => mac_cnt[3].ENA
|
340 |
|
|
reset => mac_cnt[2].ENA
|
341 |
|
|
reset => mac_cnt[1].ENA
|
342 |
|
|
reset => mac_cnt[0].ENA
|
343 |
|
|
reset => mac[47].ENA
|
344 |
|
|
reset => mac[46].ENA
|
345 |
|
|
reset => mac[45].ENA
|
346 |
|
|
reset => mac[44].ENA
|
347 |
|
|
reset => mac[43].ENA
|
348 |
|
|
reset => mac[42].ENA
|
349 |
|
|
reset => mac[41].ENA
|
350 |
|
|
reset => mac[40].ENA
|
351 |
|
|
reset => mac[39].ENA
|
352 |
|
|
reset => mac[38].ENA
|
353 |
|
|
reset => mac[37].ENA
|
354 |
|
|
reset => mac[36].ENA
|
355 |
|
|
reset => mac[35].ENA
|
356 |
|
|
reset => mac[34].ENA
|
357 |
|
|
reset => mac[33].ENA
|
358 |
|
|
reset => mac[32].ENA
|
359 |
|
|
reset => mac[31].ENA
|
360 |
|
|
reset => mac[30].ENA
|
361 |
|
|
reset => mac[29].ENA
|
362 |
|
|
reset => mac[28].ENA
|
363 |
|
|
reset => mac[27].ENA
|
364 |
|
|
reset => mac[26].ENA
|
365 |
|
|
reset => mac[25].ENA
|
366 |
|
|
reset => mac[24].ENA
|
367 |
|
|
reset => mac[23].ENA
|
368 |
|
|
reset => mac[22].ENA
|
369 |
|
|
reset => mac[21].ENA
|
370 |
|
|
reset => mac[20].ENA
|
371 |
|
|
reset => mac[19].ENA
|
372 |
|
|
reset => mac[18].ENA
|
373 |
|
|
reset => mac[17].ENA
|
374 |
|
|
reset => mac[16].ENA
|
375 |
|
|
reset => mac[15].ENA
|
376 |
|
|
reset => mac[14].ENA
|
377 |
|
|
reset => mac[13].ENA
|
378 |
|
|
reset => mac[12].ENA
|
379 |
|
|
reset => mac[11].ENA
|
380 |
|
|
reset => mac[10].ENA
|
381 |
|
|
reset => mac[9].ENA
|
382 |
|
|
reset => mac[8].ENA
|
383 |
|
|
reset => mac[7].ENA
|
384 |
|
|
reset => mac[6].ENA
|
385 |
|
|
reset => mac[5].ENA
|
386 |
|
|
reset => mac[4].ENA
|
387 |
|
|
reset => mac[3].ENA
|
388 |
|
|
reset => mac[2].ENA
|
389 |
|
|
reset => mac[1].ENA
|
390 |
|
|
reset => mac[0].ENA
|
391 |
|
|
reset => mac_weight[7].ENA
|
392 |
|
|
reset => mac_weight[6].ENA
|
393 |
|
|
reset => mac_weight[5].ENA
|
394 |
|
|
reset => mac_weight[4].ENA
|
395 |
|
|
reset => mac_weight[3].ENA
|
396 |
|
|
reset => mac_weight[2].ENA
|
397 |
|
|
reset => mac_weight[1].ENA
|
398 |
|
|
reset => mac_weight[0].ENA
|
399 |
|
|
reset => mac_exit_port[7].ENA
|
400 |
|
|
reset => mac_exit_port[6].ENA
|
401 |
|
|
reset => mac_exit_port[5].ENA
|
402 |
|
|
reset => mac_exit_port[4].ENA
|
403 |
|
|
reset => mac_exit_port[3].ENA
|
404 |
|
|
reset => mac_exit_port[2].ENA
|
405 |
|
|
reset => mac_exit_port[1].ENA
|
406 |
|
|
reset => mac_exit_port[0].ENA
|
407 |
|
|
reset => mac_wr.ENA
|
408 |
|
|
reset => state~1.IN1
|
409 |
|
|
clk => mac_cnt[31].CLK
|
410 |
|
|
clk => mac_cnt[30].CLK
|
411 |
|
|
clk => mac_cnt[29].CLK
|
412 |
|
|
clk => mac_cnt[28].CLK
|
413 |
|
|
clk => mac_cnt[27].CLK
|
414 |
|
|
clk => mac_cnt[26].CLK
|
415 |
|
|
clk => mac_cnt[25].CLK
|
416 |
|
|
clk => mac_cnt[24].CLK
|
417 |
|
|
clk => mac_cnt[23].CLK
|
418 |
|
|
clk => mac_cnt[22].CLK
|
419 |
|
|
clk => mac_cnt[21].CLK
|
420 |
|
|
clk => mac_cnt[20].CLK
|
421 |
|
|
clk => mac_cnt[19].CLK
|
422 |
|
|
clk => mac_cnt[18].CLK
|
423 |
|
|
clk => mac_cnt[17].CLK
|
424 |
|
|
clk => mac_cnt[16].CLK
|
425 |
|
|
clk => mac_cnt[15].CLK
|
426 |
|
|
clk => mac_cnt[14].CLK
|
427 |
|
|
clk => mac_cnt[13].CLK
|
428 |
|
|
clk => mac_cnt[12].CLK
|
429 |
|
|
clk => mac_cnt[11].CLK
|
430 |
|
|
clk => mac_cnt[10].CLK
|
431 |
|
|
clk => mac_cnt[9].CLK
|
432 |
|
|
clk => mac_cnt[8].CLK
|
433 |
|
|
clk => mac_cnt[7].CLK
|
434 |
|
|
clk => mac_cnt[6].CLK
|
435 |
|
|
clk => mac_cnt[5].CLK
|
436 |
|
|
clk => mac_cnt[4].CLK
|
437 |
|
|
clk => mac_cnt[3].CLK
|
438 |
|
|
clk => mac_cnt[2].CLK
|
439 |
|
|
clk => mac_cnt[1].CLK
|
440 |
|
|
clk => mac_cnt[0].CLK
|
441 |
|
|
clk => mac[47].CLK
|
442 |
|
|
clk => mac[46].CLK
|
443 |
|
|
clk => mac[45].CLK
|
444 |
|
|
clk => mac[44].CLK
|
445 |
|
|
clk => mac[43].CLK
|
446 |
|
|
clk => mac[42].CLK
|
447 |
|
|
clk => mac[41].CLK
|
448 |
|
|
clk => mac[40].CLK
|
449 |
|
|
clk => mac[39].CLK
|
450 |
|
|
clk => mac[38].CLK
|
451 |
|
|
clk => mac[37].CLK
|
452 |
|
|
clk => mac[36].CLK
|
453 |
|
|
clk => mac[35].CLK
|
454 |
|
|
clk => mac[34].CLK
|
455 |
|
|
clk => mac[33].CLK
|
456 |
|
|
clk => mac[32].CLK
|
457 |
|
|
clk => mac[31].CLK
|
458 |
|
|
clk => mac[30].CLK
|
459 |
|
|
clk => mac[29].CLK
|
460 |
|
|
clk => mac[28].CLK
|
461 |
|
|
clk => mac[27].CLK
|
462 |
|
|
clk => mac[26].CLK
|
463 |
|
|
clk => mac[25].CLK
|
464 |
|
|
clk => mac[24].CLK
|
465 |
|
|
clk => mac[23].CLK
|
466 |
|
|
clk => mac[22].CLK
|
467 |
|
|
clk => mac[21].CLK
|
468 |
|
|
clk => mac[20].CLK
|
469 |
|
|
clk => mac[19].CLK
|
470 |
|
|
clk => mac[18].CLK
|
471 |
|
|
clk => mac[17].CLK
|
472 |
|
|
clk => mac[16].CLK
|
473 |
|
|
clk => mac[15].CLK
|
474 |
|
|
clk => mac[14].CLK
|
475 |
|
|
clk => mac[13].CLK
|
476 |
|
|
clk => mac[12].CLK
|
477 |
|
|
clk => mac[11].CLK
|
478 |
|
|
clk => mac[10].CLK
|
479 |
|
|
clk => mac[9].CLK
|
480 |
|
|
clk => mac[8].CLK
|
481 |
|
|
clk => mac[7].CLK
|
482 |
|
|
clk => mac[6].CLK
|
483 |
|
|
clk => mac[5].CLK
|
484 |
|
|
clk => mac[4].CLK
|
485 |
|
|
clk => mac[3].CLK
|
486 |
|
|
clk => mac[2].CLK
|
487 |
|
|
clk => mac[1].CLK
|
488 |
|
|
clk => mac[0].CLK
|
489 |
|
|
clk => mac_weight[7].CLK
|
490 |
|
|
clk => mac_weight[6].CLK
|
491 |
|
|
clk => mac_weight[5].CLK
|
492 |
|
|
clk => mac_weight[4].CLK
|
493 |
|
|
clk => mac_weight[3].CLK
|
494 |
|
|
clk => mac_weight[2].CLK
|
495 |
|
|
clk => mac_weight[1].CLK
|
496 |
|
|
clk => mac_weight[0].CLK
|
497 |
|
|
clk => mac_exit_port[7].CLK
|
498 |
|
|
clk => mac_exit_port[6].CLK
|
499 |
|
|
clk => mac_exit_port[5].CLK
|
500 |
|
|
clk => mac_exit_port[4].CLK
|
501 |
|
|
clk => mac_exit_port[3].CLK
|
502 |
|
|
clk => mac_exit_port[2].CLK
|
503 |
|
|
clk => mac_exit_port[1].CLK
|
504 |
|
|
clk => mac_exit_port[0].CLK
|
505 |
|
|
clk => mac_wr.CLK
|
506 |
|
|
clk => \process6:cnt[7].CLK
|
507 |
|
|
clk => \process6:cnt[6].CLK
|
508 |
|
|
clk => \process6:cnt[5].CLK
|
509 |
|
|
clk => \process6:cnt[4].CLK
|
510 |
|
|
clk => \process6:cnt[3].CLK
|
511 |
|
|
clk => \process6:cnt[2].CLK
|
512 |
|
|
clk => \process6:cnt[1].CLK
|
513 |
|
|
clk => \process6:cnt[0].CLK
|
514 |
|
|
clk => table:table_Inst.clk
|
515 |
|
|
clk => state~0.IN1
|
516 |
|
|
|
517 |
|
|
|
518 |
|
|
|LB|manager:inst|table:table_Inst
|
519 |
|
|
clk => mac_ram_table:ram_Inst.clk
|
520 |
|
|
clk => last[9].CLK
|
521 |
|
|
clk => last[8].CLK
|
522 |
|
|
clk => last[7].CLK
|
523 |
|
|
clk => last[6].CLK
|
524 |
|
|
clk => last[5].CLK
|
525 |
|
|
clk => last[4].CLK
|
526 |
|
|
clk => last[3].CLK
|
527 |
|
|
clk => last[2].CLK
|
528 |
|
|
clk => last[1].CLK
|
529 |
|
|
clk => last[0].CLK
|
530 |
|
|
clk => cnt[7].CLK
|
531 |
|
|
clk => cnt[6].CLK
|
532 |
|
|
clk => cnt[5].CLK
|
533 |
|
|
clk => cnt[4].CLK
|
534 |
|
|
clk => cnt[3].CLK
|
535 |
|
|
clk => cnt[2].CLK
|
536 |
|
|
clk => cnt[1].CLK
|
537 |
|
|
clk => cnt[0].CLK
|
538 |
|
|
clk => small_fifo:small_fifo_Inst.clk
|
539 |
|
|
clk => state~0.IN1
|
540 |
|
|
reset => mac_ram_table:ram_Inst.reset
|
541 |
|
|
reset => last[9].ACLR
|
542 |
|
|
reset => last[8].ACLR
|
543 |
|
|
reset => last[7].ACLR
|
544 |
|
|
reset => last[6].ACLR
|
545 |
|
|
reset => last[5].ACLR
|
546 |
|
|
reset => last[4].ACLR
|
547 |
|
|
reset => last[3].ACLR
|
548 |
|
|
reset => last[2].ACLR
|
549 |
|
|
reset => last[1].ACLR
|
550 |
|
|
reset => last[0].ACLR
|
551 |
|
|
reset => small_fifo:small_fifo_Inst.reset
|
552 |
|
|
reset => state~1.IN1
|
553 |
|
|
in_mac[0] => small_fifo:small_fifo_Inst.din[16]
|
554 |
|
|
in_mac[1] => small_fifo:small_fifo_Inst.din[17]
|
555 |
|
|
in_mac[2] => small_fifo:small_fifo_Inst.din[18]
|
556 |
|
|
in_mac[3] => small_fifo:small_fifo_Inst.din[19]
|
557 |
|
|
in_mac[4] => small_fifo:small_fifo_Inst.din[20]
|
558 |
|
|
in_mac[5] => small_fifo:small_fifo_Inst.din[21]
|
559 |
|
|
in_mac[6] => small_fifo:small_fifo_Inst.din[22]
|
560 |
|
|
in_mac[7] => small_fifo:small_fifo_Inst.din[23]
|
561 |
|
|
in_mac[8] => small_fifo:small_fifo_Inst.din[24]
|
562 |
|
|
in_mac[9] => small_fifo:small_fifo_Inst.din[25]
|
563 |
|
|
in_mac[10] => small_fifo:small_fifo_Inst.din[26]
|
564 |
|
|
in_mac[11] => small_fifo:small_fifo_Inst.din[27]
|
565 |
|
|
in_mac[12] => small_fifo:small_fifo_Inst.din[28]
|
566 |
|
|
in_mac[13] => small_fifo:small_fifo_Inst.din[29]
|
567 |
|
|
in_mac[14] => small_fifo:small_fifo_Inst.din[30]
|
568 |
|
|
in_mac[15] => small_fifo:small_fifo_Inst.din[31]
|
569 |
|
|
in_mac[16] => small_fifo:small_fifo_Inst.din[32]
|
570 |
|
|
in_mac[17] => small_fifo:small_fifo_Inst.din[33]
|
571 |
|
|
in_mac[18] => small_fifo:small_fifo_Inst.din[34]
|
572 |
|
|
in_mac[19] => small_fifo:small_fifo_Inst.din[35]
|
573 |
|
|
in_mac[20] => small_fifo:small_fifo_Inst.din[36]
|
574 |
|
|
in_mac[21] => small_fifo:small_fifo_Inst.din[37]
|
575 |
|
|
in_mac[22] => small_fifo:small_fifo_Inst.din[38]
|
576 |
|
|
in_mac[23] => small_fifo:small_fifo_Inst.din[39]
|
577 |
|
|
in_mac[24] => small_fifo:small_fifo_Inst.din[40]
|
578 |
|
|
in_mac[25] => small_fifo:small_fifo_Inst.din[41]
|
579 |
|
|
in_mac[26] => small_fifo:small_fifo_Inst.din[42]
|
580 |
|
|
in_mac[27] => small_fifo:small_fifo_Inst.din[43]
|
581 |
|
|
in_mac[28] => small_fifo:small_fifo_Inst.din[44]
|
582 |
|
|
in_mac[29] => small_fifo:small_fifo_Inst.din[45]
|
583 |
|
|
in_mac[30] => small_fifo:small_fifo_Inst.din[46]
|
584 |
|
|
in_mac[31] => small_fifo:small_fifo_Inst.din[47]
|
585 |
|
|
in_mac[32] => small_fifo:small_fifo_Inst.din[48]
|
586 |
|
|
in_mac[33] => small_fifo:small_fifo_Inst.din[49]
|
587 |
|
|
in_mac[34] => small_fifo:small_fifo_Inst.din[50]
|
588 |
|
|
in_mac[35] => small_fifo:small_fifo_Inst.din[51]
|
589 |
|
|
in_mac[36] => small_fifo:small_fifo_Inst.din[52]
|
590 |
|
|
in_mac[37] => small_fifo:small_fifo_Inst.din[53]
|
591 |
|
|
in_mac[38] => small_fifo:small_fifo_Inst.din[54]
|
592 |
|
|
in_mac[39] => small_fifo:small_fifo_Inst.din[55]
|
593 |
|
|
in_mac[40] => small_fifo:small_fifo_Inst.din[56]
|
594 |
|
|
in_mac[41] => small_fifo:small_fifo_Inst.din[57]
|
595 |
|
|
in_mac[42] => small_fifo:small_fifo_Inst.din[58]
|
596 |
|
|
in_mac[43] => small_fifo:small_fifo_Inst.din[59]
|
597 |
|
|
in_mac[44] => small_fifo:small_fifo_Inst.din[60]
|
598 |
|
|
in_mac[45] => small_fifo:small_fifo_Inst.din[61]
|
599 |
|
|
in_mac[46] => small_fifo:small_fifo_Inst.din[62]
|
600 |
|
|
in_mac[47] => small_fifo:small_fifo_Inst.din[63]
|
601 |
|
|
in_weight[0] => small_fifo:small_fifo_Inst.din[8]
|
602 |
|
|
in_weight[1] => small_fifo:small_fifo_Inst.din[9]
|
603 |
|
|
in_weight[2] => small_fifo:small_fifo_Inst.din[10]
|
604 |
|
|
in_weight[3] => small_fifo:small_fifo_Inst.din[11]
|
605 |
|
|
in_weight[4] => small_fifo:small_fifo_Inst.din[12]
|
606 |
|
|
in_weight[5] => small_fifo:small_fifo_Inst.din[13]
|
607 |
|
|
in_weight[6] => small_fifo:small_fifo_Inst.din[14]
|
608 |
|
|
in_weight[7] => small_fifo:small_fifo_Inst.din[15]
|
609 |
|
|
in_port[0] => small_fifo:small_fifo_Inst.din[0]
|
610 |
|
|
in_port[1] => small_fifo:small_fifo_Inst.din[1]
|
611 |
|
|
in_port[2] => small_fifo:small_fifo_Inst.din[2]
|
612 |
|
|
in_port[3] => small_fifo:small_fifo_Inst.din[3]
|
613 |
|
|
in_port[4] => small_fifo:small_fifo_Inst.din[4]
|
614 |
|
|
in_port[5] => small_fifo:small_fifo_Inst.din[5]
|
615 |
|
|
in_port[6] => small_fifo:small_fifo_Inst.din[6]
|
616 |
|
|
in_port[7] => small_fifo:small_fifo_Inst.din[7]
|
617 |
|
|
in_wr => small_fifo:small_fifo_Inst.wr_en
|
618 |
|
|
in_rd => mac_ram_table:ram_Inst.in_rd
|
619 |
|
|
in_key[0] => mac_ram_table:ram_Inst.in_key[0]
|
620 |
|
|
in_key[1] => mac_ram_table:ram_Inst.in_key[1]
|
621 |
|
|
in_key[2] => mac_ram_table:ram_Inst.in_key[2]
|
622 |
|
|
in_key[3] => mac_ram_table:ram_Inst.in_key[3]
|
623 |
|
|
in_key[4] => mac_ram_table:ram_Inst.in_key[4]
|
624 |
|
|
in_key[5] => mac_ram_table:ram_Inst.in_key[5]
|
625 |
|
|
in_key[6] => mac_ram_table:ram_Inst.in_key[6]
|
626 |
|
|
in_key[7] => mac_ram_table:ram_Inst.in_key[7]
|
627 |
|
|
in_key[8] => mac_ram_table:ram_Inst.in_key[8]
|
628 |
|
|
in_key[9] => mac_ram_table:ram_Inst.in_key[9]
|
629 |
|
|
out_mac[0] <= mac_ram_table:ram_Inst.out_mac[0]
|
630 |
|
|
out_mac[1] <= mac_ram_table:ram_Inst.out_mac[1]
|
631 |
|
|
out_mac[2] <= mac_ram_table:ram_Inst.out_mac[2]
|
632 |
|
|
out_mac[3] <= mac_ram_table:ram_Inst.out_mac[3]
|
633 |
|
|
out_mac[4] <= mac_ram_table:ram_Inst.out_mac[4]
|
634 |
|
|
out_mac[5] <= mac_ram_table:ram_Inst.out_mac[5]
|
635 |
|
|
out_mac[6] <= mac_ram_table:ram_Inst.out_mac[6]
|
636 |
|
|
out_mac[7] <= mac_ram_table:ram_Inst.out_mac[7]
|
637 |
|
|
out_mac[8] <= mac_ram_table:ram_Inst.out_mac[8]
|
638 |
|
|
out_mac[9] <= mac_ram_table:ram_Inst.out_mac[9]
|
639 |
|
|
out_mac[10] <= mac_ram_table:ram_Inst.out_mac[10]
|
640 |
|
|
out_mac[11] <= mac_ram_table:ram_Inst.out_mac[11]
|
641 |
|
|
out_mac[12] <= mac_ram_table:ram_Inst.out_mac[12]
|
642 |
|
|
out_mac[13] <= mac_ram_table:ram_Inst.out_mac[13]
|
643 |
|
|
out_mac[14] <= mac_ram_table:ram_Inst.out_mac[14]
|
644 |
|
|
out_mac[15] <= mac_ram_table:ram_Inst.out_mac[15]
|
645 |
|
|
out_mac[16] <= mac_ram_table:ram_Inst.out_mac[16]
|
646 |
|
|
out_mac[17] <= mac_ram_table:ram_Inst.out_mac[17]
|
647 |
|
|
out_mac[18] <= mac_ram_table:ram_Inst.out_mac[18]
|
648 |
|
|
out_mac[19] <= mac_ram_table:ram_Inst.out_mac[19]
|
649 |
|
|
out_mac[20] <= mac_ram_table:ram_Inst.out_mac[20]
|
650 |
|
|
out_mac[21] <= mac_ram_table:ram_Inst.out_mac[21]
|
651 |
|
|
out_mac[22] <= mac_ram_table:ram_Inst.out_mac[22]
|
652 |
|
|
out_mac[23] <= mac_ram_table:ram_Inst.out_mac[23]
|
653 |
|
|
out_mac[24] <= mac_ram_table:ram_Inst.out_mac[24]
|
654 |
|
|
out_mac[25] <= mac_ram_table:ram_Inst.out_mac[25]
|
655 |
|
|
out_mac[26] <= mac_ram_table:ram_Inst.out_mac[26]
|
656 |
|
|
out_mac[27] <= mac_ram_table:ram_Inst.out_mac[27]
|
657 |
|
|
out_mac[28] <= mac_ram_table:ram_Inst.out_mac[28]
|
658 |
|
|
out_mac[29] <= mac_ram_table:ram_Inst.out_mac[29]
|
659 |
|
|
out_mac[30] <= mac_ram_table:ram_Inst.out_mac[30]
|
660 |
|
|
out_mac[31] <= mac_ram_table:ram_Inst.out_mac[31]
|
661 |
|
|
out_mac[32] <= mac_ram_table:ram_Inst.out_mac[32]
|
662 |
|
|
out_mac[33] <= mac_ram_table:ram_Inst.out_mac[33]
|
663 |
|
|
out_mac[34] <= mac_ram_table:ram_Inst.out_mac[34]
|
664 |
|
|
out_mac[35] <= mac_ram_table:ram_Inst.out_mac[35]
|
665 |
|
|
out_mac[36] <= mac_ram_table:ram_Inst.out_mac[36]
|
666 |
|
|
out_mac[37] <= mac_ram_table:ram_Inst.out_mac[37]
|
667 |
|
|
out_mac[38] <= mac_ram_table:ram_Inst.out_mac[38]
|
668 |
|
|
out_mac[39] <= mac_ram_table:ram_Inst.out_mac[39]
|
669 |
|
|
out_mac[40] <= mac_ram_table:ram_Inst.out_mac[40]
|
670 |
|
|
out_mac[41] <= mac_ram_table:ram_Inst.out_mac[41]
|
671 |
|
|
out_mac[42] <= mac_ram_table:ram_Inst.out_mac[42]
|
672 |
|
|
out_mac[43] <= mac_ram_table:ram_Inst.out_mac[43]
|
673 |
|
|
out_mac[44] <= mac_ram_table:ram_Inst.out_mac[44]
|
674 |
|
|
out_mac[45] <= mac_ram_table:ram_Inst.out_mac[45]
|
675 |
|
|
out_mac[46] <= mac_ram_table:ram_Inst.out_mac[46]
|
676 |
|
|
out_mac[47] <= mac_ram_table:ram_Inst.out_mac[47]
|
677 |
|
|
out_port[0] <= mac_ram_table:ram_Inst.out_port[0]
|
678 |
|
|
out_port[1] <= mac_ram_table:ram_Inst.out_port[1]
|
679 |
|
|
out_port[2] <= mac_ram_table:ram_Inst.out_port[2]
|
680 |
|
|
out_port[3] <= mac_ram_table:ram_Inst.out_port[3]
|
681 |
|
|
out_port[4] <= mac_ram_table:ram_Inst.out_port[4]
|
682 |
|
|
out_port[5] <= mac_ram_table:ram_Inst.out_port[5]
|
683 |
|
|
out_port[6] <= mac_ram_table:ram_Inst.out_port[6]
|
684 |
|
|
out_port[7] <= mac_ram_table:ram_Inst.out_port[7]
|
685 |
|
|
out_rd_rdy <= mac_ram_table:ram_Inst.out_rd_rdy
|
686 |
|
|
|
687 |
|
|
|
688 |
|
|
|LB|manager:inst|table:table_Inst|small_fifo:small_fifo_Inst
|
689 |
|
|
din[0] => queue.data_a[0].DATAIN
|
690 |
|
|
din[0] => queue.DATAIN
|
691 |
|
|
din[1] => queue.data_a[1].DATAIN
|
692 |
|
|
din[1] => queue.DATAIN1
|
693 |
|
|
din[2] => queue.data_a[2].DATAIN
|
694 |
|
|
din[2] => queue.DATAIN2
|
695 |
|
|
din[3] => queue.data_a[3].DATAIN
|
696 |
|
|
din[3] => queue.DATAIN3
|
697 |
|
|
din[4] => queue.data_a[4].DATAIN
|
698 |
|
|
din[4] => queue.DATAIN4
|
699 |
|
|
din[5] => queue.data_a[5].DATAIN
|
700 |
|
|
din[5] => queue.DATAIN5
|
701 |
|
|
din[6] => queue.data_a[6].DATAIN
|
702 |
|
|
din[6] => queue.DATAIN6
|
703 |
|
|
din[7] => queue.data_a[7].DATAIN
|
704 |
|
|
din[7] => queue.DATAIN7
|
705 |
|
|
din[8] => queue.data_a[8].DATAIN
|
706 |
|
|
din[8] => queue.DATAIN8
|
707 |
|
|
din[9] => queue.data_a[9].DATAIN
|
708 |
|
|
din[9] => queue.DATAIN9
|
709 |
|
|
din[10] => queue.data_a[10].DATAIN
|
710 |
|
|
din[10] => queue.DATAIN10
|
711 |
|
|
din[11] => queue.data_a[11].DATAIN
|
712 |
|
|
din[11] => queue.DATAIN11
|
713 |
|
|
din[12] => queue.data_a[12].DATAIN
|
714 |
|
|
din[12] => queue.DATAIN12
|
715 |
|
|
din[13] => queue.data_a[13].DATAIN
|
716 |
|
|
din[13] => queue.DATAIN13
|
717 |
|
|
din[14] => queue.data_a[14].DATAIN
|
718 |
|
|
din[14] => queue.DATAIN14
|
719 |
|
|
din[15] => queue.data_a[15].DATAIN
|
720 |
|
|
din[15] => queue.DATAIN15
|
721 |
|
|
din[16] => queue.data_a[16].DATAIN
|
722 |
|
|
din[16] => queue.DATAIN16
|
723 |
|
|
din[17] => queue.data_a[17].DATAIN
|
724 |
|
|
din[17] => queue.DATAIN17
|
725 |
|
|
din[18] => queue.data_a[18].DATAIN
|
726 |
|
|
din[18] => queue.DATAIN18
|
727 |
|
|
din[19] => queue.data_a[19].DATAIN
|
728 |
|
|
din[19] => queue.DATAIN19
|
729 |
|
|
din[20] => queue.data_a[20].DATAIN
|
730 |
|
|
din[20] => queue.DATAIN20
|
731 |
|
|
din[21] => queue.data_a[21].DATAIN
|
732 |
|
|
din[21] => queue.DATAIN21
|
733 |
|
|
din[22] => queue.data_a[22].DATAIN
|
734 |
|
|
din[22] => queue.DATAIN22
|
735 |
|
|
din[23] => queue.data_a[23].DATAIN
|
736 |
|
|
din[23] => queue.DATAIN23
|
737 |
|
|
din[24] => queue.data_a[24].DATAIN
|
738 |
|
|
din[24] => queue.DATAIN24
|
739 |
|
|
din[25] => queue.data_a[25].DATAIN
|
740 |
|
|
din[25] => queue.DATAIN25
|
741 |
|
|
din[26] => queue.data_a[26].DATAIN
|
742 |
|
|
din[26] => queue.DATAIN26
|
743 |
|
|
din[27] => queue.data_a[27].DATAIN
|
744 |
|
|
din[27] => queue.DATAIN27
|
745 |
|
|
din[28] => queue.data_a[28].DATAIN
|
746 |
|
|
din[28] => queue.DATAIN28
|
747 |
|
|
din[29] => queue.data_a[29].DATAIN
|
748 |
|
|
din[29] => queue.DATAIN29
|
749 |
|
|
din[30] => queue.data_a[30].DATAIN
|
750 |
|
|
din[30] => queue.DATAIN30
|
751 |
|
|
din[31] => queue.data_a[31].DATAIN
|
752 |
|
|
din[31] => queue.DATAIN31
|
753 |
|
|
din[32] => queue.data_a[32].DATAIN
|
754 |
|
|
din[32] => queue.DATAIN32
|
755 |
|
|
din[33] => queue.data_a[33].DATAIN
|
756 |
|
|
din[33] => queue.DATAIN33
|
757 |
|
|
din[34] => queue.data_a[34].DATAIN
|
758 |
|
|
din[34] => queue.DATAIN34
|
759 |
|
|
din[35] => queue.data_a[35].DATAIN
|
760 |
|
|
din[35] => queue.DATAIN35
|
761 |
|
|
din[36] => queue.data_a[36].DATAIN
|
762 |
|
|
din[36] => queue.DATAIN36
|
763 |
|
|
din[37] => queue.data_a[37].DATAIN
|
764 |
|
|
din[37] => queue.DATAIN37
|
765 |
|
|
din[38] => queue.data_a[38].DATAIN
|
766 |
|
|
din[38] => queue.DATAIN38
|
767 |
|
|
din[39] => queue.data_a[39].DATAIN
|
768 |
|
|
din[39] => queue.DATAIN39
|
769 |
|
|
din[40] => queue.data_a[40].DATAIN
|
770 |
|
|
din[40] => queue.DATAIN40
|
771 |
|
|
din[41] => queue.data_a[41].DATAIN
|
772 |
|
|
din[41] => queue.DATAIN41
|
773 |
|
|
din[42] => queue.data_a[42].DATAIN
|
774 |
|
|
din[42] => queue.DATAIN42
|
775 |
|
|
din[43] => queue.data_a[43].DATAIN
|
776 |
|
|
din[43] => queue.DATAIN43
|
777 |
|
|
din[44] => queue.data_a[44].DATAIN
|
778 |
|
|
din[44] => queue.DATAIN44
|
779 |
|
|
din[45] => queue.data_a[45].DATAIN
|
780 |
|
|
din[45] => queue.DATAIN45
|
781 |
|
|
din[46] => queue.data_a[46].DATAIN
|
782 |
|
|
din[46] => queue.DATAIN46
|
783 |
|
|
din[47] => queue.data_a[47].DATAIN
|
784 |
|
|
din[47] => queue.DATAIN47
|
785 |
|
|
din[48] => queue.data_a[48].DATAIN
|
786 |
|
|
din[48] => queue.DATAIN48
|
787 |
|
|
din[49] => queue.data_a[49].DATAIN
|
788 |
|
|
din[49] => queue.DATAIN49
|
789 |
|
|
din[50] => queue.data_a[50].DATAIN
|
790 |
|
|
din[50] => queue.DATAIN50
|
791 |
|
|
din[51] => queue.data_a[51].DATAIN
|
792 |
|
|
din[51] => queue.DATAIN51
|
793 |
|
|
din[52] => queue.data_a[52].DATAIN
|
794 |
|
|
din[52] => queue.DATAIN52
|
795 |
|
|
din[53] => queue.data_a[53].DATAIN
|
796 |
|
|
din[53] => queue.DATAIN53
|
797 |
|
|
din[54] => queue.data_a[54].DATAIN
|
798 |
|
|
din[54] => queue.DATAIN54
|
799 |
|
|
din[55] => queue.data_a[55].DATAIN
|
800 |
|
|
din[55] => queue.DATAIN55
|
801 |
|
|
din[56] => queue.data_a[56].DATAIN
|
802 |
|
|
din[56] => queue.DATAIN56
|
803 |
|
|
din[57] => queue.data_a[57].DATAIN
|
804 |
|
|
din[57] => queue.DATAIN57
|
805 |
|
|
din[58] => queue.data_a[58].DATAIN
|
806 |
|
|
din[58] => queue.DATAIN58
|
807 |
|
|
din[59] => queue.data_a[59].DATAIN
|
808 |
|
|
din[59] => queue.DATAIN59
|
809 |
|
|
din[60] => queue.data_a[60].DATAIN
|
810 |
|
|
din[60] => queue.DATAIN60
|
811 |
|
|
din[61] => queue.data_a[61].DATAIN
|
812 |
|
|
din[61] => queue.DATAIN61
|
813 |
|
|
din[62] => queue.data_a[62].DATAIN
|
814 |
|
|
din[62] => queue.DATAIN62
|
815 |
|
|
din[63] => queue.data_a[63].DATAIN
|
816 |
|
|
din[63] => queue.DATAIN63
|
817 |
|
|
wr_en => always0~0.DATAIN
|
818 |
|
|
wr_en => always1~0.IN0
|
819 |
|
|
wr_en => wr_ptr~7.OUTPUTSELECT
|
820 |
|
|
wr_en => wr_ptr~6.OUTPUTSELECT
|
821 |
|
|
wr_en => wr_ptr~5.OUTPUTSELECT
|
822 |
|
|
wr_en => wr_ptr~4.OUTPUTSELECT
|
823 |
|
|
wr_en => wr_ptr~3.OUTPUTSELECT
|
824 |
|
|
wr_en => wr_ptr~2.OUTPUTSELECT
|
825 |
|
|
wr_en => wr_ptr~1.OUTPUTSELECT
|
826 |
|
|
wr_en => wr_ptr~0.OUTPUTSELECT
|
827 |
|
|
wr_en => always1~1.IN0
|
828 |
|
|
wr_en => queue.WE
|
829 |
|
|
rd_en => always1~1.IN1
|
830 |
|
|
rd_en => rd_ptr~7.OUTPUTSELECT
|
831 |
|
|
rd_en => rd_ptr~6.OUTPUTSELECT
|
832 |
|
|
rd_en => rd_ptr~5.OUTPUTSELECT
|
833 |
|
|
rd_en => rd_ptr~4.OUTPUTSELECT
|
834 |
|
|
rd_en => rd_ptr~3.OUTPUTSELECT
|
835 |
|
|
rd_en => rd_ptr~2.OUTPUTSELECT
|
836 |
|
|
rd_en => rd_ptr~1.OUTPUTSELECT
|
837 |
|
|
rd_en => rd_ptr~0.OUTPUTSELECT
|
838 |
|
|
rd_en => always1~0.IN1
|
839 |
|
|
rd_en => dout[0]~reg0.ENA
|
840 |
|
|
rd_en => dout[1]~reg0.ENA
|
841 |
|
|
rd_en => dout[2]~reg0.ENA
|
842 |
|
|
rd_en => dout[3]~reg0.ENA
|
843 |
|
|
rd_en => dout[4]~reg0.ENA
|
844 |
|
|
rd_en => dout[5]~reg0.ENA
|
845 |
|
|
rd_en => dout[6]~reg0.ENA
|
846 |
|
|
rd_en => dout[7]~reg0.ENA
|
847 |
|
|
rd_en => dout[8]~reg0.ENA
|
848 |
|
|
rd_en => dout[9]~reg0.ENA
|
849 |
|
|
rd_en => dout[10]~reg0.ENA
|
850 |
|
|
rd_en => dout[11]~reg0.ENA
|
851 |
|
|
rd_en => dout[12]~reg0.ENA
|
852 |
|
|
rd_en => dout[13]~reg0.ENA
|
853 |
|
|
rd_en => dout[14]~reg0.ENA
|
854 |
|
|
rd_en => dout[15]~reg0.ENA
|
855 |
|
|
rd_en => dout[16]~reg0.ENA
|
856 |
|
|
rd_en => dout[17]~reg0.ENA
|
857 |
|
|
rd_en => dout[18]~reg0.ENA
|
858 |
|
|
rd_en => dout[19]~reg0.ENA
|
859 |
|
|
rd_en => dout[20]~reg0.ENA
|
860 |
|
|
rd_en => dout[21]~reg0.ENA
|
861 |
|
|
rd_en => dout[22]~reg0.ENA
|
862 |
|
|
rd_en => dout[23]~reg0.ENA
|
863 |
|
|
rd_en => dout[24]~reg0.ENA
|
864 |
|
|
rd_en => dout[25]~reg0.ENA
|
865 |
|
|
rd_en => dout[26]~reg0.ENA
|
866 |
|
|
rd_en => dout[27]~reg0.ENA
|
867 |
|
|
rd_en => dout[28]~reg0.ENA
|
868 |
|
|
rd_en => dout[29]~reg0.ENA
|
869 |
|
|
rd_en => dout[30]~reg0.ENA
|
870 |
|
|
rd_en => dout[31]~reg0.ENA
|
871 |
|
|
rd_en => dout[32]~reg0.ENA
|
872 |
|
|
rd_en => dout[33]~reg0.ENA
|
873 |
|
|
rd_en => dout[34]~reg0.ENA
|
874 |
|
|
rd_en => dout[35]~reg0.ENA
|
875 |
|
|
rd_en => dout[36]~reg0.ENA
|
876 |
|
|
rd_en => dout[37]~reg0.ENA
|
877 |
|
|
rd_en => dout[38]~reg0.ENA
|
878 |
|
|
rd_en => dout[39]~reg0.ENA
|
879 |
|
|
rd_en => dout[40]~reg0.ENA
|
880 |
|
|
rd_en => dout[41]~reg0.ENA
|
881 |
|
|
rd_en => dout[42]~reg0.ENA
|
882 |
|
|
rd_en => dout[43]~reg0.ENA
|
883 |
|
|
rd_en => dout[44]~reg0.ENA
|
884 |
|
|
rd_en => dout[45]~reg0.ENA
|
885 |
|
|
rd_en => dout[46]~reg0.ENA
|
886 |
|
|
rd_en => dout[47]~reg0.ENA
|
887 |
|
|
rd_en => dout[48]~reg0.ENA
|
888 |
|
|
rd_en => dout[49]~reg0.ENA
|
889 |
|
|
rd_en => dout[50]~reg0.ENA
|
890 |
|
|
rd_en => dout[51]~reg0.ENA
|
891 |
|
|
rd_en => dout[52]~reg0.ENA
|
892 |
|
|
rd_en => dout[53]~reg0.ENA
|
893 |
|
|
rd_en => dout[54]~reg0.ENA
|
894 |
|
|
rd_en => dout[55]~reg0.ENA
|
895 |
|
|
rd_en => dout[56]~reg0.ENA
|
896 |
|
|
rd_en => dout[57]~reg0.ENA
|
897 |
|
|
rd_en => dout[58]~reg0.ENA
|
898 |
|
|
rd_en => dout[59]~reg0.ENA
|
899 |
|
|
rd_en => dout[60]~reg0.ENA
|
900 |
|
|
rd_en => dout[61]~reg0.ENA
|
901 |
|
|
rd_en => dout[62]~reg0.ENA
|
902 |
|
|
rd_en => dout[63]~reg0.ENA
|
903 |
|
|
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
904 |
|
|
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
905 |
|
|
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
906 |
|
|
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
907 |
|
|
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
908 |
|
|
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
909 |
|
|
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
910 |
|
|
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
911 |
|
|
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
912 |
|
|
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
913 |
|
|
dout[10] <= dout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
914 |
|
|
dout[11] <= dout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
915 |
|
|
dout[12] <= dout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
916 |
|
|
dout[13] <= dout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
917 |
|
|
dout[14] <= dout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
918 |
|
|
dout[15] <= dout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
919 |
|
|
dout[16] <= dout[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
920 |
|
|
dout[17] <= dout[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
921 |
|
|
dout[18] <= dout[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
922 |
|
|
dout[19] <= dout[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
923 |
|
|
dout[20] <= dout[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
924 |
|
|
dout[21] <= dout[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
925 |
|
|
dout[22] <= dout[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
926 |
|
|
dout[23] <= dout[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
927 |
|
|
dout[24] <= dout[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
928 |
|
|
dout[25] <= dout[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
929 |
|
|
dout[26] <= dout[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
930 |
|
|
dout[27] <= dout[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
931 |
|
|
dout[28] <= dout[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
932 |
|
|
dout[29] <= dout[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
933 |
|
|
dout[30] <= dout[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
934 |
|
|
dout[31] <= dout[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
935 |
|
|
dout[32] <= dout[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
936 |
|
|
dout[33] <= dout[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
937 |
|
|
dout[34] <= dout[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
938 |
|
|
dout[35] <= dout[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
939 |
|
|
dout[36] <= dout[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
940 |
|
|
dout[37] <= dout[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
941 |
|
|
dout[38] <= dout[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
942 |
|
|
dout[39] <= dout[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
943 |
|
|
dout[40] <= dout[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
944 |
|
|
dout[41] <= dout[41]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
945 |
|
|
dout[42] <= dout[42]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
946 |
|
|
dout[43] <= dout[43]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
947 |
|
|
dout[44] <= dout[44]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
948 |
|
|
dout[45] <= dout[45]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
949 |
|
|
dout[46] <= dout[46]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
950 |
|
|
dout[47] <= dout[47]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
951 |
|
|
dout[48] <= dout[48]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
952 |
|
|
dout[49] <= dout[49]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
953 |
|
|
dout[50] <= dout[50]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
954 |
|
|
dout[51] <= dout[51]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
955 |
|
|
dout[52] <= dout[52]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
956 |
|
|
dout[53] <= dout[53]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
957 |
|
|
dout[54] <= dout[54]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
958 |
|
|
dout[55] <= dout[55]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
959 |
|
|
dout[56] <= dout[56]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
960 |
|
|
dout[57] <= dout[57]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
961 |
|
|
dout[58] <= dout[58]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
962 |
|
|
dout[59] <= dout[59]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
963 |
|
|
dout[60] <= dout[60]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
964 |
|
|
dout[61] <= dout[61]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
965 |
|
|
dout[62] <= dout[62]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
966 |
|
|
dout[63] <= dout[63]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
967 |
|
|
full <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
968 |
|
|
nearly_full <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
|
969 |
|
|
empty <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
|
970 |
|
|
reset => depth~26.OUTPUTSELECT
|
971 |
|
|
reset => depth~25.OUTPUTSELECT
|
972 |
|
|
reset => depth~24.OUTPUTSELECT
|
973 |
|
|
reset => depth~23.OUTPUTSELECT
|
974 |
|
|
reset => depth~22.OUTPUTSELECT
|
975 |
|
|
reset => depth~21.OUTPUTSELECT
|
976 |
|
|
reset => depth~20.OUTPUTSELECT
|
977 |
|
|
reset => depth~19.OUTPUTSELECT
|
978 |
|
|
reset => depth~18.OUTPUTSELECT
|
979 |
|
|
reset => wr_ptr~15.OUTPUTSELECT
|
980 |
|
|
reset => wr_ptr~14.OUTPUTSELECT
|
981 |
|
|
reset => wr_ptr~13.OUTPUTSELECT
|
982 |
|
|
reset => wr_ptr~12.OUTPUTSELECT
|
983 |
|
|
reset => wr_ptr~11.OUTPUTSELECT
|
984 |
|
|
reset => wr_ptr~10.OUTPUTSELECT
|
985 |
|
|
reset => wr_ptr~9.OUTPUTSELECT
|
986 |
|
|
reset => wr_ptr~8.OUTPUTSELECT
|
987 |
|
|
reset => rd_ptr~15.OUTPUTSELECT
|
988 |
|
|
reset => rd_ptr~14.OUTPUTSELECT
|
989 |
|
|
reset => rd_ptr~13.OUTPUTSELECT
|
990 |
|
|
reset => rd_ptr~12.OUTPUTSELECT
|
991 |
|
|
reset => rd_ptr~11.OUTPUTSELECT
|
992 |
|
|
reset => rd_ptr~10.OUTPUTSELECT
|
993 |
|
|
reset => rd_ptr~9.OUTPUTSELECT
|
994 |
|
|
reset => rd_ptr~8.OUTPUTSELECT
|
995 |
|
|
clk => dout[63]~reg0.CLK
|
996 |
|
|
clk => dout[62]~reg0.CLK
|
997 |
|
|
clk => dout[61]~reg0.CLK
|
998 |
|
|
clk => dout[60]~reg0.CLK
|
999 |
|
|
clk => dout[59]~reg0.CLK
|
1000 |
|
|
clk => dout[58]~reg0.CLK
|
1001 |
|
|
clk => dout[57]~reg0.CLK
|
1002 |
|
|
clk => dout[56]~reg0.CLK
|
1003 |
|
|
clk => dout[55]~reg0.CLK
|
1004 |
|
|
clk => dout[54]~reg0.CLK
|
1005 |
|
|
clk => dout[53]~reg0.CLK
|
1006 |
|
|
clk => dout[52]~reg0.CLK
|
1007 |
|
|
clk => dout[51]~reg0.CLK
|
1008 |
|
|
clk => dout[50]~reg0.CLK
|
1009 |
|
|
clk => dout[49]~reg0.CLK
|
1010 |
|
|
clk => dout[48]~reg0.CLK
|
1011 |
|
|
clk => dout[47]~reg0.CLK
|
1012 |
|
|
clk => dout[46]~reg0.CLK
|
1013 |
|
|
clk => dout[45]~reg0.CLK
|
1014 |
|
|
clk => dout[44]~reg0.CLK
|
1015 |
|
|
clk => dout[43]~reg0.CLK
|
1016 |
|
|
clk => dout[42]~reg0.CLK
|
1017 |
|
|
clk => dout[41]~reg0.CLK
|
1018 |
|
|
clk => dout[40]~reg0.CLK
|
1019 |
|
|
clk => dout[39]~reg0.CLK
|
1020 |
|
|
clk => dout[38]~reg0.CLK
|
1021 |
|
|
clk => dout[37]~reg0.CLK
|
1022 |
|
|
clk => dout[36]~reg0.CLK
|
1023 |
|
|
clk => dout[35]~reg0.CLK
|
1024 |
|
|
clk => dout[34]~reg0.CLK
|
1025 |
|
|
clk => dout[33]~reg0.CLK
|
1026 |
|
|
clk => dout[32]~reg0.CLK
|
1027 |
|
|
clk => dout[31]~reg0.CLK
|
1028 |
|
|
clk => dout[30]~reg0.CLK
|
1029 |
|
|
clk => dout[29]~reg0.CLK
|
1030 |
|
|
clk => dout[28]~reg0.CLK
|
1031 |
|
|
clk => dout[27]~reg0.CLK
|
1032 |
|
|
clk => dout[26]~reg0.CLK
|
1033 |
|
|
clk => dout[25]~reg0.CLK
|
1034 |
|
|
clk => dout[24]~reg0.CLK
|
1035 |
|
|
clk => dout[23]~reg0.CLK
|
1036 |
|
|
clk => dout[22]~reg0.CLK
|
1037 |
|
|
clk => dout[21]~reg0.CLK
|
1038 |
|
|
clk => dout[20]~reg0.CLK
|
1039 |
|
|
clk => dout[19]~reg0.CLK
|
1040 |
|
|
clk => dout[18]~reg0.CLK
|
1041 |
|
|
clk => dout[17]~reg0.CLK
|
1042 |
|
|
clk => dout[16]~reg0.CLK
|
1043 |
|
|
clk => dout[15]~reg0.CLK
|
1044 |
|
|
clk => dout[14]~reg0.CLK
|
1045 |
|
|
clk => dout[13]~reg0.CLK
|
1046 |
|
|
clk => dout[12]~reg0.CLK
|
1047 |
|
|
clk => dout[11]~reg0.CLK
|
1048 |
|
|
clk => dout[10]~reg0.CLK
|
1049 |
|
|
clk => dout[9]~reg0.CLK
|
1050 |
|
|
clk => dout[8]~reg0.CLK
|
1051 |
|
|
clk => dout[7]~reg0.CLK
|
1052 |
|
|
clk => dout[6]~reg0.CLK
|
1053 |
|
|
clk => dout[5]~reg0.CLK
|
1054 |
|
|
clk => dout[4]~reg0.CLK
|
1055 |
|
|
clk => dout[3]~reg0.CLK
|
1056 |
|
|
clk => dout[2]~reg0.CLK
|
1057 |
|
|
clk => dout[1]~reg0.CLK
|
1058 |
|
|
clk => dout[0]~reg0.CLK
|
1059 |
|
|
clk => rd_ptr[7].CLK
|
1060 |
|
|
clk => rd_ptr[6].CLK
|
1061 |
|
|
clk => rd_ptr[5].CLK
|
1062 |
|
|
clk => rd_ptr[4].CLK
|
1063 |
|
|
clk => rd_ptr[3].CLK
|
1064 |
|
|
clk => rd_ptr[2].CLK
|
1065 |
|
|
clk => rd_ptr[1].CLK
|
1066 |
|
|
clk => rd_ptr[0].CLK
|
1067 |
|
|
clk => wr_ptr[7].CLK
|
1068 |
|
|
clk => wr_ptr[6].CLK
|
1069 |
|
|
clk => wr_ptr[5].CLK
|
1070 |
|
|
clk => wr_ptr[4].CLK
|
1071 |
|
|
clk => wr_ptr[3].CLK
|
1072 |
|
|
clk => wr_ptr[2].CLK
|
1073 |
|
|
clk => wr_ptr[1].CLK
|
1074 |
|
|
clk => wr_ptr[0].CLK
|
1075 |
|
|
clk => depth[8].CLK
|
1076 |
|
|
clk => depth[7].CLK
|
1077 |
|
|
clk => depth[6].CLK
|
1078 |
|
|
clk => depth[5].CLK
|
1079 |
|
|
clk => depth[4].CLK
|
1080 |
|
|
clk => depth[3].CLK
|
1081 |
|
|
clk => depth[2].CLK
|
1082 |
|
|
clk => depth[1].CLK
|
1083 |
|
|
clk => depth[0].CLK
|
1084 |
|
|
clk => queue.data_a[0].CLK
|
1085 |
|
|
clk => queue.data_a[1].CLK
|
1086 |
|
|
clk => queue.data_a[2].CLK
|
1087 |
|
|
clk => queue.data_a[3].CLK
|
1088 |
|
|
clk => queue.data_a[4].CLK
|
1089 |
|
|
clk => queue.data_a[5].CLK
|
1090 |
|
|
clk => queue.data_a[6].CLK
|
1091 |
|
|
clk => queue.data_a[7].CLK
|
1092 |
|
|
clk => queue.data_a[8].CLK
|
1093 |
|
|
clk => queue.data_a[9].CLK
|
1094 |
|
|
clk => queue.data_a[10].CLK
|
1095 |
|
|
clk => queue.data_a[11].CLK
|
1096 |
|
|
clk => queue.data_a[12].CLK
|
1097 |
|
|
clk => queue.data_a[13].CLK
|
1098 |
|
|
clk => queue.data_a[14].CLK
|
1099 |
|
|
clk => queue.data_a[15].CLK
|
1100 |
|
|
clk => queue.data_a[16].CLK
|
1101 |
|
|
clk => queue.data_a[17].CLK
|
1102 |
|
|
clk => queue.data_a[18].CLK
|
1103 |
|
|
clk => queue.data_a[19].CLK
|
1104 |
|
|
clk => queue.data_a[20].CLK
|
1105 |
|
|
clk => queue.data_a[21].CLK
|
1106 |
|
|
clk => queue.data_a[22].CLK
|
1107 |
|
|
clk => queue.data_a[23].CLK
|
1108 |
|
|
clk => queue.data_a[24].CLK
|
1109 |
|
|
clk => queue.data_a[25].CLK
|
1110 |
|
|
clk => queue.data_a[26].CLK
|
1111 |
|
|
clk => queue.data_a[27].CLK
|
1112 |
|
|
clk => queue.data_a[28].CLK
|
1113 |
|
|
clk => queue.data_a[29].CLK
|
1114 |
|
|
clk => queue.data_a[30].CLK
|
1115 |
|
|
clk => queue.data_a[31].CLK
|
1116 |
|
|
clk => queue.data_a[32].CLK
|
1117 |
|
|
clk => queue.data_a[33].CLK
|
1118 |
|
|
clk => queue.data_a[34].CLK
|
1119 |
|
|
clk => queue.data_a[35].CLK
|
1120 |
|
|
clk => queue.data_a[36].CLK
|
1121 |
|
|
clk => queue.data_a[37].CLK
|
1122 |
|
|
clk => queue.data_a[38].CLK
|
1123 |
|
|
clk => queue.data_a[39].CLK
|
1124 |
|
|
clk => queue.data_a[40].CLK
|
1125 |
|
|
clk => queue.data_a[41].CLK
|
1126 |
|
|
clk => queue.data_a[42].CLK
|
1127 |
|
|
clk => queue.data_a[43].CLK
|
1128 |
|
|
clk => queue.data_a[44].CLK
|
1129 |
|
|
clk => queue.data_a[45].CLK
|
1130 |
|
|
clk => queue.data_a[46].CLK
|
1131 |
|
|
clk => queue.data_a[47].CLK
|
1132 |
|
|
clk => queue.data_a[48].CLK
|
1133 |
|
|
clk => queue.data_a[49].CLK
|
1134 |
|
|
clk => queue.data_a[50].CLK
|
1135 |
|
|
clk => queue.data_a[51].CLK
|
1136 |
|
|
clk => queue.data_a[52].CLK
|
1137 |
|
|
clk => queue.data_a[53].CLK
|
1138 |
|
|
clk => queue.data_a[54].CLK
|
1139 |
|
|
clk => queue.data_a[55].CLK
|
1140 |
|
|
clk => queue.data_a[56].CLK
|
1141 |
|
|
clk => queue.data_a[57].CLK
|
1142 |
|
|
clk => queue.data_a[58].CLK
|
1143 |
|
|
clk => queue.data_a[59].CLK
|
1144 |
|
|
clk => queue.data_a[60].CLK
|
1145 |
|
|
clk => queue.data_a[61].CLK
|
1146 |
|
|
clk => queue.data_a[62].CLK
|
1147 |
|
|
clk => queue.data_a[63].CLK
|
1148 |
|
|
clk => queue.waddr_a[0].CLK
|
1149 |
|
|
clk => queue.waddr_a[1].CLK
|
1150 |
|
|
clk => queue.waddr_a[2].CLK
|
1151 |
|
|
clk => queue.waddr_a[3].CLK
|
1152 |
|
|
clk => queue.waddr_a[4].CLK
|
1153 |
|
|
clk => queue.waddr_a[5].CLK
|
1154 |
|
|
clk => queue.waddr_a[6].CLK
|
1155 |
|
|
clk => queue.waddr_a[7].CLK
|
1156 |
|
|
clk => always0~0.CLK
|
1157 |
|
|
clk => queue.CLK0
|
1158 |
|
|
|
1159 |
|
|
|
1160 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst
|
1161 |
|
|
clk => valid_address:valid_address_Inst.clk
|
1162 |
|
|
clk => ram_256x48:Aging_Valid_256x48_Inst.clk
|
1163 |
|
|
clk => small_fifo:time_command_Inst.clk
|
1164 |
|
|
clk => small_fifo:WRITE_command_Inst.clk
|
1165 |
|
|
clk => ram_256x48:ram_256x48_Inst.clk
|
1166 |
|
|
clk => ram_256x48:ram_256x48_search_Inst.clk
|
1167 |
|
|
clk => in_mac_no_prt_i[55].CLK
|
1168 |
|
|
clk => in_mac_no_prt_i[54].CLK
|
1169 |
|
|
clk => in_mac_no_prt_i[53].CLK
|
1170 |
|
|
clk => in_mac_no_prt_i[52].CLK
|
1171 |
|
|
clk => in_mac_no_prt_i[51].CLK
|
1172 |
|
|
clk => in_mac_no_prt_i[50].CLK
|
1173 |
|
|
clk => in_mac_no_prt_i[49].CLK
|
1174 |
|
|
clk => in_mac_no_prt_i[48].CLK
|
1175 |
|
|
clk => in_mac_no_prt_i[47].CLK
|
1176 |
|
|
clk => in_mac_no_prt_i[46].CLK
|
1177 |
|
|
clk => in_mac_no_prt_i[45].CLK
|
1178 |
|
|
clk => in_mac_no_prt_i[44].CLK
|
1179 |
|
|
clk => in_mac_no_prt_i[43].CLK
|
1180 |
|
|
clk => in_mac_no_prt_i[42].CLK
|
1181 |
|
|
clk => in_mac_no_prt_i[41].CLK
|
1182 |
|
|
clk => in_mac_no_prt_i[40].CLK
|
1183 |
|
|
clk => in_mac_no_prt_i[39].CLK
|
1184 |
|
|
clk => in_mac_no_prt_i[38].CLK
|
1185 |
|
|
clk => in_mac_no_prt_i[37].CLK
|
1186 |
|
|
clk => in_mac_no_prt_i[36].CLK
|
1187 |
|
|
clk => in_mac_no_prt_i[35].CLK
|
1188 |
|
|
clk => in_mac_no_prt_i[34].CLK
|
1189 |
|
|
clk => in_mac_no_prt_i[33].CLK
|
1190 |
|
|
clk => in_mac_no_prt_i[32].CLK
|
1191 |
|
|
clk => in_mac_no_prt_i[31].CLK
|
1192 |
|
|
clk => in_mac_no_prt_i[30].CLK
|
1193 |
|
|
clk => in_mac_no_prt_i[29].CLK
|
1194 |
|
|
clk => in_mac_no_prt_i[28].CLK
|
1195 |
|
|
clk => in_mac_no_prt_i[27].CLK
|
1196 |
|
|
clk => in_mac_no_prt_i[26].CLK
|
1197 |
|
|
clk => in_mac_no_prt_i[25].CLK
|
1198 |
|
|
clk => in_mac_no_prt_i[24].CLK
|
1199 |
|
|
clk => in_mac_no_prt_i[23].CLK
|
1200 |
|
|
clk => in_mac_no_prt_i[22].CLK
|
1201 |
|
|
clk => in_mac_no_prt_i[21].CLK
|
1202 |
|
|
clk => in_mac_no_prt_i[20].CLK
|
1203 |
|
|
clk => in_mac_no_prt_i[19].CLK
|
1204 |
|
|
clk => in_mac_no_prt_i[18].CLK
|
1205 |
|
|
clk => in_mac_no_prt_i[17].CLK
|
1206 |
|
|
clk => in_mac_no_prt_i[16].CLK
|
1207 |
|
|
clk => in_mac_no_prt_i[15].CLK
|
1208 |
|
|
clk => in_mac_no_prt_i[14].CLK
|
1209 |
|
|
clk => in_mac_no_prt_i[13].CLK
|
1210 |
|
|
clk => in_mac_no_prt_i[12].CLK
|
1211 |
|
|
clk => in_mac_no_prt_i[11].CLK
|
1212 |
|
|
clk => in_mac_no_prt_i[10].CLK
|
1213 |
|
|
clk => in_mac_no_prt_i[9].CLK
|
1214 |
|
|
clk => in_mac_no_prt_i[8].CLK
|
1215 |
|
|
clk => in_mac_no_prt_i[7].CLK
|
1216 |
|
|
clk => in_mac_no_prt_i[6].CLK
|
1217 |
|
|
clk => in_mac_no_prt_i[5].CLK
|
1218 |
|
|
clk => in_mac_no_prt_i[4].CLK
|
1219 |
|
|
clk => in_mac_no_prt_i[3].CLK
|
1220 |
|
|
clk => in_mac_no_prt_i[2].CLK
|
1221 |
|
|
clk => in_mac_no_prt_i[1].CLK
|
1222 |
|
|
clk => in_mac_no_prt_i[0].CLK
|
1223 |
|
|
clk => match_address[9]~reg0.CLK
|
1224 |
|
|
clk => match_address[8]~reg0.CLK
|
1225 |
|
|
clk => match_address[7]~reg0.CLK
|
1226 |
|
|
clk => match_address[6]~reg0.CLK
|
1227 |
|
|
clk => match_address[5]~reg0.CLK
|
1228 |
|
|
clk => match_address[4]~reg0.CLK
|
1229 |
|
|
clk => match_address[3]~reg0.CLK
|
1230 |
|
|
clk => match_address[2]~reg0.CLK
|
1231 |
|
|
clk => match_address[1]~reg0.CLK
|
1232 |
|
|
clk => match_address[0]~reg0.CLK
|
1233 |
|
|
clk => match~reg0.CLK
|
1234 |
|
|
clk => unmatch~reg0.CLK
|
1235 |
|
|
clk => cnt1[9].CLK
|
1236 |
|
|
clk => cnt1[8].CLK
|
1237 |
|
|
clk => cnt1[7].CLK
|
1238 |
|
|
clk => cnt1[6].CLK
|
1239 |
|
|
clk => cnt1[5].CLK
|
1240 |
|
|
clk => cnt1[4].CLK
|
1241 |
|
|
clk => cnt1[3].CLK
|
1242 |
|
|
clk => cnt1[2].CLK
|
1243 |
|
|
clk => cnt1[1].CLK
|
1244 |
|
|
clk => cnt1[0].CLK
|
1245 |
|
|
clk => out_rd_rdy_i.CLK
|
1246 |
|
|
clk => out_rd_rdy~reg0.CLK
|
1247 |
|
|
clk => \process7:cnt1[9].CLK
|
1248 |
|
|
clk => \process7:cnt1[8].CLK
|
1249 |
|
|
clk => \process7:cnt1[7].CLK
|
1250 |
|
|
clk => \process7:cnt1[6].CLK
|
1251 |
|
|
clk => \process7:cnt1[5].CLK
|
1252 |
|
|
clk => \process7:cnt1[4].CLK
|
1253 |
|
|
clk => \process7:cnt1[3].CLK
|
1254 |
|
|
clk => \process7:cnt1[2].CLK
|
1255 |
|
|
clk => \process7:cnt1[1].CLK
|
1256 |
|
|
clk => \process7:cnt1[0].CLK
|
1257 |
|
|
clk => Aging_Timer:Aging_Timer_Inst.clk
|
1258 |
|
|
clk => state~0.IN1
|
1259 |
|
|
clk => state_search~0.IN1
|
1260 |
|
|
reset => valid_address:valid_address_Inst.reset
|
1261 |
|
|
reset => small_fifo:time_command_Inst.reset
|
1262 |
|
|
reset => small_fifo:WRITE_command_Inst.reset
|
1263 |
|
|
reset => Aging_Timer:Aging_Timer_Inst.reset
|
1264 |
|
|
reset => cnt1~49.OUTPUTSELECT
|
1265 |
|
|
reset => cnt1~48.OUTPUTSELECT
|
1266 |
|
|
reset => cnt1~47.OUTPUTSELECT
|
1267 |
|
|
reset => cnt1~46.OUTPUTSELECT
|
1268 |
|
|
reset => cnt1~45.OUTPUTSELECT
|
1269 |
|
|
reset => cnt1~44.OUTPUTSELECT
|
1270 |
|
|
reset => cnt1~43.OUTPUTSELECT
|
1271 |
|
|
reset => cnt1~42.OUTPUTSELECT
|
1272 |
|
|
reset => cnt1~41.OUTPUTSELECT
|
1273 |
|
|
reset => cnt1~40.OUTPUTSELECT
|
1274 |
|
|
reset => cnt1~19.OUTPUTSELECT
|
1275 |
|
|
reset => cnt1~18.OUTPUTSELECT
|
1276 |
|
|
reset => cnt1~17.OUTPUTSELECT
|
1277 |
|
|
reset => cnt1~16.OUTPUTSELECT
|
1278 |
|
|
reset => cnt1~15.OUTPUTSELECT
|
1279 |
|
|
reset => cnt1~14.OUTPUTSELECT
|
1280 |
|
|
reset => cnt1~13.OUTPUTSELECT
|
1281 |
|
|
reset => cnt1~12.OUTPUTSELECT
|
1282 |
|
|
reset => cnt1~11.OUTPUTSELECT
|
1283 |
|
|
reset => cnt1~10.OUTPUTSELECT
|
1284 |
|
|
reset => in_mac_no_prt_i[55].ENA
|
1285 |
|
|
reset => in_mac_no_prt_i[54].ENA
|
1286 |
|
|
reset => in_mac_no_prt_i[53].ENA
|
1287 |
|
|
reset => in_mac_no_prt_i[52].ENA
|
1288 |
|
|
reset => in_mac_no_prt_i[51].ENA
|
1289 |
|
|
reset => in_mac_no_prt_i[50].ENA
|
1290 |
|
|
reset => in_mac_no_prt_i[49].ENA
|
1291 |
|
|
reset => in_mac_no_prt_i[48].ENA
|
1292 |
|
|
reset => in_mac_no_prt_i[47].ENA
|
1293 |
|
|
reset => in_mac_no_prt_i[46].ENA
|
1294 |
|
|
reset => in_mac_no_prt_i[45].ENA
|
1295 |
|
|
reset => in_mac_no_prt_i[44].ENA
|
1296 |
|
|
reset => in_mac_no_prt_i[43].ENA
|
1297 |
|
|
reset => in_mac_no_prt_i[42].ENA
|
1298 |
|
|
reset => in_mac_no_prt_i[41].ENA
|
1299 |
|
|
reset => in_mac_no_prt_i[40].ENA
|
1300 |
|
|
reset => in_mac_no_prt_i[39].ENA
|
1301 |
|
|
reset => in_mac_no_prt_i[38].ENA
|
1302 |
|
|
reset => in_mac_no_prt_i[37].ENA
|
1303 |
|
|
reset => in_mac_no_prt_i[36].ENA
|
1304 |
|
|
reset => in_mac_no_prt_i[35].ENA
|
1305 |
|
|
reset => in_mac_no_prt_i[34].ENA
|
1306 |
|
|
reset => in_mac_no_prt_i[33].ENA
|
1307 |
|
|
reset => in_mac_no_prt_i[32].ENA
|
1308 |
|
|
reset => in_mac_no_prt_i[31].ENA
|
1309 |
|
|
reset => in_mac_no_prt_i[30].ENA
|
1310 |
|
|
reset => in_mac_no_prt_i[29].ENA
|
1311 |
|
|
reset => in_mac_no_prt_i[28].ENA
|
1312 |
|
|
reset => in_mac_no_prt_i[27].ENA
|
1313 |
|
|
reset => in_mac_no_prt_i[26].ENA
|
1314 |
|
|
reset => in_mac_no_prt_i[25].ENA
|
1315 |
|
|
reset => in_mac_no_prt_i[24].ENA
|
1316 |
|
|
reset => in_mac_no_prt_i[23].ENA
|
1317 |
|
|
reset => in_mac_no_prt_i[22].ENA
|
1318 |
|
|
reset => in_mac_no_prt_i[21].ENA
|
1319 |
|
|
reset => in_mac_no_prt_i[20].ENA
|
1320 |
|
|
reset => in_mac_no_prt_i[19].ENA
|
1321 |
|
|
reset => in_mac_no_prt_i[18].ENA
|
1322 |
|
|
reset => in_mac_no_prt_i[17].ENA
|
1323 |
|
|
reset => in_mac_no_prt_i[16].ENA
|
1324 |
|
|
reset => in_mac_no_prt_i[15].ENA
|
1325 |
|
|
reset => in_mac_no_prt_i[14].ENA
|
1326 |
|
|
reset => in_mac_no_prt_i[13].ENA
|
1327 |
|
|
reset => in_mac_no_prt_i[12].ENA
|
1328 |
|
|
reset => in_mac_no_prt_i[11].ENA
|
1329 |
|
|
reset => in_mac_no_prt_i[10].ENA
|
1330 |
|
|
reset => in_mac_no_prt_i[9].ENA
|
1331 |
|
|
reset => in_mac_no_prt_i[8].ENA
|
1332 |
|
|
reset => in_mac_no_prt_i[7].ENA
|
1333 |
|
|
reset => in_mac_no_prt_i[6].ENA
|
1334 |
|
|
reset => in_mac_no_prt_i[5].ENA
|
1335 |
|
|
reset => in_mac_no_prt_i[4].ENA
|
1336 |
|
|
reset => in_mac_no_prt_i[3].ENA
|
1337 |
|
|
reset => in_mac_no_prt_i[2].ENA
|
1338 |
|
|
reset => in_mac_no_prt_i[1].ENA
|
1339 |
|
|
reset => in_mac_no_prt_i[0].ENA
|
1340 |
|
|
reset => match_address[9]~reg0.ENA
|
1341 |
|
|
reset => match_address[8]~reg0.ENA
|
1342 |
|
|
reset => match_address[7]~reg0.ENA
|
1343 |
|
|
reset => match_address[6]~reg0.ENA
|
1344 |
|
|
reset => match_address[5]~reg0.ENA
|
1345 |
|
|
reset => match_address[4]~reg0.ENA
|
1346 |
|
|
reset => match_address[3]~reg0.ENA
|
1347 |
|
|
reset => match_address[2]~reg0.ENA
|
1348 |
|
|
reset => match_address[1]~reg0.ENA
|
1349 |
|
|
reset => match_address[0]~reg0.ENA
|
1350 |
|
|
reset => out_rd_rdy_i.ENA
|
1351 |
|
|
reset => out_rd_rdy~reg0.ENA
|
1352 |
|
|
reset => state~1.IN1
|
1353 |
|
|
reset => state_search~1.IN1
|
1354 |
|
|
in_mac_no_prt[0] => ram_256x48:ram_256x48_Inst.data[0]
|
1355 |
|
|
in_mac_no_prt[1] => ram_256x48:ram_256x48_Inst.data[1]
|
1356 |
|
|
in_mac_no_prt[2] => ram_256x48:ram_256x48_Inst.data[2]
|
1357 |
|
|
in_mac_no_prt[3] => ram_256x48:ram_256x48_Inst.data[3]
|
1358 |
|
|
in_mac_no_prt[4] => ram_256x48:ram_256x48_Inst.data[4]
|
1359 |
|
|
in_mac_no_prt[5] => ram_256x48:ram_256x48_Inst.data[5]
|
1360 |
|
|
in_mac_no_prt[6] => ram_256x48:ram_256x48_Inst.data[6]
|
1361 |
|
|
in_mac_no_prt[7] => ram_256x48:ram_256x48_Inst.data[7]
|
1362 |
|
|
in_mac_no_prt[8] => ram_256x48:ram_256x48_search_Inst.data[0]
|
1363 |
|
|
in_mac_no_prt[8] => in_mac_no_prt_i~55.DATAB
|
1364 |
|
|
in_mac_no_prt[9] => ram_256x48:ram_256x48_search_Inst.data[1]
|
1365 |
|
|
in_mac_no_prt[9] => in_mac_no_prt_i~54.DATAB
|
1366 |
|
|
in_mac_no_prt[10] => ram_256x48:ram_256x48_search_Inst.data[2]
|
1367 |
|
|
in_mac_no_prt[10] => in_mac_no_prt_i~53.DATAB
|
1368 |
|
|
in_mac_no_prt[11] => ram_256x48:ram_256x48_search_Inst.data[3]
|
1369 |
|
|
in_mac_no_prt[11] => in_mac_no_prt_i~52.DATAB
|
1370 |
|
|
in_mac_no_prt[12] => ram_256x48:ram_256x48_search_Inst.data[4]
|
1371 |
|
|
in_mac_no_prt[12] => in_mac_no_prt_i~51.DATAB
|
1372 |
|
|
in_mac_no_prt[13] => ram_256x48:ram_256x48_search_Inst.data[5]
|
1373 |
|
|
in_mac_no_prt[13] => in_mac_no_prt_i~50.DATAB
|
1374 |
|
|
in_mac_no_prt[14] => ram_256x48:ram_256x48_search_Inst.data[6]
|
1375 |
|
|
in_mac_no_prt[14] => in_mac_no_prt_i~49.DATAB
|
1376 |
|
|
in_mac_no_prt[15] => ram_256x48:ram_256x48_search_Inst.data[7]
|
1377 |
|
|
in_mac_no_prt[15] => in_mac_no_prt_i~48.DATAB
|
1378 |
|
|
in_mac_no_prt[16] => ram_256x48:ram_256x48_Inst.data[8]
|
1379 |
|
|
in_mac_no_prt[16] => ram_256x48:ram_256x48_search_Inst.data[8]
|
1380 |
|
|
in_mac_no_prt[16] => in_mac_no_prt_i~47.DATAB
|
1381 |
|
|
in_mac_no_prt[17] => ram_256x48:ram_256x48_Inst.data[9]
|
1382 |
|
|
in_mac_no_prt[17] => ram_256x48:ram_256x48_search_Inst.data[9]
|
1383 |
|
|
in_mac_no_prt[17] => in_mac_no_prt_i~46.DATAB
|
1384 |
|
|
in_mac_no_prt[18] => ram_256x48:ram_256x48_Inst.data[10]
|
1385 |
|
|
in_mac_no_prt[18] => ram_256x48:ram_256x48_search_Inst.data[10]
|
1386 |
|
|
in_mac_no_prt[18] => in_mac_no_prt_i~45.DATAB
|
1387 |
|
|
in_mac_no_prt[19] => ram_256x48:ram_256x48_Inst.data[11]
|
1388 |
|
|
in_mac_no_prt[19] => ram_256x48:ram_256x48_search_Inst.data[11]
|
1389 |
|
|
in_mac_no_prt[19] => in_mac_no_prt_i~44.DATAB
|
1390 |
|
|
in_mac_no_prt[20] => ram_256x48:ram_256x48_Inst.data[12]
|
1391 |
|
|
in_mac_no_prt[20] => ram_256x48:ram_256x48_search_Inst.data[12]
|
1392 |
|
|
in_mac_no_prt[20] => in_mac_no_prt_i~43.DATAB
|
1393 |
|
|
in_mac_no_prt[21] => ram_256x48:ram_256x48_Inst.data[13]
|
1394 |
|
|
in_mac_no_prt[21] => ram_256x48:ram_256x48_search_Inst.data[13]
|
1395 |
|
|
in_mac_no_prt[21] => in_mac_no_prt_i~42.DATAB
|
1396 |
|
|
in_mac_no_prt[22] => ram_256x48:ram_256x48_Inst.data[14]
|
1397 |
|
|
in_mac_no_prt[22] => ram_256x48:ram_256x48_search_Inst.data[14]
|
1398 |
|
|
in_mac_no_prt[22] => in_mac_no_prt_i~41.DATAB
|
1399 |
|
|
in_mac_no_prt[23] => ram_256x48:ram_256x48_Inst.data[15]
|
1400 |
|
|
in_mac_no_prt[23] => ram_256x48:ram_256x48_search_Inst.data[15]
|
1401 |
|
|
in_mac_no_prt[23] => in_mac_no_prt_i~40.DATAB
|
1402 |
|
|
in_mac_no_prt[24] => ram_256x48:ram_256x48_Inst.data[16]
|
1403 |
|
|
in_mac_no_prt[24] => ram_256x48:ram_256x48_search_Inst.data[16]
|
1404 |
|
|
in_mac_no_prt[24] => in_mac_no_prt_i~39.DATAB
|
1405 |
|
|
in_mac_no_prt[25] => ram_256x48:ram_256x48_Inst.data[17]
|
1406 |
|
|
in_mac_no_prt[25] => ram_256x48:ram_256x48_search_Inst.data[17]
|
1407 |
|
|
in_mac_no_prt[25] => in_mac_no_prt_i~38.DATAB
|
1408 |
|
|
in_mac_no_prt[26] => ram_256x48:ram_256x48_Inst.data[18]
|
1409 |
|
|
in_mac_no_prt[26] => ram_256x48:ram_256x48_search_Inst.data[18]
|
1410 |
|
|
in_mac_no_prt[26] => in_mac_no_prt_i~37.DATAB
|
1411 |
|
|
in_mac_no_prt[27] => ram_256x48:ram_256x48_Inst.data[19]
|
1412 |
|
|
in_mac_no_prt[27] => ram_256x48:ram_256x48_search_Inst.data[19]
|
1413 |
|
|
in_mac_no_prt[27] => in_mac_no_prt_i~36.DATAB
|
1414 |
|
|
in_mac_no_prt[28] => ram_256x48:ram_256x48_Inst.data[20]
|
1415 |
|
|
in_mac_no_prt[28] => ram_256x48:ram_256x48_search_Inst.data[20]
|
1416 |
|
|
in_mac_no_prt[28] => in_mac_no_prt_i~35.DATAB
|
1417 |
|
|
in_mac_no_prt[29] => ram_256x48:ram_256x48_Inst.data[21]
|
1418 |
|
|
in_mac_no_prt[29] => ram_256x48:ram_256x48_search_Inst.data[21]
|
1419 |
|
|
in_mac_no_prt[29] => in_mac_no_prt_i~34.DATAB
|
1420 |
|
|
in_mac_no_prt[30] => ram_256x48:ram_256x48_Inst.data[22]
|
1421 |
|
|
in_mac_no_prt[30] => ram_256x48:ram_256x48_search_Inst.data[22]
|
1422 |
|
|
in_mac_no_prt[30] => in_mac_no_prt_i~33.DATAB
|
1423 |
|
|
in_mac_no_prt[31] => ram_256x48:ram_256x48_Inst.data[23]
|
1424 |
|
|
in_mac_no_prt[31] => ram_256x48:ram_256x48_search_Inst.data[23]
|
1425 |
|
|
in_mac_no_prt[31] => in_mac_no_prt_i~32.DATAB
|
1426 |
|
|
in_mac_no_prt[32] => ram_256x48:ram_256x48_Inst.data[24]
|
1427 |
|
|
in_mac_no_prt[32] => ram_256x48:ram_256x48_search_Inst.data[24]
|
1428 |
|
|
in_mac_no_prt[32] => in_mac_no_prt_i~31.DATAB
|
1429 |
|
|
in_mac_no_prt[33] => ram_256x48:ram_256x48_Inst.data[25]
|
1430 |
|
|
in_mac_no_prt[33] => ram_256x48:ram_256x48_search_Inst.data[25]
|
1431 |
|
|
in_mac_no_prt[33] => in_mac_no_prt_i~30.DATAB
|
1432 |
|
|
in_mac_no_prt[34] => ram_256x48:ram_256x48_Inst.data[26]
|
1433 |
|
|
in_mac_no_prt[34] => ram_256x48:ram_256x48_search_Inst.data[26]
|
1434 |
|
|
in_mac_no_prt[34] => in_mac_no_prt_i~29.DATAB
|
1435 |
|
|
in_mac_no_prt[35] => ram_256x48:ram_256x48_Inst.data[27]
|
1436 |
|
|
in_mac_no_prt[35] => ram_256x48:ram_256x48_search_Inst.data[27]
|
1437 |
|
|
in_mac_no_prt[35] => in_mac_no_prt_i~28.DATAB
|
1438 |
|
|
in_mac_no_prt[36] => ram_256x48:ram_256x48_Inst.data[28]
|
1439 |
|
|
in_mac_no_prt[36] => ram_256x48:ram_256x48_search_Inst.data[28]
|
1440 |
|
|
in_mac_no_prt[36] => in_mac_no_prt_i~27.DATAB
|
1441 |
|
|
in_mac_no_prt[37] => ram_256x48:ram_256x48_Inst.data[29]
|
1442 |
|
|
in_mac_no_prt[37] => ram_256x48:ram_256x48_search_Inst.data[29]
|
1443 |
|
|
in_mac_no_prt[37] => in_mac_no_prt_i~26.DATAB
|
1444 |
|
|
in_mac_no_prt[38] => ram_256x48:ram_256x48_Inst.data[30]
|
1445 |
|
|
in_mac_no_prt[38] => ram_256x48:ram_256x48_search_Inst.data[30]
|
1446 |
|
|
in_mac_no_prt[38] => in_mac_no_prt_i~25.DATAB
|
1447 |
|
|
in_mac_no_prt[39] => ram_256x48:ram_256x48_Inst.data[31]
|
1448 |
|
|
in_mac_no_prt[39] => ram_256x48:ram_256x48_search_Inst.data[31]
|
1449 |
|
|
in_mac_no_prt[39] => in_mac_no_prt_i~24.DATAB
|
1450 |
|
|
in_mac_no_prt[40] => ram_256x48:ram_256x48_Inst.data[32]
|
1451 |
|
|
in_mac_no_prt[40] => ram_256x48:ram_256x48_search_Inst.data[32]
|
1452 |
|
|
in_mac_no_prt[40] => in_mac_no_prt_i~23.DATAB
|
1453 |
|
|
in_mac_no_prt[41] => ram_256x48:ram_256x48_Inst.data[33]
|
1454 |
|
|
in_mac_no_prt[41] => ram_256x48:ram_256x48_search_Inst.data[33]
|
1455 |
|
|
in_mac_no_prt[41] => in_mac_no_prt_i~22.DATAB
|
1456 |
|
|
in_mac_no_prt[42] => ram_256x48:ram_256x48_Inst.data[34]
|
1457 |
|
|
in_mac_no_prt[42] => ram_256x48:ram_256x48_search_Inst.data[34]
|
1458 |
|
|
in_mac_no_prt[42] => in_mac_no_prt_i~21.DATAB
|
1459 |
|
|
in_mac_no_prt[43] => ram_256x48:ram_256x48_Inst.data[35]
|
1460 |
|
|
in_mac_no_prt[43] => ram_256x48:ram_256x48_search_Inst.data[35]
|
1461 |
|
|
in_mac_no_prt[43] => in_mac_no_prt_i~20.DATAB
|
1462 |
|
|
in_mac_no_prt[44] => ram_256x48:ram_256x48_Inst.data[36]
|
1463 |
|
|
in_mac_no_prt[44] => ram_256x48:ram_256x48_search_Inst.data[36]
|
1464 |
|
|
in_mac_no_prt[44] => in_mac_no_prt_i~19.DATAB
|
1465 |
|
|
in_mac_no_prt[45] => ram_256x48:ram_256x48_Inst.data[37]
|
1466 |
|
|
in_mac_no_prt[45] => ram_256x48:ram_256x48_search_Inst.data[37]
|
1467 |
|
|
in_mac_no_prt[45] => in_mac_no_prt_i~18.DATAB
|
1468 |
|
|
in_mac_no_prt[46] => ram_256x48:ram_256x48_Inst.data[38]
|
1469 |
|
|
in_mac_no_prt[46] => ram_256x48:ram_256x48_search_Inst.data[38]
|
1470 |
|
|
in_mac_no_prt[46] => in_mac_no_prt_i~17.DATAB
|
1471 |
|
|
in_mac_no_prt[47] => ram_256x48:ram_256x48_Inst.data[39]
|
1472 |
|
|
in_mac_no_prt[47] => ram_256x48:ram_256x48_search_Inst.data[39]
|
1473 |
|
|
in_mac_no_prt[47] => in_mac_no_prt_i~16.DATAB
|
1474 |
|
|
in_mac_no_prt[48] => ram_256x48:ram_256x48_Inst.data[40]
|
1475 |
|
|
in_mac_no_prt[48] => ram_256x48:ram_256x48_search_Inst.data[40]
|
1476 |
|
|
in_mac_no_prt[48] => in_mac_no_prt_i~15.DATAB
|
1477 |
|
|
in_mac_no_prt[49] => ram_256x48:ram_256x48_Inst.data[41]
|
1478 |
|
|
in_mac_no_prt[49] => ram_256x48:ram_256x48_search_Inst.data[41]
|
1479 |
|
|
in_mac_no_prt[49] => in_mac_no_prt_i~14.DATAB
|
1480 |
|
|
in_mac_no_prt[50] => ram_256x48:ram_256x48_Inst.data[42]
|
1481 |
|
|
in_mac_no_prt[50] => ram_256x48:ram_256x48_search_Inst.data[42]
|
1482 |
|
|
in_mac_no_prt[50] => in_mac_no_prt_i~13.DATAB
|
1483 |
|
|
in_mac_no_prt[51] => ram_256x48:ram_256x48_Inst.data[43]
|
1484 |
|
|
in_mac_no_prt[51] => ram_256x48:ram_256x48_search_Inst.data[43]
|
1485 |
|
|
in_mac_no_prt[51] => in_mac_no_prt_i~12.DATAB
|
1486 |
|
|
in_mac_no_prt[52] => ram_256x48:ram_256x48_Inst.data[44]
|
1487 |
|
|
in_mac_no_prt[52] => ram_256x48:ram_256x48_search_Inst.data[44]
|
1488 |
|
|
in_mac_no_prt[52] => in_mac_no_prt_i~11.DATAB
|
1489 |
|
|
in_mac_no_prt[53] => ram_256x48:ram_256x48_Inst.data[45]
|
1490 |
|
|
in_mac_no_prt[53] => ram_256x48:ram_256x48_search_Inst.data[45]
|
1491 |
|
|
in_mac_no_prt[53] => in_mac_no_prt_i~10.DATAB
|
1492 |
|
|
in_mac_no_prt[54] => ram_256x48:ram_256x48_Inst.data[46]
|
1493 |
|
|
in_mac_no_prt[54] => ram_256x48:ram_256x48_search_Inst.data[46]
|
1494 |
|
|
in_mac_no_prt[54] => in_mac_no_prt_i~9.DATAB
|
1495 |
|
|
in_mac_no_prt[55] => ram_256x48:ram_256x48_Inst.data[47]
|
1496 |
|
|
in_mac_no_prt[55] => ram_256x48:ram_256x48_search_Inst.data[47]
|
1497 |
|
|
in_mac_no_prt[55] => in_mac_no_prt_i~8.DATAB
|
1498 |
|
|
in_mac_no_prt[56] => ram_256x48:ram_256x48_Inst.data[48]
|
1499 |
|
|
in_mac_no_prt[56] => ram_256x48:ram_256x48_search_Inst.data[48]
|
1500 |
|
|
in_mac_no_prt[56] => in_mac_no_prt_i~7.DATAB
|
1501 |
|
|
in_mac_no_prt[57] => ram_256x48:ram_256x48_Inst.data[49]
|
1502 |
|
|
in_mac_no_prt[57] => ram_256x48:ram_256x48_search_Inst.data[49]
|
1503 |
|
|
in_mac_no_prt[57] => in_mac_no_prt_i~6.DATAB
|
1504 |
|
|
in_mac_no_prt[58] => ram_256x48:ram_256x48_Inst.data[50]
|
1505 |
|
|
in_mac_no_prt[58] => ram_256x48:ram_256x48_search_Inst.data[50]
|
1506 |
|
|
in_mac_no_prt[58] => in_mac_no_prt_i~5.DATAB
|
1507 |
|
|
in_mac_no_prt[59] => ram_256x48:ram_256x48_Inst.data[51]
|
1508 |
|
|
in_mac_no_prt[59] => ram_256x48:ram_256x48_search_Inst.data[51]
|
1509 |
|
|
in_mac_no_prt[59] => in_mac_no_prt_i~4.DATAB
|
1510 |
|
|
in_mac_no_prt[60] => ram_256x48:ram_256x48_Inst.data[52]
|
1511 |
|
|
in_mac_no_prt[60] => ram_256x48:ram_256x48_search_Inst.data[52]
|
1512 |
|
|
in_mac_no_prt[60] => in_mac_no_prt_i~3.DATAB
|
1513 |
|
|
in_mac_no_prt[61] => ram_256x48:ram_256x48_Inst.data[53]
|
1514 |
|
|
in_mac_no_prt[61] => ram_256x48:ram_256x48_search_Inst.data[53]
|
1515 |
|
|
in_mac_no_prt[61] => in_mac_no_prt_i~2.DATAB
|
1516 |
|
|
in_mac_no_prt[62] => ram_256x48:ram_256x48_Inst.data[54]
|
1517 |
|
|
in_mac_no_prt[62] => ram_256x48:ram_256x48_search_Inst.data[54]
|
1518 |
|
|
in_mac_no_prt[62] => in_mac_no_prt_i~1.DATAB
|
1519 |
|
|
in_mac_no_prt[63] => ram_256x48:ram_256x48_Inst.data[55]
|
1520 |
|
|
in_mac_no_prt[63] => ram_256x48:ram_256x48_search_Inst.data[55]
|
1521 |
|
|
in_mac_no_prt[63] => in_mac_no_prt_i~0.DATAB
|
1522 |
|
|
in_address[0] => small_fifo:WRITE_command_Inst.din[0]
|
1523 |
|
|
in_address[0] => ram_256x48:ram_256x48_Inst.waddr[0]
|
1524 |
|
|
in_address[0] => ram_256x48:ram_256x48_search_Inst.waddr[0]
|
1525 |
|
|
in_address[1] => small_fifo:WRITE_command_Inst.din[1]
|
1526 |
|
|
in_address[1] => ram_256x48:ram_256x48_Inst.waddr[1]
|
1527 |
|
|
in_address[1] => ram_256x48:ram_256x48_search_Inst.waddr[1]
|
1528 |
|
|
in_address[2] => small_fifo:WRITE_command_Inst.din[2]
|
1529 |
|
|
in_address[2] => ram_256x48:ram_256x48_Inst.waddr[2]
|
1530 |
|
|
in_address[2] => ram_256x48:ram_256x48_search_Inst.waddr[2]
|
1531 |
|
|
in_address[3] => small_fifo:WRITE_command_Inst.din[3]
|
1532 |
|
|
in_address[3] => ram_256x48:ram_256x48_Inst.waddr[3]
|
1533 |
|
|
in_address[3] => ram_256x48:ram_256x48_search_Inst.waddr[3]
|
1534 |
|
|
in_address[4] => small_fifo:WRITE_command_Inst.din[4]
|
1535 |
|
|
in_address[4] => ram_256x48:ram_256x48_Inst.waddr[4]
|
1536 |
|
|
in_address[4] => ram_256x48:ram_256x48_search_Inst.waddr[4]
|
1537 |
|
|
in_address[5] => small_fifo:WRITE_command_Inst.din[5]
|
1538 |
|
|
in_address[5] => ram_256x48:ram_256x48_Inst.waddr[5]
|
1539 |
|
|
in_address[5] => ram_256x48:ram_256x48_search_Inst.waddr[5]
|
1540 |
|
|
in_address[6] => small_fifo:WRITE_command_Inst.din[6]
|
1541 |
|
|
in_address[6] => ram_256x48:ram_256x48_Inst.waddr[6]
|
1542 |
|
|
in_address[6] => ram_256x48:ram_256x48_search_Inst.waddr[6]
|
1543 |
|
|
in_address[7] => small_fifo:WRITE_command_Inst.din[7]
|
1544 |
|
|
in_address[7] => ram_256x48:ram_256x48_Inst.waddr[7]
|
1545 |
|
|
in_address[7] => ram_256x48:ram_256x48_search_Inst.waddr[7]
|
1546 |
|
|
in_address[8] => small_fifo:WRITE_command_Inst.din[8]
|
1547 |
|
|
in_address[8] => ram_256x48:ram_256x48_Inst.waddr[8]
|
1548 |
|
|
in_address[8] => ram_256x48:ram_256x48_search_Inst.waddr[8]
|
1549 |
|
|
in_address[9] => small_fifo:WRITE_command_Inst.din[9]
|
1550 |
|
|
in_address[9] => ram_256x48:ram_256x48_Inst.waddr[9]
|
1551 |
|
|
in_address[9] => ram_256x48:ram_256x48_search_Inst.waddr[9]
|
1552 |
|
|
in_wr => small_fifo:WRITE_command_Inst.wr_en
|
1553 |
|
|
in_wr => ram_256x48:ram_256x48_Inst.we
|
1554 |
|
|
in_wr => ram_256x48:ram_256x48_search_Inst.we
|
1555 |
|
|
in_check => cnt1~9.OUTPUTSELECT
|
1556 |
|
|
in_check => cnt1~8.OUTPUTSELECT
|
1557 |
|
|
in_check => cnt1~7.OUTPUTSELECT
|
1558 |
|
|
in_check => cnt1~6.OUTPUTSELECT
|
1559 |
|
|
in_check => cnt1~5.OUTPUTSELECT
|
1560 |
|
|
in_check => cnt1~4.OUTPUTSELECT
|
1561 |
|
|
in_check => cnt1~3.OUTPUTSELECT
|
1562 |
|
|
in_check => cnt1~2.OUTPUTSELECT
|
1563 |
|
|
in_check => cnt1~1.OUTPUTSELECT
|
1564 |
|
|
in_check => cnt1~0.OUTPUTSELECT
|
1565 |
|
|
in_check => state_next_search~3.OUTPUTSELECT
|
1566 |
|
|
in_check => state_next_search~2.OUTPUTSELECT
|
1567 |
|
|
in_check => state_next_search~1.OUTPUTSELECT
|
1568 |
|
|
in_check => state_next_search~0.OUTPUTSELECT
|
1569 |
|
|
in_check => in_mac_no_prt_i~55.OUTPUTSELECT
|
1570 |
|
|
in_check => in_mac_no_prt_i~54.OUTPUTSELECT
|
1571 |
|
|
in_check => in_mac_no_prt_i~53.OUTPUTSELECT
|
1572 |
|
|
in_check => in_mac_no_prt_i~52.OUTPUTSELECT
|
1573 |
|
|
in_check => in_mac_no_prt_i~51.OUTPUTSELECT
|
1574 |
|
|
in_check => in_mac_no_prt_i~50.OUTPUTSELECT
|
1575 |
|
|
in_check => in_mac_no_prt_i~49.OUTPUTSELECT
|
1576 |
|
|
in_check => in_mac_no_prt_i~48.OUTPUTSELECT
|
1577 |
|
|
in_check => in_mac_no_prt_i~47.OUTPUTSELECT
|
1578 |
|
|
in_check => in_mac_no_prt_i~46.OUTPUTSELECT
|
1579 |
|
|
in_check => in_mac_no_prt_i~45.OUTPUTSELECT
|
1580 |
|
|
in_check => in_mac_no_prt_i~44.OUTPUTSELECT
|
1581 |
|
|
in_check => in_mac_no_prt_i~43.OUTPUTSELECT
|
1582 |
|
|
in_check => in_mac_no_prt_i~42.OUTPUTSELECT
|
1583 |
|
|
in_check => in_mac_no_prt_i~41.OUTPUTSELECT
|
1584 |
|
|
in_check => in_mac_no_prt_i~40.OUTPUTSELECT
|
1585 |
|
|
in_check => in_mac_no_prt_i~39.OUTPUTSELECT
|
1586 |
|
|
in_check => in_mac_no_prt_i~38.OUTPUTSELECT
|
1587 |
|
|
in_check => in_mac_no_prt_i~37.OUTPUTSELECT
|
1588 |
|
|
in_check => in_mac_no_prt_i~36.OUTPUTSELECT
|
1589 |
|
|
in_check => in_mac_no_prt_i~35.OUTPUTSELECT
|
1590 |
|
|
in_check => in_mac_no_prt_i~34.OUTPUTSELECT
|
1591 |
|
|
in_check => in_mac_no_prt_i~33.OUTPUTSELECT
|
1592 |
|
|
in_check => in_mac_no_prt_i~32.OUTPUTSELECT
|
1593 |
|
|
in_check => in_mac_no_prt_i~31.OUTPUTSELECT
|
1594 |
|
|
in_check => in_mac_no_prt_i~30.OUTPUTSELECT
|
1595 |
|
|
in_check => in_mac_no_prt_i~29.OUTPUTSELECT
|
1596 |
|
|
in_check => in_mac_no_prt_i~28.OUTPUTSELECT
|
1597 |
|
|
in_check => in_mac_no_prt_i~27.OUTPUTSELECT
|
1598 |
|
|
in_check => in_mac_no_prt_i~26.OUTPUTSELECT
|
1599 |
|
|
in_check => in_mac_no_prt_i~25.OUTPUTSELECT
|
1600 |
|
|
in_check => in_mac_no_prt_i~24.OUTPUTSELECT
|
1601 |
|
|
in_check => in_mac_no_prt_i~23.OUTPUTSELECT
|
1602 |
|
|
in_check => in_mac_no_prt_i~22.OUTPUTSELECT
|
1603 |
|
|
in_check => in_mac_no_prt_i~21.OUTPUTSELECT
|
1604 |
|
|
in_check => in_mac_no_prt_i~20.OUTPUTSELECT
|
1605 |
|
|
in_check => in_mac_no_prt_i~19.OUTPUTSELECT
|
1606 |
|
|
in_check => in_mac_no_prt_i~18.OUTPUTSELECT
|
1607 |
|
|
in_check => in_mac_no_prt_i~17.OUTPUTSELECT
|
1608 |
|
|
in_check => in_mac_no_prt_i~16.OUTPUTSELECT
|
1609 |
|
|
in_check => in_mac_no_prt_i~15.OUTPUTSELECT
|
1610 |
|
|
in_check => in_mac_no_prt_i~14.OUTPUTSELECT
|
1611 |
|
|
in_check => in_mac_no_prt_i~13.OUTPUTSELECT
|
1612 |
|
|
in_check => in_mac_no_prt_i~12.OUTPUTSELECT
|
1613 |
|
|
in_check => in_mac_no_prt_i~11.OUTPUTSELECT
|
1614 |
|
|
in_check => in_mac_no_prt_i~10.OUTPUTSELECT
|
1615 |
|
|
in_check => in_mac_no_prt_i~9.OUTPUTSELECT
|
1616 |
|
|
in_check => in_mac_no_prt_i~8.OUTPUTSELECT
|
1617 |
|
|
in_check => in_mac_no_prt_i~7.OUTPUTSELECT
|
1618 |
|
|
in_check => in_mac_no_prt_i~6.OUTPUTSELECT
|
1619 |
|
|
in_check => in_mac_no_prt_i~5.OUTPUTSELECT
|
1620 |
|
|
in_check => in_mac_no_prt_i~4.OUTPUTSELECT
|
1621 |
|
|
in_check => in_mac_no_prt_i~3.OUTPUTSELECT
|
1622 |
|
|
in_check => in_mac_no_prt_i~2.OUTPUTSELECT
|
1623 |
|
|
in_check => in_mac_no_prt_i~1.OUTPUTSELECT
|
1624 |
|
|
in_check => in_mac_no_prt_i~0.OUTPUTSELECT
|
1625 |
|
|
match_address[0] <= match_address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1626 |
|
|
match_address[1] <= match_address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1627 |
|
|
match_address[2] <= match_address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1628 |
|
|
match_address[3] <= match_address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1629 |
|
|
match_address[4] <= match_address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1630 |
|
|
match_address[5] <= match_address[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1631 |
|
|
match_address[6] <= match_address[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1632 |
|
|
match_address[7] <= match_address[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1633 |
|
|
match_address[8] <= match_address[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1634 |
|
|
match_address[9] <= match_address[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1635 |
|
|
match <= match~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1636 |
|
|
unmatch <= unmatch~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1637 |
|
|
in_rd => valid_address:valid_address_Inst.in_rd
|
1638 |
|
|
in_key[0] => valid_address:valid_address_Inst.in_key[0]
|
1639 |
|
|
in_key[1] => valid_address:valid_address_Inst.in_key[1]
|
1640 |
|
|
in_key[2] => valid_address:valid_address_Inst.in_key[2]
|
1641 |
|
|
in_key[3] => valid_address:valid_address_Inst.in_key[3]
|
1642 |
|
|
in_key[4] => valid_address:valid_address_Inst.in_key[4]
|
1643 |
|
|
in_key[5] => valid_address:valid_address_Inst.in_key[5]
|
1644 |
|
|
in_key[6] => valid_address:valid_address_Inst.in_key[6]
|
1645 |
|
|
in_key[7] => valid_address:valid_address_Inst.in_key[7]
|
1646 |
|
|
in_key[8] => valid_address:valid_address_Inst.in_key[8]
|
1647 |
|
|
in_key[9] => valid_address:valid_address_Inst.in_key[9]
|
1648 |
|
|
last_address[0] => Equal2.IN11
|
1649 |
|
|
last_address[0] => Equal1.IN53
|
1650 |
|
|
last_address[1] => Equal2.IN10
|
1651 |
|
|
last_address[1] => Equal1.IN52
|
1652 |
|
|
last_address[2] => Equal2.IN9
|
1653 |
|
|
last_address[2] => Equal1.IN51
|
1654 |
|
|
last_address[3] => Equal2.IN8
|
1655 |
|
|
last_address[3] => Equal1.IN50
|
1656 |
|
|
last_address[4] => Equal2.IN7
|
1657 |
|
|
last_address[4] => Equal1.IN49
|
1658 |
|
|
last_address[5] => Equal2.IN6
|
1659 |
|
|
last_address[5] => Equal1.IN48
|
1660 |
|
|
last_address[6] => Equal2.IN5
|
1661 |
|
|
last_address[6] => Equal1.IN47
|
1662 |
|
|
last_address[7] => Equal2.IN4
|
1663 |
|
|
last_address[7] => Equal1.IN46
|
1664 |
|
|
last_address[8] => Equal2.IN3
|
1665 |
|
|
last_address[8] => Equal1.IN45
|
1666 |
|
|
last_address[9] => Equal2.IN2
|
1667 |
|
|
last_address[9] => Equal1.IN44
|
1668 |
|
|
out_rd_rdy <= out_rd_rdy~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
1669 |
|
|
out_port[0] <= ram_256x48:ram_256x48_Inst.q[0]
|
1670 |
|
|
out_port[1] <= ram_256x48:ram_256x48_Inst.q[1]
|
1671 |
|
|
out_port[2] <= ram_256x48:ram_256x48_Inst.q[2]
|
1672 |
|
|
out_port[3] <= ram_256x48:ram_256x48_Inst.q[3]
|
1673 |
|
|
out_port[4] <= ram_256x48:ram_256x48_Inst.q[4]
|
1674 |
|
|
out_port[5] <= ram_256x48:ram_256x48_Inst.q[5]
|
1675 |
|
|
out_port[6] <= ram_256x48:ram_256x48_Inst.q[6]
|
1676 |
|
|
out_port[7] <= ram_256x48:ram_256x48_Inst.q[7]
|
1677 |
|
|
out_mac[0] <= ram_256x48:ram_256x48_Inst.q[8]
|
1678 |
|
|
out_mac[1] <= ram_256x48:ram_256x48_Inst.q[9]
|
1679 |
|
|
out_mac[2] <= ram_256x48:ram_256x48_Inst.q[10]
|
1680 |
|
|
out_mac[3] <= ram_256x48:ram_256x48_Inst.q[11]
|
1681 |
|
|
out_mac[4] <= ram_256x48:ram_256x48_Inst.q[12]
|
1682 |
|
|
out_mac[5] <= ram_256x48:ram_256x48_Inst.q[13]
|
1683 |
|
|
out_mac[6] <= ram_256x48:ram_256x48_Inst.q[14]
|
1684 |
|
|
out_mac[7] <= ram_256x48:ram_256x48_Inst.q[15]
|
1685 |
|
|
out_mac[8] <= ram_256x48:ram_256x48_Inst.q[16]
|
1686 |
|
|
out_mac[9] <= ram_256x48:ram_256x48_Inst.q[17]
|
1687 |
|
|
out_mac[10] <= ram_256x48:ram_256x48_Inst.q[18]
|
1688 |
|
|
out_mac[11] <= ram_256x48:ram_256x48_Inst.q[19]
|
1689 |
|
|
out_mac[12] <= ram_256x48:ram_256x48_Inst.q[20]
|
1690 |
|
|
out_mac[13] <= ram_256x48:ram_256x48_Inst.q[21]
|
1691 |
|
|
out_mac[14] <= ram_256x48:ram_256x48_Inst.q[22]
|
1692 |
|
|
out_mac[15] <= ram_256x48:ram_256x48_Inst.q[23]
|
1693 |
|
|
out_mac[16] <= ram_256x48:ram_256x48_Inst.q[24]
|
1694 |
|
|
out_mac[17] <= ram_256x48:ram_256x48_Inst.q[25]
|
1695 |
|
|
out_mac[18] <= ram_256x48:ram_256x48_Inst.q[26]
|
1696 |
|
|
out_mac[19] <= ram_256x48:ram_256x48_Inst.q[27]
|
1697 |
|
|
out_mac[20] <= ram_256x48:ram_256x48_Inst.q[28]
|
1698 |
|
|
out_mac[21] <= ram_256x48:ram_256x48_Inst.q[29]
|
1699 |
|
|
out_mac[22] <= ram_256x48:ram_256x48_Inst.q[30]
|
1700 |
|
|
out_mac[23] <= ram_256x48:ram_256x48_Inst.q[31]
|
1701 |
|
|
out_mac[24] <= ram_256x48:ram_256x48_Inst.q[32]
|
1702 |
|
|
out_mac[25] <= ram_256x48:ram_256x48_Inst.q[33]
|
1703 |
|
|
out_mac[26] <= ram_256x48:ram_256x48_Inst.q[34]
|
1704 |
|
|
out_mac[27] <= ram_256x48:ram_256x48_Inst.q[35]
|
1705 |
|
|
out_mac[28] <= ram_256x48:ram_256x48_Inst.q[36]
|
1706 |
|
|
out_mac[29] <= ram_256x48:ram_256x48_Inst.q[37]
|
1707 |
|
|
out_mac[30] <= ram_256x48:ram_256x48_Inst.q[38]
|
1708 |
|
|
out_mac[31] <= ram_256x48:ram_256x48_Inst.q[39]
|
1709 |
|
|
out_mac[32] <= ram_256x48:ram_256x48_Inst.q[40]
|
1710 |
|
|
out_mac[33] <= ram_256x48:ram_256x48_Inst.q[41]
|
1711 |
|
|
out_mac[34] <= ram_256x48:ram_256x48_Inst.q[42]
|
1712 |
|
|
out_mac[35] <= ram_256x48:ram_256x48_Inst.q[43]
|
1713 |
|
|
out_mac[36] <= ram_256x48:ram_256x48_Inst.q[44]
|
1714 |
|
|
out_mac[37] <= ram_256x48:ram_256x48_Inst.q[45]
|
1715 |
|
|
out_mac[38] <= ram_256x48:ram_256x48_Inst.q[46]
|
1716 |
|
|
out_mac[39] <= ram_256x48:ram_256x48_Inst.q[47]
|
1717 |
|
|
out_mac[40] <= ram_256x48:ram_256x48_Inst.q[48]
|
1718 |
|
|
out_mac[41] <= ram_256x48:ram_256x48_Inst.q[49]
|
1719 |
|
|
out_mac[42] <= ram_256x48:ram_256x48_Inst.q[50]
|
1720 |
|
|
out_mac[43] <= ram_256x48:ram_256x48_Inst.q[51]
|
1721 |
|
|
out_mac[44] <= ram_256x48:ram_256x48_Inst.q[52]
|
1722 |
|
|
out_mac[45] <= ram_256x48:ram_256x48_Inst.q[53]
|
1723 |
|
|
out_mac[46] <= ram_256x48:ram_256x48_Inst.q[54]
|
1724 |
|
|
out_mac[47] <= ram_256x48:ram_256x48_Inst.q[55]
|
1725 |
|
|
|
1726 |
|
|
|
1727 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Aging_Timer:Aging_Timer_Inst
|
1728 |
|
|
clk => r_reg[31].CLK
|
1729 |
|
|
clk => r_reg[30].CLK
|
1730 |
|
|
clk => r_reg[29].CLK
|
1731 |
|
|
clk => r_reg[28].CLK
|
1732 |
|
|
clk => r_reg[27].CLK
|
1733 |
|
|
clk => r_reg[26].CLK
|
1734 |
|
|
clk => r_reg[25].CLK
|
1735 |
|
|
clk => r_reg[24].CLK
|
1736 |
|
|
clk => r_reg[23].CLK
|
1737 |
|
|
clk => r_reg[22].CLK
|
1738 |
|
|
clk => r_reg[21].CLK
|
1739 |
|
|
clk => r_reg[20].CLK
|
1740 |
|
|
clk => r_reg[19].CLK
|
1741 |
|
|
clk => r_reg[18].CLK
|
1742 |
|
|
clk => r_reg[17].CLK
|
1743 |
|
|
clk => r_reg[16].CLK
|
1744 |
|
|
clk => r_reg[15].CLK
|
1745 |
|
|
clk => r_reg[14].CLK
|
1746 |
|
|
clk => r_reg[13].CLK
|
1747 |
|
|
clk => r_reg[12].CLK
|
1748 |
|
|
clk => r_reg[11].CLK
|
1749 |
|
|
clk => r_reg[10].CLK
|
1750 |
|
|
clk => r_reg[9].CLK
|
1751 |
|
|
clk => r_reg[8].CLK
|
1752 |
|
|
clk => r_reg[7].CLK
|
1753 |
|
|
clk => r_reg[6].CLK
|
1754 |
|
|
clk => r_reg[5].CLK
|
1755 |
|
|
clk => r_reg[4].CLK
|
1756 |
|
|
clk => r_reg[3].CLK
|
1757 |
|
|
clk => r_reg[2].CLK
|
1758 |
|
|
clk => r_reg[1].CLK
|
1759 |
|
|
clk => r_reg[0].CLK
|
1760 |
|
|
clk => timer_aging_bit_i.CLK
|
1761 |
|
|
reset => r_reg[31].ACLR
|
1762 |
|
|
reset => r_reg[30].ACLR
|
1763 |
|
|
reset => r_reg[29].ACLR
|
1764 |
|
|
reset => r_reg[28].ACLR
|
1765 |
|
|
reset => r_reg[27].ACLR
|
1766 |
|
|
reset => r_reg[26].ACLR
|
1767 |
|
|
reset => r_reg[25].ACLR
|
1768 |
|
|
reset => r_reg[24].ACLR
|
1769 |
|
|
reset => r_reg[23].ACLR
|
1770 |
|
|
reset => r_reg[22].ACLR
|
1771 |
|
|
reset => r_reg[21].ACLR
|
1772 |
|
|
reset => r_reg[20].ACLR
|
1773 |
|
|
reset => r_reg[19].ACLR
|
1774 |
|
|
reset => r_reg[18].ACLR
|
1775 |
|
|
reset => r_reg[17].ACLR
|
1776 |
|
|
reset => r_reg[16].ACLR
|
1777 |
|
|
reset => r_reg[15].ACLR
|
1778 |
|
|
reset => r_reg[14].ACLR
|
1779 |
|
|
reset => r_reg[13].ACLR
|
1780 |
|
|
reset => r_reg[12].ACLR
|
1781 |
|
|
reset => r_reg[11].ACLR
|
1782 |
|
|
reset => r_reg[10].ACLR
|
1783 |
|
|
reset => r_reg[9].ACLR
|
1784 |
|
|
reset => r_reg[8].ACLR
|
1785 |
|
|
reset => r_reg[7].ACLR
|
1786 |
|
|
reset => r_reg[6].ACLR
|
1787 |
|
|
reset => r_reg[5].ACLR
|
1788 |
|
|
reset => r_reg[4].ACLR
|
1789 |
|
|
reset => r_reg[3].ACLR
|
1790 |
|
|
reset => r_reg[2].ACLR
|
1791 |
|
|
reset => r_reg[1].ACLR
|
1792 |
|
|
reset => r_reg[0].ACLR
|
1793 |
|
|
reset => timer_aging_bit_i.ACLR
|
1794 |
|
|
timeout <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
1795 |
|
|
timer_aging_bit <= timer_aging_bit_i.DB_MAX_OUTPUT_PORT_TYPE
|
1796 |
|
|
count_out[0] <= r_reg[0].DB_MAX_OUTPUT_PORT_TYPE
|
1797 |
|
|
count_out[1] <= r_reg[1].DB_MAX_OUTPUT_PORT_TYPE
|
1798 |
|
|
count_out[2] <= r_reg[2].DB_MAX_OUTPUT_PORT_TYPE
|
1799 |
|
|
count_out[3] <= r_reg[3].DB_MAX_OUTPUT_PORT_TYPE
|
1800 |
|
|
count_out[4] <= r_reg[4].DB_MAX_OUTPUT_PORT_TYPE
|
1801 |
|
|
count_out[5] <= r_reg[5].DB_MAX_OUTPUT_PORT_TYPE
|
1802 |
|
|
count_out[6] <= r_reg[6].DB_MAX_OUTPUT_PORT_TYPE
|
1803 |
|
|
count_out[7] <= r_reg[7].DB_MAX_OUTPUT_PORT_TYPE
|
1804 |
|
|
count_out[8] <= r_reg[8].DB_MAX_OUTPUT_PORT_TYPE
|
1805 |
|
|
count_out[9] <= r_reg[9].DB_MAX_OUTPUT_PORT_TYPE
|
1806 |
|
|
count_out[10] <= r_reg[10].DB_MAX_OUTPUT_PORT_TYPE
|
1807 |
|
|
count_out[11] <= r_reg[11].DB_MAX_OUTPUT_PORT_TYPE
|
1808 |
|
|
count_out[12] <= r_reg[12].DB_MAX_OUTPUT_PORT_TYPE
|
1809 |
|
|
count_out[13] <= r_reg[13].DB_MAX_OUTPUT_PORT_TYPE
|
1810 |
|
|
count_out[14] <= r_reg[14].DB_MAX_OUTPUT_PORT_TYPE
|
1811 |
|
|
count_out[15] <= r_reg[15].DB_MAX_OUTPUT_PORT_TYPE
|
1812 |
|
|
count_out[16] <= r_reg[16].DB_MAX_OUTPUT_PORT_TYPE
|
1813 |
|
|
count_out[17] <= r_reg[17].DB_MAX_OUTPUT_PORT_TYPE
|
1814 |
|
|
count_out[18] <= r_reg[18].DB_MAX_OUTPUT_PORT_TYPE
|
1815 |
|
|
count_out[19] <= r_reg[19].DB_MAX_OUTPUT_PORT_TYPE
|
1816 |
|
|
count_out[20] <= r_reg[20].DB_MAX_OUTPUT_PORT_TYPE
|
1817 |
|
|
count_out[21] <= r_reg[21].DB_MAX_OUTPUT_PORT_TYPE
|
1818 |
|
|
count_out[22] <= r_reg[22].DB_MAX_OUTPUT_PORT_TYPE
|
1819 |
|
|
count_out[23] <= r_reg[23].DB_MAX_OUTPUT_PORT_TYPE
|
1820 |
|
|
count_out[24] <= r_reg[24].DB_MAX_OUTPUT_PORT_TYPE
|
1821 |
|
|
count_out[25] <= r_reg[25].DB_MAX_OUTPUT_PORT_TYPE
|
1822 |
|
|
count_out[26] <= r_reg[26].DB_MAX_OUTPUT_PORT_TYPE
|
1823 |
|
|
count_out[27] <= r_reg[27].DB_MAX_OUTPUT_PORT_TYPE
|
1824 |
|
|
count_out[28] <= r_reg[28].DB_MAX_OUTPUT_PORT_TYPE
|
1825 |
|
|
count_out[29] <= r_reg[29].DB_MAX_OUTPUT_PORT_TYPE
|
1826 |
|
|
count_out[30] <= r_reg[30].DB_MAX_OUTPUT_PORT_TYPE
|
1827 |
|
|
count_out[31] <= r_reg[31].DB_MAX_OUTPUT_PORT_TYPE
|
1828 |
|
|
|
1829 |
|
|
|
1830 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst
|
1831 |
|
|
clk => q[55]~reg0.CLK
|
1832 |
|
|
clk => q[54]~reg0.CLK
|
1833 |
|
|
clk => q[53]~reg0.CLK
|
1834 |
|
|
clk => q[52]~reg0.CLK
|
1835 |
|
|
clk => q[51]~reg0.CLK
|
1836 |
|
|
clk => q[50]~reg0.CLK
|
1837 |
|
|
clk => q[49]~reg0.CLK
|
1838 |
|
|
clk => q[48]~reg0.CLK
|
1839 |
|
|
clk => q[47]~reg0.CLK
|
1840 |
|
|
clk => q[46]~reg0.CLK
|
1841 |
|
|
clk => q[45]~reg0.CLK
|
1842 |
|
|
clk => q[44]~reg0.CLK
|
1843 |
|
|
clk => q[43]~reg0.CLK
|
1844 |
|
|
clk => q[42]~reg0.CLK
|
1845 |
|
|
clk => q[41]~reg0.CLK
|
1846 |
|
|
clk => q[40]~reg0.CLK
|
1847 |
|
|
clk => q[39]~reg0.CLK
|
1848 |
|
|
clk => q[38]~reg0.CLK
|
1849 |
|
|
clk => q[37]~reg0.CLK
|
1850 |
|
|
clk => q[36]~reg0.CLK
|
1851 |
|
|
clk => q[35]~reg0.CLK
|
1852 |
|
|
clk => q[34]~reg0.CLK
|
1853 |
|
|
clk => q[33]~reg0.CLK
|
1854 |
|
|
clk => q[32]~reg0.CLK
|
1855 |
|
|
clk => q[31]~reg0.CLK
|
1856 |
|
|
clk => q[30]~reg0.CLK
|
1857 |
|
|
clk => q[29]~reg0.CLK
|
1858 |
|
|
clk => q[28]~reg0.CLK
|
1859 |
|
|
clk => q[27]~reg0.CLK
|
1860 |
|
|
clk => q[26]~reg0.CLK
|
1861 |
|
|
clk => q[25]~reg0.CLK
|
1862 |
|
|
clk => q[24]~reg0.CLK
|
1863 |
|
|
clk => q[23]~reg0.CLK
|
1864 |
|
|
clk => q[22]~reg0.CLK
|
1865 |
|
|
clk => q[21]~reg0.CLK
|
1866 |
|
|
clk => q[20]~reg0.CLK
|
1867 |
|
|
clk => q[19]~reg0.CLK
|
1868 |
|
|
clk => q[18]~reg0.CLK
|
1869 |
|
|
clk => q[17]~reg0.CLK
|
1870 |
|
|
clk => q[16]~reg0.CLK
|
1871 |
|
|
clk => q[15]~reg0.CLK
|
1872 |
|
|
clk => q[14]~reg0.CLK
|
1873 |
|
|
clk => q[13]~reg0.CLK
|
1874 |
|
|
clk => q[12]~reg0.CLK
|
1875 |
|
|
clk => q[11]~reg0.CLK
|
1876 |
|
|
clk => q[10]~reg0.CLK
|
1877 |
|
|
clk => q[9]~reg0.CLK
|
1878 |
|
|
clk => q[8]~reg0.CLK
|
1879 |
|
|
clk => q[7]~reg0.CLK
|
1880 |
|
|
clk => q[6]~reg0.CLK
|
1881 |
|
|
clk => q[5]~reg0.CLK
|
1882 |
|
|
clk => q[4]~reg0.CLK
|
1883 |
|
|
clk => q[3]~reg0.CLK
|
1884 |
|
|
clk => q[2]~reg0.CLK
|
1885 |
|
|
clk => q[1]~reg0.CLK
|
1886 |
|
|
clk => q[0]~reg0.CLK
|
1887 |
|
|
clk => ram~65.CLK
|
1888 |
|
|
clk => ram~64.CLK
|
1889 |
|
|
clk => ram~63.CLK
|
1890 |
|
|
clk => ram~62.CLK
|
1891 |
|
|
clk => ram~61.CLK
|
1892 |
|
|
clk => ram~60.CLK
|
1893 |
|
|
clk => ram~59.CLK
|
1894 |
|
|
clk => ram~58.CLK
|
1895 |
|
|
clk => ram~57.CLK
|
1896 |
|
|
clk => ram~56.CLK
|
1897 |
|
|
clk => ram~55.CLK
|
1898 |
|
|
clk => ram~54.CLK
|
1899 |
|
|
clk => ram~53.CLK
|
1900 |
|
|
clk => ram~52.CLK
|
1901 |
|
|
clk => ram~51.CLK
|
1902 |
|
|
clk => ram~50.CLK
|
1903 |
|
|
clk => ram~49.CLK
|
1904 |
|
|
clk => ram~48.CLK
|
1905 |
|
|
clk => ram~47.CLK
|
1906 |
|
|
clk => ram~46.CLK
|
1907 |
|
|
clk => ram~45.CLK
|
1908 |
|
|
clk => ram~44.CLK
|
1909 |
|
|
clk => ram~43.CLK
|
1910 |
|
|
clk => ram~42.CLK
|
1911 |
|
|
clk => ram~41.CLK
|
1912 |
|
|
clk => ram~40.CLK
|
1913 |
|
|
clk => ram~39.CLK
|
1914 |
|
|
clk => ram~38.CLK
|
1915 |
|
|
clk => ram~37.CLK
|
1916 |
|
|
clk => ram~36.CLK
|
1917 |
|
|
clk => ram~35.CLK
|
1918 |
|
|
clk => ram~34.CLK
|
1919 |
|
|
clk => ram~33.CLK
|
1920 |
|
|
clk => ram~32.CLK
|
1921 |
|
|
clk => ram~31.CLK
|
1922 |
|
|
clk => ram~30.CLK
|
1923 |
|
|
clk => ram~29.CLK
|
1924 |
|
|
clk => ram~28.CLK
|
1925 |
|
|
clk => ram~27.CLK
|
1926 |
|
|
clk => ram~26.CLK
|
1927 |
|
|
clk => ram~25.CLK
|
1928 |
|
|
clk => ram~24.CLK
|
1929 |
|
|
clk => ram~23.CLK
|
1930 |
|
|
clk => ram~22.CLK
|
1931 |
|
|
clk => ram~21.CLK
|
1932 |
|
|
clk => ram~20.CLK
|
1933 |
|
|
clk => ram~19.CLK
|
1934 |
|
|
clk => ram~18.CLK
|
1935 |
|
|
clk => ram~17.CLK
|
1936 |
|
|
clk => ram~16.CLK
|
1937 |
|
|
clk => ram~15.CLK
|
1938 |
|
|
clk => ram~14.CLK
|
1939 |
|
|
clk => ram~13.CLK
|
1940 |
|
|
clk => ram~12.CLK
|
1941 |
|
|
clk => ram~11.CLK
|
1942 |
|
|
clk => ram~10.CLK
|
1943 |
|
|
clk => ram~9.CLK
|
1944 |
|
|
clk => ram~8.CLK
|
1945 |
|
|
clk => ram~7.CLK
|
1946 |
|
|
clk => ram~6.CLK
|
1947 |
|
|
clk => ram~5.CLK
|
1948 |
|
|
clk => ram~4.CLK
|
1949 |
|
|
clk => ram~3.CLK
|
1950 |
|
|
clk => ram~2.CLK
|
1951 |
|
|
clk => ram~1.CLK
|
1952 |
|
|
clk => ram~0.CLK
|
1953 |
|
|
clk => ram~66.CLK
|
1954 |
|
|
clk => ram.CLK0
|
1955 |
|
|
raddr[0] => ram.RADDR
|
1956 |
|
|
raddr[1] => ram.RADDR1
|
1957 |
|
|
raddr[2] => ram.RADDR2
|
1958 |
|
|
raddr[3] => ram.RADDR3
|
1959 |
|
|
raddr[4] => ram.RADDR4
|
1960 |
|
|
raddr[5] => ram.RADDR5
|
1961 |
|
|
raddr[6] => ram.RADDR6
|
1962 |
|
|
raddr[7] => ram.RADDR7
|
1963 |
|
|
raddr[8] => ram.RADDR8
|
1964 |
|
|
raddr[9] => ram.RADDR9
|
1965 |
|
|
waddr[0] => ram~9.DATAIN
|
1966 |
|
|
waddr[0] => ram.WADDR
|
1967 |
|
|
waddr[1] => ram~8.DATAIN
|
1968 |
|
|
waddr[1] => ram.WADDR1
|
1969 |
|
|
waddr[2] => ram~7.DATAIN
|
1970 |
|
|
waddr[2] => ram.WADDR2
|
1971 |
|
|
waddr[3] => ram~6.DATAIN
|
1972 |
|
|
waddr[3] => ram.WADDR3
|
1973 |
|
|
waddr[4] => ram~5.DATAIN
|
1974 |
|
|
waddr[4] => ram.WADDR4
|
1975 |
|
|
waddr[5] => ram~4.DATAIN
|
1976 |
|
|
waddr[5] => ram.WADDR5
|
1977 |
|
|
waddr[6] => ram~3.DATAIN
|
1978 |
|
|
waddr[6] => ram.WADDR6
|
1979 |
|
|
waddr[7] => ram~2.DATAIN
|
1980 |
|
|
waddr[7] => ram.WADDR7
|
1981 |
|
|
waddr[8] => ram~1.DATAIN
|
1982 |
|
|
waddr[8] => ram.WADDR8
|
1983 |
|
|
waddr[9] => ram~0.DATAIN
|
1984 |
|
|
waddr[9] => ram.WADDR9
|
1985 |
|
|
data[0] => ram~65.DATAIN
|
1986 |
|
|
data[0] => ram.DATAIN
|
1987 |
|
|
data[1] => ram~64.DATAIN
|
1988 |
|
|
data[1] => ram.DATAIN1
|
1989 |
|
|
data[2] => ram~63.DATAIN
|
1990 |
|
|
data[2] => ram.DATAIN2
|
1991 |
|
|
data[3] => ram~62.DATAIN
|
1992 |
|
|
data[3] => ram.DATAIN3
|
1993 |
|
|
data[4] => ram~61.DATAIN
|
1994 |
|
|
data[4] => ram.DATAIN4
|
1995 |
|
|
data[5] => ram~60.DATAIN
|
1996 |
|
|
data[5] => ram.DATAIN5
|
1997 |
|
|
data[6] => ram~59.DATAIN
|
1998 |
|
|
data[6] => ram.DATAIN6
|
1999 |
|
|
data[7] => ram~58.DATAIN
|
2000 |
|
|
data[7] => ram.DATAIN7
|
2001 |
|
|
data[8] => ram~57.DATAIN
|
2002 |
|
|
data[8] => ram.DATAIN8
|
2003 |
|
|
data[9] => ram~56.DATAIN
|
2004 |
|
|
data[9] => ram.DATAIN9
|
2005 |
|
|
data[10] => ram~55.DATAIN
|
2006 |
|
|
data[10] => ram.DATAIN10
|
2007 |
|
|
data[11] => ram~54.DATAIN
|
2008 |
|
|
data[11] => ram.DATAIN11
|
2009 |
|
|
data[12] => ram~53.DATAIN
|
2010 |
|
|
data[12] => ram.DATAIN12
|
2011 |
|
|
data[13] => ram~52.DATAIN
|
2012 |
|
|
data[13] => ram.DATAIN13
|
2013 |
|
|
data[14] => ram~51.DATAIN
|
2014 |
|
|
data[14] => ram.DATAIN14
|
2015 |
|
|
data[15] => ram~50.DATAIN
|
2016 |
|
|
data[15] => ram.DATAIN15
|
2017 |
|
|
data[16] => ram~49.DATAIN
|
2018 |
|
|
data[16] => ram.DATAIN16
|
2019 |
|
|
data[17] => ram~48.DATAIN
|
2020 |
|
|
data[17] => ram.DATAIN17
|
2021 |
|
|
data[18] => ram~47.DATAIN
|
2022 |
|
|
data[18] => ram.DATAIN18
|
2023 |
|
|
data[19] => ram~46.DATAIN
|
2024 |
|
|
data[19] => ram.DATAIN19
|
2025 |
|
|
data[20] => ram~45.DATAIN
|
2026 |
|
|
data[20] => ram.DATAIN20
|
2027 |
|
|
data[21] => ram~44.DATAIN
|
2028 |
|
|
data[21] => ram.DATAIN21
|
2029 |
|
|
data[22] => ram~43.DATAIN
|
2030 |
|
|
data[22] => ram.DATAIN22
|
2031 |
|
|
data[23] => ram~42.DATAIN
|
2032 |
|
|
data[23] => ram.DATAIN23
|
2033 |
|
|
data[24] => ram~41.DATAIN
|
2034 |
|
|
data[24] => ram.DATAIN24
|
2035 |
|
|
data[25] => ram~40.DATAIN
|
2036 |
|
|
data[25] => ram.DATAIN25
|
2037 |
|
|
data[26] => ram~39.DATAIN
|
2038 |
|
|
data[26] => ram.DATAIN26
|
2039 |
|
|
data[27] => ram~38.DATAIN
|
2040 |
|
|
data[27] => ram.DATAIN27
|
2041 |
|
|
data[28] => ram~37.DATAIN
|
2042 |
|
|
data[28] => ram.DATAIN28
|
2043 |
|
|
data[29] => ram~36.DATAIN
|
2044 |
|
|
data[29] => ram.DATAIN29
|
2045 |
|
|
data[30] => ram~35.DATAIN
|
2046 |
|
|
data[30] => ram.DATAIN30
|
2047 |
|
|
data[31] => ram~34.DATAIN
|
2048 |
|
|
data[31] => ram.DATAIN31
|
2049 |
|
|
data[32] => ram~33.DATAIN
|
2050 |
|
|
data[32] => ram.DATAIN32
|
2051 |
|
|
data[33] => ram~32.DATAIN
|
2052 |
|
|
data[33] => ram.DATAIN33
|
2053 |
|
|
data[34] => ram~31.DATAIN
|
2054 |
|
|
data[34] => ram.DATAIN34
|
2055 |
|
|
data[35] => ram~30.DATAIN
|
2056 |
|
|
data[35] => ram.DATAIN35
|
2057 |
|
|
data[36] => ram~29.DATAIN
|
2058 |
|
|
data[36] => ram.DATAIN36
|
2059 |
|
|
data[37] => ram~28.DATAIN
|
2060 |
|
|
data[37] => ram.DATAIN37
|
2061 |
|
|
data[38] => ram~27.DATAIN
|
2062 |
|
|
data[38] => ram.DATAIN38
|
2063 |
|
|
data[39] => ram~26.DATAIN
|
2064 |
|
|
data[39] => ram.DATAIN39
|
2065 |
|
|
data[40] => ram~25.DATAIN
|
2066 |
|
|
data[40] => ram.DATAIN40
|
2067 |
|
|
data[41] => ram~24.DATAIN
|
2068 |
|
|
data[41] => ram.DATAIN41
|
2069 |
|
|
data[42] => ram~23.DATAIN
|
2070 |
|
|
data[42] => ram.DATAIN42
|
2071 |
|
|
data[43] => ram~22.DATAIN
|
2072 |
|
|
data[43] => ram.DATAIN43
|
2073 |
|
|
data[44] => ram~21.DATAIN
|
2074 |
|
|
data[44] => ram.DATAIN44
|
2075 |
|
|
data[45] => ram~20.DATAIN
|
2076 |
|
|
data[45] => ram.DATAIN45
|
2077 |
|
|
data[46] => ram~19.DATAIN
|
2078 |
|
|
data[46] => ram.DATAIN46
|
2079 |
|
|
data[47] => ram~18.DATAIN
|
2080 |
|
|
data[47] => ram.DATAIN47
|
2081 |
|
|
data[48] => ram~17.DATAIN
|
2082 |
|
|
data[48] => ram.DATAIN48
|
2083 |
|
|
data[49] => ram~16.DATAIN
|
2084 |
|
|
data[49] => ram.DATAIN49
|
2085 |
|
|
data[50] => ram~15.DATAIN
|
2086 |
|
|
data[50] => ram.DATAIN50
|
2087 |
|
|
data[51] => ram~14.DATAIN
|
2088 |
|
|
data[51] => ram.DATAIN51
|
2089 |
|
|
data[52] => ram~13.DATAIN
|
2090 |
|
|
data[52] => ram.DATAIN52
|
2091 |
|
|
data[53] => ram~12.DATAIN
|
2092 |
|
|
data[53] => ram.DATAIN53
|
2093 |
|
|
data[54] => ram~11.DATAIN
|
2094 |
|
|
data[54] => ram.DATAIN54
|
2095 |
|
|
data[55] => ram~10.DATAIN
|
2096 |
|
|
data[55] => ram.DATAIN55
|
2097 |
|
|
we => ram~66.DATAIN
|
2098 |
|
|
we => ram.WE
|
2099 |
|
|
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2100 |
|
|
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2101 |
|
|
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2102 |
|
|
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2103 |
|
|
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2104 |
|
|
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2105 |
|
|
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2106 |
|
|
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2107 |
|
|
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2108 |
|
|
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2109 |
|
|
q[10] <= q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2110 |
|
|
q[11] <= q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2111 |
|
|
q[12] <= q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2112 |
|
|
q[13] <= q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2113 |
|
|
q[14] <= q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2114 |
|
|
q[15] <= q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2115 |
|
|
q[16] <= q[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2116 |
|
|
q[17] <= q[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2117 |
|
|
q[18] <= q[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2118 |
|
|
q[19] <= q[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2119 |
|
|
q[20] <= q[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2120 |
|
|
q[21] <= q[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2121 |
|
|
q[22] <= q[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2122 |
|
|
q[23] <= q[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2123 |
|
|
q[24] <= q[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2124 |
|
|
q[25] <= q[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2125 |
|
|
q[26] <= q[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2126 |
|
|
q[27] <= q[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2127 |
|
|
q[28] <= q[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2128 |
|
|
q[29] <= q[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2129 |
|
|
q[30] <= q[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2130 |
|
|
q[31] <= q[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2131 |
|
|
q[32] <= q[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2132 |
|
|
q[33] <= q[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2133 |
|
|
q[34] <= q[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2134 |
|
|
q[35] <= q[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2135 |
|
|
q[36] <= q[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2136 |
|
|
q[37] <= q[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2137 |
|
|
q[38] <= q[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2138 |
|
|
q[39] <= q[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2139 |
|
|
q[40] <= q[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2140 |
|
|
q[41] <= q[41]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2141 |
|
|
q[42] <= q[42]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2142 |
|
|
q[43] <= q[43]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2143 |
|
|
q[44] <= q[44]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2144 |
|
|
q[45] <= q[45]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2145 |
|
|
q[46] <= q[46]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2146 |
|
|
q[47] <= q[47]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2147 |
|
|
q[48] <= q[48]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2148 |
|
|
q[49] <= q[49]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2149 |
|
|
q[50] <= q[50]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2150 |
|
|
q[51] <= q[51]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2151 |
|
|
q[52] <= q[52]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2152 |
|
|
q[53] <= q[53]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2153 |
|
|
q[54] <= q[54]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2154 |
|
|
q[55] <= q[55]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2155 |
|
|
|
2156 |
|
|
|
2157 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst
|
2158 |
|
|
clk => q[55]~reg0.CLK
|
2159 |
|
|
clk => q[54]~reg0.CLK
|
2160 |
|
|
clk => q[53]~reg0.CLK
|
2161 |
|
|
clk => q[52]~reg0.CLK
|
2162 |
|
|
clk => q[51]~reg0.CLK
|
2163 |
|
|
clk => q[50]~reg0.CLK
|
2164 |
|
|
clk => q[49]~reg0.CLK
|
2165 |
|
|
clk => q[48]~reg0.CLK
|
2166 |
|
|
clk => q[47]~reg0.CLK
|
2167 |
|
|
clk => q[46]~reg0.CLK
|
2168 |
|
|
clk => q[45]~reg0.CLK
|
2169 |
|
|
clk => q[44]~reg0.CLK
|
2170 |
|
|
clk => q[43]~reg0.CLK
|
2171 |
|
|
clk => q[42]~reg0.CLK
|
2172 |
|
|
clk => q[41]~reg0.CLK
|
2173 |
|
|
clk => q[40]~reg0.CLK
|
2174 |
|
|
clk => q[39]~reg0.CLK
|
2175 |
|
|
clk => q[38]~reg0.CLK
|
2176 |
|
|
clk => q[37]~reg0.CLK
|
2177 |
|
|
clk => q[36]~reg0.CLK
|
2178 |
|
|
clk => q[35]~reg0.CLK
|
2179 |
|
|
clk => q[34]~reg0.CLK
|
2180 |
|
|
clk => q[33]~reg0.CLK
|
2181 |
|
|
clk => q[32]~reg0.CLK
|
2182 |
|
|
clk => q[31]~reg0.CLK
|
2183 |
|
|
clk => q[30]~reg0.CLK
|
2184 |
|
|
clk => q[29]~reg0.CLK
|
2185 |
|
|
clk => q[28]~reg0.CLK
|
2186 |
|
|
clk => q[27]~reg0.CLK
|
2187 |
|
|
clk => q[26]~reg0.CLK
|
2188 |
|
|
clk => q[25]~reg0.CLK
|
2189 |
|
|
clk => q[24]~reg0.CLK
|
2190 |
|
|
clk => q[23]~reg0.CLK
|
2191 |
|
|
clk => q[22]~reg0.CLK
|
2192 |
|
|
clk => q[21]~reg0.CLK
|
2193 |
|
|
clk => q[20]~reg0.CLK
|
2194 |
|
|
clk => q[19]~reg0.CLK
|
2195 |
|
|
clk => q[18]~reg0.CLK
|
2196 |
|
|
clk => q[17]~reg0.CLK
|
2197 |
|
|
clk => q[16]~reg0.CLK
|
2198 |
|
|
clk => q[15]~reg0.CLK
|
2199 |
|
|
clk => q[14]~reg0.CLK
|
2200 |
|
|
clk => q[13]~reg0.CLK
|
2201 |
|
|
clk => q[12]~reg0.CLK
|
2202 |
|
|
clk => q[11]~reg0.CLK
|
2203 |
|
|
clk => q[10]~reg0.CLK
|
2204 |
|
|
clk => q[9]~reg0.CLK
|
2205 |
|
|
clk => q[8]~reg0.CLK
|
2206 |
|
|
clk => q[7]~reg0.CLK
|
2207 |
|
|
clk => q[6]~reg0.CLK
|
2208 |
|
|
clk => q[5]~reg0.CLK
|
2209 |
|
|
clk => q[4]~reg0.CLK
|
2210 |
|
|
clk => q[3]~reg0.CLK
|
2211 |
|
|
clk => q[2]~reg0.CLK
|
2212 |
|
|
clk => q[1]~reg0.CLK
|
2213 |
|
|
clk => q[0]~reg0.CLK
|
2214 |
|
|
clk => ram~65.CLK
|
2215 |
|
|
clk => ram~64.CLK
|
2216 |
|
|
clk => ram~63.CLK
|
2217 |
|
|
clk => ram~62.CLK
|
2218 |
|
|
clk => ram~61.CLK
|
2219 |
|
|
clk => ram~60.CLK
|
2220 |
|
|
clk => ram~59.CLK
|
2221 |
|
|
clk => ram~58.CLK
|
2222 |
|
|
clk => ram~57.CLK
|
2223 |
|
|
clk => ram~56.CLK
|
2224 |
|
|
clk => ram~55.CLK
|
2225 |
|
|
clk => ram~54.CLK
|
2226 |
|
|
clk => ram~53.CLK
|
2227 |
|
|
clk => ram~52.CLK
|
2228 |
|
|
clk => ram~51.CLK
|
2229 |
|
|
clk => ram~50.CLK
|
2230 |
|
|
clk => ram~49.CLK
|
2231 |
|
|
clk => ram~48.CLK
|
2232 |
|
|
clk => ram~47.CLK
|
2233 |
|
|
clk => ram~46.CLK
|
2234 |
|
|
clk => ram~45.CLK
|
2235 |
|
|
clk => ram~44.CLK
|
2236 |
|
|
clk => ram~43.CLK
|
2237 |
|
|
clk => ram~42.CLK
|
2238 |
|
|
clk => ram~41.CLK
|
2239 |
|
|
clk => ram~40.CLK
|
2240 |
|
|
clk => ram~39.CLK
|
2241 |
|
|
clk => ram~38.CLK
|
2242 |
|
|
clk => ram~37.CLK
|
2243 |
|
|
clk => ram~36.CLK
|
2244 |
|
|
clk => ram~35.CLK
|
2245 |
|
|
clk => ram~34.CLK
|
2246 |
|
|
clk => ram~33.CLK
|
2247 |
|
|
clk => ram~32.CLK
|
2248 |
|
|
clk => ram~31.CLK
|
2249 |
|
|
clk => ram~30.CLK
|
2250 |
|
|
clk => ram~29.CLK
|
2251 |
|
|
clk => ram~28.CLK
|
2252 |
|
|
clk => ram~27.CLK
|
2253 |
|
|
clk => ram~26.CLK
|
2254 |
|
|
clk => ram~25.CLK
|
2255 |
|
|
clk => ram~24.CLK
|
2256 |
|
|
clk => ram~23.CLK
|
2257 |
|
|
clk => ram~22.CLK
|
2258 |
|
|
clk => ram~21.CLK
|
2259 |
|
|
clk => ram~20.CLK
|
2260 |
|
|
clk => ram~19.CLK
|
2261 |
|
|
clk => ram~18.CLK
|
2262 |
|
|
clk => ram~17.CLK
|
2263 |
|
|
clk => ram~16.CLK
|
2264 |
|
|
clk => ram~15.CLK
|
2265 |
|
|
clk => ram~14.CLK
|
2266 |
|
|
clk => ram~13.CLK
|
2267 |
|
|
clk => ram~12.CLK
|
2268 |
|
|
clk => ram~11.CLK
|
2269 |
|
|
clk => ram~10.CLK
|
2270 |
|
|
clk => ram~9.CLK
|
2271 |
|
|
clk => ram~8.CLK
|
2272 |
|
|
clk => ram~7.CLK
|
2273 |
|
|
clk => ram~6.CLK
|
2274 |
|
|
clk => ram~5.CLK
|
2275 |
|
|
clk => ram~4.CLK
|
2276 |
|
|
clk => ram~3.CLK
|
2277 |
|
|
clk => ram~2.CLK
|
2278 |
|
|
clk => ram~1.CLK
|
2279 |
|
|
clk => ram~0.CLK
|
2280 |
|
|
clk => ram~66.CLK
|
2281 |
|
|
clk => ram.CLK0
|
2282 |
|
|
raddr[0] => ram.RADDR
|
2283 |
|
|
raddr[1] => ram.RADDR1
|
2284 |
|
|
raddr[2] => ram.RADDR2
|
2285 |
|
|
raddr[3] => ram.RADDR3
|
2286 |
|
|
raddr[4] => ram.RADDR4
|
2287 |
|
|
raddr[5] => ram.RADDR5
|
2288 |
|
|
raddr[6] => ram.RADDR6
|
2289 |
|
|
raddr[7] => ram.RADDR7
|
2290 |
|
|
raddr[8] => ram.RADDR8
|
2291 |
|
|
raddr[9] => ram.RADDR9
|
2292 |
|
|
waddr[0] => ram~9.DATAIN
|
2293 |
|
|
waddr[0] => ram.WADDR
|
2294 |
|
|
waddr[1] => ram~8.DATAIN
|
2295 |
|
|
waddr[1] => ram.WADDR1
|
2296 |
|
|
waddr[2] => ram~7.DATAIN
|
2297 |
|
|
waddr[2] => ram.WADDR2
|
2298 |
|
|
waddr[3] => ram~6.DATAIN
|
2299 |
|
|
waddr[3] => ram.WADDR3
|
2300 |
|
|
waddr[4] => ram~5.DATAIN
|
2301 |
|
|
waddr[4] => ram.WADDR4
|
2302 |
|
|
waddr[5] => ram~4.DATAIN
|
2303 |
|
|
waddr[5] => ram.WADDR5
|
2304 |
|
|
waddr[6] => ram~3.DATAIN
|
2305 |
|
|
waddr[6] => ram.WADDR6
|
2306 |
|
|
waddr[7] => ram~2.DATAIN
|
2307 |
|
|
waddr[7] => ram.WADDR7
|
2308 |
|
|
waddr[8] => ram~1.DATAIN
|
2309 |
|
|
waddr[8] => ram.WADDR8
|
2310 |
|
|
waddr[9] => ram~0.DATAIN
|
2311 |
|
|
waddr[9] => ram.WADDR9
|
2312 |
|
|
data[0] => ram~65.DATAIN
|
2313 |
|
|
data[0] => ram.DATAIN
|
2314 |
|
|
data[1] => ram~64.DATAIN
|
2315 |
|
|
data[1] => ram.DATAIN1
|
2316 |
|
|
data[2] => ram~63.DATAIN
|
2317 |
|
|
data[2] => ram.DATAIN2
|
2318 |
|
|
data[3] => ram~62.DATAIN
|
2319 |
|
|
data[3] => ram.DATAIN3
|
2320 |
|
|
data[4] => ram~61.DATAIN
|
2321 |
|
|
data[4] => ram.DATAIN4
|
2322 |
|
|
data[5] => ram~60.DATAIN
|
2323 |
|
|
data[5] => ram.DATAIN5
|
2324 |
|
|
data[6] => ram~59.DATAIN
|
2325 |
|
|
data[6] => ram.DATAIN6
|
2326 |
|
|
data[7] => ram~58.DATAIN
|
2327 |
|
|
data[7] => ram.DATAIN7
|
2328 |
|
|
data[8] => ram~57.DATAIN
|
2329 |
|
|
data[8] => ram.DATAIN8
|
2330 |
|
|
data[9] => ram~56.DATAIN
|
2331 |
|
|
data[9] => ram.DATAIN9
|
2332 |
|
|
data[10] => ram~55.DATAIN
|
2333 |
|
|
data[10] => ram.DATAIN10
|
2334 |
|
|
data[11] => ram~54.DATAIN
|
2335 |
|
|
data[11] => ram.DATAIN11
|
2336 |
|
|
data[12] => ram~53.DATAIN
|
2337 |
|
|
data[12] => ram.DATAIN12
|
2338 |
|
|
data[13] => ram~52.DATAIN
|
2339 |
|
|
data[13] => ram.DATAIN13
|
2340 |
|
|
data[14] => ram~51.DATAIN
|
2341 |
|
|
data[14] => ram.DATAIN14
|
2342 |
|
|
data[15] => ram~50.DATAIN
|
2343 |
|
|
data[15] => ram.DATAIN15
|
2344 |
|
|
data[16] => ram~49.DATAIN
|
2345 |
|
|
data[16] => ram.DATAIN16
|
2346 |
|
|
data[17] => ram~48.DATAIN
|
2347 |
|
|
data[17] => ram.DATAIN17
|
2348 |
|
|
data[18] => ram~47.DATAIN
|
2349 |
|
|
data[18] => ram.DATAIN18
|
2350 |
|
|
data[19] => ram~46.DATAIN
|
2351 |
|
|
data[19] => ram.DATAIN19
|
2352 |
|
|
data[20] => ram~45.DATAIN
|
2353 |
|
|
data[20] => ram.DATAIN20
|
2354 |
|
|
data[21] => ram~44.DATAIN
|
2355 |
|
|
data[21] => ram.DATAIN21
|
2356 |
|
|
data[22] => ram~43.DATAIN
|
2357 |
|
|
data[22] => ram.DATAIN22
|
2358 |
|
|
data[23] => ram~42.DATAIN
|
2359 |
|
|
data[23] => ram.DATAIN23
|
2360 |
|
|
data[24] => ram~41.DATAIN
|
2361 |
|
|
data[24] => ram.DATAIN24
|
2362 |
|
|
data[25] => ram~40.DATAIN
|
2363 |
|
|
data[25] => ram.DATAIN25
|
2364 |
|
|
data[26] => ram~39.DATAIN
|
2365 |
|
|
data[26] => ram.DATAIN26
|
2366 |
|
|
data[27] => ram~38.DATAIN
|
2367 |
|
|
data[27] => ram.DATAIN27
|
2368 |
|
|
data[28] => ram~37.DATAIN
|
2369 |
|
|
data[28] => ram.DATAIN28
|
2370 |
|
|
data[29] => ram~36.DATAIN
|
2371 |
|
|
data[29] => ram.DATAIN29
|
2372 |
|
|
data[30] => ram~35.DATAIN
|
2373 |
|
|
data[30] => ram.DATAIN30
|
2374 |
|
|
data[31] => ram~34.DATAIN
|
2375 |
|
|
data[31] => ram.DATAIN31
|
2376 |
|
|
data[32] => ram~33.DATAIN
|
2377 |
|
|
data[32] => ram.DATAIN32
|
2378 |
|
|
data[33] => ram~32.DATAIN
|
2379 |
|
|
data[33] => ram.DATAIN33
|
2380 |
|
|
data[34] => ram~31.DATAIN
|
2381 |
|
|
data[34] => ram.DATAIN34
|
2382 |
|
|
data[35] => ram~30.DATAIN
|
2383 |
|
|
data[35] => ram.DATAIN35
|
2384 |
|
|
data[36] => ram~29.DATAIN
|
2385 |
|
|
data[36] => ram.DATAIN36
|
2386 |
|
|
data[37] => ram~28.DATAIN
|
2387 |
|
|
data[37] => ram.DATAIN37
|
2388 |
|
|
data[38] => ram~27.DATAIN
|
2389 |
|
|
data[38] => ram.DATAIN38
|
2390 |
|
|
data[39] => ram~26.DATAIN
|
2391 |
|
|
data[39] => ram.DATAIN39
|
2392 |
|
|
data[40] => ram~25.DATAIN
|
2393 |
|
|
data[40] => ram.DATAIN40
|
2394 |
|
|
data[41] => ram~24.DATAIN
|
2395 |
|
|
data[41] => ram.DATAIN41
|
2396 |
|
|
data[42] => ram~23.DATAIN
|
2397 |
|
|
data[42] => ram.DATAIN42
|
2398 |
|
|
data[43] => ram~22.DATAIN
|
2399 |
|
|
data[43] => ram.DATAIN43
|
2400 |
|
|
data[44] => ram~21.DATAIN
|
2401 |
|
|
data[44] => ram.DATAIN44
|
2402 |
|
|
data[45] => ram~20.DATAIN
|
2403 |
|
|
data[45] => ram.DATAIN45
|
2404 |
|
|
data[46] => ram~19.DATAIN
|
2405 |
|
|
data[46] => ram.DATAIN46
|
2406 |
|
|
data[47] => ram~18.DATAIN
|
2407 |
|
|
data[47] => ram.DATAIN47
|
2408 |
|
|
data[48] => ram~17.DATAIN
|
2409 |
|
|
data[48] => ram.DATAIN48
|
2410 |
|
|
data[49] => ram~16.DATAIN
|
2411 |
|
|
data[49] => ram.DATAIN49
|
2412 |
|
|
data[50] => ram~15.DATAIN
|
2413 |
|
|
data[50] => ram.DATAIN50
|
2414 |
|
|
data[51] => ram~14.DATAIN
|
2415 |
|
|
data[51] => ram.DATAIN51
|
2416 |
|
|
data[52] => ram~13.DATAIN
|
2417 |
|
|
data[52] => ram.DATAIN52
|
2418 |
|
|
data[53] => ram~12.DATAIN
|
2419 |
|
|
data[53] => ram.DATAIN53
|
2420 |
|
|
data[54] => ram~11.DATAIN
|
2421 |
|
|
data[54] => ram.DATAIN54
|
2422 |
|
|
data[55] => ram~10.DATAIN
|
2423 |
|
|
data[55] => ram.DATAIN55
|
2424 |
|
|
we => ram~66.DATAIN
|
2425 |
|
|
we => ram.WE
|
2426 |
|
|
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2427 |
|
|
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2428 |
|
|
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2429 |
|
|
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2430 |
|
|
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2431 |
|
|
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2432 |
|
|
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2433 |
|
|
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2434 |
|
|
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2435 |
|
|
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2436 |
|
|
q[10] <= q[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2437 |
|
|
q[11] <= q[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2438 |
|
|
q[12] <= q[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2439 |
|
|
q[13] <= q[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2440 |
|
|
q[14] <= q[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2441 |
|
|
q[15] <= q[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2442 |
|
|
q[16] <= q[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2443 |
|
|
q[17] <= q[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2444 |
|
|
q[18] <= q[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2445 |
|
|
q[19] <= q[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2446 |
|
|
q[20] <= q[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2447 |
|
|
q[21] <= q[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2448 |
|
|
q[22] <= q[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2449 |
|
|
q[23] <= q[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2450 |
|
|
q[24] <= q[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2451 |
|
|
q[25] <= q[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2452 |
|
|
q[26] <= q[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2453 |
|
|
q[27] <= q[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2454 |
|
|
q[28] <= q[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2455 |
|
|
q[29] <= q[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2456 |
|
|
q[30] <= q[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2457 |
|
|
q[31] <= q[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2458 |
|
|
q[32] <= q[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2459 |
|
|
q[33] <= q[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2460 |
|
|
q[34] <= q[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2461 |
|
|
q[35] <= q[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2462 |
|
|
q[36] <= q[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2463 |
|
|
q[37] <= q[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2464 |
|
|
q[38] <= q[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2465 |
|
|
q[39] <= q[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2466 |
|
|
q[40] <= q[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2467 |
|
|
q[41] <= q[41]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2468 |
|
|
q[42] <= q[42]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2469 |
|
|
q[43] <= q[43]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2470 |
|
|
q[44] <= q[44]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2471 |
|
|
q[45] <= q[45]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2472 |
|
|
q[46] <= q[46]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2473 |
|
|
q[47] <= q[47]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2474 |
|
|
q[48] <= q[48]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2475 |
|
|
q[49] <= q[49]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2476 |
|
|
q[50] <= q[50]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2477 |
|
|
q[51] <= q[51]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2478 |
|
|
q[52] <= q[52]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2479 |
|
|
q[53] <= q[53]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2480 |
|
|
q[54] <= q[54]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2481 |
|
|
q[55] <= q[55]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2482 |
|
|
|
2483 |
|
|
|
2484 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst
|
2485 |
|
|
din[0] => queue.data_a[0].DATAIN
|
2486 |
|
|
din[0] => queue.DATAIN
|
2487 |
|
|
din[1] => queue.data_a[1].DATAIN
|
2488 |
|
|
din[1] => queue.DATAIN1
|
2489 |
|
|
din[2] => queue.data_a[2].DATAIN
|
2490 |
|
|
din[2] => queue.DATAIN2
|
2491 |
|
|
din[3] => queue.data_a[3].DATAIN
|
2492 |
|
|
din[3] => queue.DATAIN3
|
2493 |
|
|
din[4] => queue.data_a[4].DATAIN
|
2494 |
|
|
din[4] => queue.DATAIN4
|
2495 |
|
|
din[5] => queue.data_a[5].DATAIN
|
2496 |
|
|
din[5] => queue.DATAIN5
|
2497 |
|
|
din[6] => queue.data_a[6].DATAIN
|
2498 |
|
|
din[6] => queue.DATAIN6
|
2499 |
|
|
din[7] => queue.data_a[7].DATAIN
|
2500 |
|
|
din[7] => queue.DATAIN7
|
2501 |
|
|
din[8] => queue.data_a[8].DATAIN
|
2502 |
|
|
din[8] => queue.DATAIN8
|
2503 |
|
|
din[9] => queue.data_a[9].DATAIN
|
2504 |
|
|
din[9] => queue.DATAIN9
|
2505 |
|
|
wr_en => always0~0.DATAIN
|
2506 |
|
|
wr_en => always1~0.IN0
|
2507 |
|
|
wr_en => wr_ptr~4.OUTPUTSELECT
|
2508 |
|
|
wr_en => wr_ptr~3.OUTPUTSELECT
|
2509 |
|
|
wr_en => wr_ptr~2.OUTPUTSELECT
|
2510 |
|
|
wr_en => wr_ptr~1.OUTPUTSELECT
|
2511 |
|
|
wr_en => wr_ptr~0.OUTPUTSELECT
|
2512 |
|
|
wr_en => always1~1.IN0
|
2513 |
|
|
wr_en => queue.WE
|
2514 |
|
|
rd_en => always1~1.IN1
|
2515 |
|
|
rd_en => rd_ptr~4.OUTPUTSELECT
|
2516 |
|
|
rd_en => rd_ptr~3.OUTPUTSELECT
|
2517 |
|
|
rd_en => rd_ptr~2.OUTPUTSELECT
|
2518 |
|
|
rd_en => rd_ptr~1.OUTPUTSELECT
|
2519 |
|
|
rd_en => rd_ptr~0.OUTPUTSELECT
|
2520 |
|
|
rd_en => always1~0.IN1
|
2521 |
|
|
rd_en => dout[0]~reg0.ENA
|
2522 |
|
|
rd_en => dout[1]~reg0.ENA
|
2523 |
|
|
rd_en => dout[2]~reg0.ENA
|
2524 |
|
|
rd_en => dout[3]~reg0.ENA
|
2525 |
|
|
rd_en => dout[4]~reg0.ENA
|
2526 |
|
|
rd_en => dout[5]~reg0.ENA
|
2527 |
|
|
rd_en => dout[6]~reg0.ENA
|
2528 |
|
|
rd_en => dout[7]~reg0.ENA
|
2529 |
|
|
rd_en => dout[8]~reg0.ENA
|
2530 |
|
|
rd_en => dout[9]~reg0.ENA
|
2531 |
|
|
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2532 |
|
|
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2533 |
|
|
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2534 |
|
|
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2535 |
|
|
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2536 |
|
|
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2537 |
|
|
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2538 |
|
|
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2539 |
|
|
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2540 |
|
|
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2541 |
|
|
full <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
2542 |
|
|
nearly_full <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
|
2543 |
|
|
empty <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
|
2544 |
|
|
reset => depth~17.OUTPUTSELECT
|
2545 |
|
|
reset => depth~16.OUTPUTSELECT
|
2546 |
|
|
reset => depth~15.OUTPUTSELECT
|
2547 |
|
|
reset => depth~14.OUTPUTSELECT
|
2548 |
|
|
reset => depth~13.OUTPUTSELECT
|
2549 |
|
|
reset => depth~12.OUTPUTSELECT
|
2550 |
|
|
reset => wr_ptr~9.OUTPUTSELECT
|
2551 |
|
|
reset => wr_ptr~8.OUTPUTSELECT
|
2552 |
|
|
reset => wr_ptr~7.OUTPUTSELECT
|
2553 |
|
|
reset => wr_ptr~6.OUTPUTSELECT
|
2554 |
|
|
reset => wr_ptr~5.OUTPUTSELECT
|
2555 |
|
|
reset => rd_ptr~9.OUTPUTSELECT
|
2556 |
|
|
reset => rd_ptr~8.OUTPUTSELECT
|
2557 |
|
|
reset => rd_ptr~7.OUTPUTSELECT
|
2558 |
|
|
reset => rd_ptr~6.OUTPUTSELECT
|
2559 |
|
|
reset => rd_ptr~5.OUTPUTSELECT
|
2560 |
|
|
clk => dout[9]~reg0.CLK
|
2561 |
|
|
clk => dout[8]~reg0.CLK
|
2562 |
|
|
clk => dout[7]~reg0.CLK
|
2563 |
|
|
clk => dout[6]~reg0.CLK
|
2564 |
|
|
clk => dout[5]~reg0.CLK
|
2565 |
|
|
clk => dout[4]~reg0.CLK
|
2566 |
|
|
clk => dout[3]~reg0.CLK
|
2567 |
|
|
clk => dout[2]~reg0.CLK
|
2568 |
|
|
clk => dout[1]~reg0.CLK
|
2569 |
|
|
clk => dout[0]~reg0.CLK
|
2570 |
|
|
clk => rd_ptr[4].CLK
|
2571 |
|
|
clk => rd_ptr[3].CLK
|
2572 |
|
|
clk => rd_ptr[2].CLK
|
2573 |
|
|
clk => rd_ptr[1].CLK
|
2574 |
|
|
clk => rd_ptr[0].CLK
|
2575 |
|
|
clk => wr_ptr[4].CLK
|
2576 |
|
|
clk => wr_ptr[3].CLK
|
2577 |
|
|
clk => wr_ptr[2].CLK
|
2578 |
|
|
clk => wr_ptr[1].CLK
|
2579 |
|
|
clk => wr_ptr[0].CLK
|
2580 |
|
|
clk => depth[5].CLK
|
2581 |
|
|
clk => depth[4].CLK
|
2582 |
|
|
clk => depth[3].CLK
|
2583 |
|
|
clk => depth[2].CLK
|
2584 |
|
|
clk => depth[1].CLK
|
2585 |
|
|
clk => depth[0].CLK
|
2586 |
|
|
clk => queue.data_a[0].CLK
|
2587 |
|
|
clk => queue.data_a[1].CLK
|
2588 |
|
|
clk => queue.data_a[2].CLK
|
2589 |
|
|
clk => queue.data_a[3].CLK
|
2590 |
|
|
clk => queue.data_a[4].CLK
|
2591 |
|
|
clk => queue.data_a[5].CLK
|
2592 |
|
|
clk => queue.data_a[6].CLK
|
2593 |
|
|
clk => queue.data_a[7].CLK
|
2594 |
|
|
clk => queue.data_a[8].CLK
|
2595 |
|
|
clk => queue.data_a[9].CLK
|
2596 |
|
|
clk => queue.waddr_a[0].CLK
|
2597 |
|
|
clk => queue.waddr_a[1].CLK
|
2598 |
|
|
clk => queue.waddr_a[2].CLK
|
2599 |
|
|
clk => queue.waddr_a[3].CLK
|
2600 |
|
|
clk => queue.waddr_a[4].CLK
|
2601 |
|
|
clk => always0~0.CLK
|
2602 |
|
|
clk => queue.CLK0
|
2603 |
|
|
|
2604 |
|
|
|
2605 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:time_command_Inst
|
2606 |
|
|
din[0] => queue.data_a[0].DATAIN
|
2607 |
|
|
din[0] => queue.DATAIN
|
2608 |
|
|
wr_en => always0~0.DATAIN
|
2609 |
|
|
wr_en => always1~0.IN0
|
2610 |
|
|
wr_en => wr_ptr~1.OUTPUTSELECT
|
2611 |
|
|
wr_en => wr_ptr~0.OUTPUTSELECT
|
2612 |
|
|
wr_en => always1~1.IN0
|
2613 |
|
|
wr_en => queue.WE
|
2614 |
|
|
rd_en => always1~1.IN1
|
2615 |
|
|
rd_en => rd_ptr~1.OUTPUTSELECT
|
2616 |
|
|
rd_en => rd_ptr~0.OUTPUTSELECT
|
2617 |
|
|
rd_en => always1~0.IN1
|
2618 |
|
|
rd_en => dout[0]~reg0.ENA
|
2619 |
|
|
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2620 |
|
|
full <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
2621 |
|
|
nearly_full <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
|
2622 |
|
|
empty <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
|
2623 |
|
|
reset => depth~8.OUTPUTSELECT
|
2624 |
|
|
reset => depth~7.OUTPUTSELECT
|
2625 |
|
|
reset => depth~6.OUTPUTSELECT
|
2626 |
|
|
reset => wr_ptr~3.OUTPUTSELECT
|
2627 |
|
|
reset => wr_ptr~2.OUTPUTSELECT
|
2628 |
|
|
reset => rd_ptr~3.OUTPUTSELECT
|
2629 |
|
|
reset => rd_ptr~2.OUTPUTSELECT
|
2630 |
|
|
clk => dout[0]~reg0.CLK
|
2631 |
|
|
clk => rd_ptr[1].CLK
|
2632 |
|
|
clk => rd_ptr[0].CLK
|
2633 |
|
|
clk => wr_ptr[1].CLK
|
2634 |
|
|
clk => wr_ptr[0].CLK
|
2635 |
|
|
clk => depth[2].CLK
|
2636 |
|
|
clk => depth[1].CLK
|
2637 |
|
|
clk => depth[0].CLK
|
2638 |
|
|
clk => queue.data_a[0].CLK
|
2639 |
|
|
clk => queue.waddr_a[0].CLK
|
2640 |
|
|
clk => queue.waddr_a[1].CLK
|
2641 |
|
|
clk => always0~0.CLK
|
2642 |
|
|
clk => queue.CLK0
|
2643 |
|
|
|
2644 |
|
|
|
2645 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst
|
2646 |
|
|
clk => q[1]~reg0.CLK
|
2647 |
|
|
clk => q[0]~reg0.CLK
|
2648 |
|
|
clk => ram~11.CLK
|
2649 |
|
|
clk => ram~10.CLK
|
2650 |
|
|
clk => ram~9.CLK
|
2651 |
|
|
clk => ram~8.CLK
|
2652 |
|
|
clk => ram~7.CLK
|
2653 |
|
|
clk => ram~6.CLK
|
2654 |
|
|
clk => ram~5.CLK
|
2655 |
|
|
clk => ram~4.CLK
|
2656 |
|
|
clk => ram~3.CLK
|
2657 |
|
|
clk => ram~2.CLK
|
2658 |
|
|
clk => ram~1.CLK
|
2659 |
|
|
clk => ram~0.CLK
|
2660 |
|
|
clk => ram~12.CLK
|
2661 |
|
|
clk => ram.CLK0
|
2662 |
|
|
raddr[0] => ram.RADDR
|
2663 |
|
|
raddr[1] => ram.RADDR1
|
2664 |
|
|
raddr[2] => ram.RADDR2
|
2665 |
|
|
raddr[3] => ram.RADDR3
|
2666 |
|
|
raddr[4] => ram.RADDR4
|
2667 |
|
|
raddr[5] => ram.RADDR5
|
2668 |
|
|
raddr[6] => ram.RADDR6
|
2669 |
|
|
raddr[7] => ram.RADDR7
|
2670 |
|
|
raddr[8] => ram.RADDR8
|
2671 |
|
|
raddr[9] => ram.RADDR9
|
2672 |
|
|
waddr[0] => ram~9.DATAIN
|
2673 |
|
|
waddr[0] => ram.WADDR
|
2674 |
|
|
waddr[1] => ram~8.DATAIN
|
2675 |
|
|
waddr[1] => ram.WADDR1
|
2676 |
|
|
waddr[2] => ram~7.DATAIN
|
2677 |
|
|
waddr[2] => ram.WADDR2
|
2678 |
|
|
waddr[3] => ram~6.DATAIN
|
2679 |
|
|
waddr[3] => ram.WADDR3
|
2680 |
|
|
waddr[4] => ram~5.DATAIN
|
2681 |
|
|
waddr[4] => ram.WADDR4
|
2682 |
|
|
waddr[5] => ram~4.DATAIN
|
2683 |
|
|
waddr[5] => ram.WADDR5
|
2684 |
|
|
waddr[6] => ram~3.DATAIN
|
2685 |
|
|
waddr[6] => ram.WADDR6
|
2686 |
|
|
waddr[7] => ram~2.DATAIN
|
2687 |
|
|
waddr[7] => ram.WADDR7
|
2688 |
|
|
waddr[8] => ram~1.DATAIN
|
2689 |
|
|
waddr[8] => ram.WADDR8
|
2690 |
|
|
waddr[9] => ram~0.DATAIN
|
2691 |
|
|
waddr[9] => ram.WADDR9
|
2692 |
|
|
data[0] => ram~11.DATAIN
|
2693 |
|
|
data[0] => ram.DATAIN
|
2694 |
|
|
data[1] => ram~10.DATAIN
|
2695 |
|
|
data[1] => ram.DATAIN1
|
2696 |
|
|
we => ram~12.DATAIN
|
2697 |
|
|
we => ram.WE
|
2698 |
|
|
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2699 |
|
|
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2700 |
|
|
|
2701 |
|
|
|
2702 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst
|
2703 |
|
|
clk => ram_256x48:valid_mac_256x48_Inst.clk
|
2704 |
|
|
clk => ram_256x48:valid_mac_Map_256x48_Inst.clk
|
2705 |
|
|
clk => small_fifo:read_command_Inst.clk
|
2706 |
|
|
clk => small_fifo:remove_command_Inst.clk
|
2707 |
|
|
clk => out_rdy~reg0.CLK
|
2708 |
|
|
clk => out_rdy_ii.CLK
|
2709 |
|
|
clk => current_up.CLK
|
2710 |
|
|
clk => item_wr_en.CLK
|
2711 |
|
|
clk => item_raddr[9].CLK
|
2712 |
|
|
clk => item_raddr[8].CLK
|
2713 |
|
|
clk => item_raddr[7].CLK
|
2714 |
|
|
clk => item_raddr[6].CLK
|
2715 |
|
|
clk => item_raddr[5].CLK
|
2716 |
|
|
clk => item_raddr[4].CLK
|
2717 |
|
|
clk => item_raddr[3].CLK
|
2718 |
|
|
clk => item_raddr[2].CLK
|
2719 |
|
|
clk => item_raddr[1].CLK
|
2720 |
|
|
clk => item_raddr[0].CLK
|
2721 |
|
|
clk => item_waddr[9].CLK
|
2722 |
|
|
clk => item_waddr[8].CLK
|
2723 |
|
|
clk => item_waddr[7].CLK
|
2724 |
|
|
clk => item_waddr[6].CLK
|
2725 |
|
|
clk => item_waddr[5].CLK
|
2726 |
|
|
clk => item_waddr[4].CLK
|
2727 |
|
|
clk => item_waddr[3].CLK
|
2728 |
|
|
clk => item_waddr[2].CLK
|
2729 |
|
|
clk => item_waddr[1].CLK
|
2730 |
|
|
clk => item_waddr[0].CLK
|
2731 |
|
|
clk => item_value[9].CLK
|
2732 |
|
|
clk => item_value[8].CLK
|
2733 |
|
|
clk => item_value[7].CLK
|
2734 |
|
|
clk => item_value[6].CLK
|
2735 |
|
|
clk => item_value[5].CLK
|
2736 |
|
|
clk => item_value[4].CLK
|
2737 |
|
|
clk => item_value[3].CLK
|
2738 |
|
|
clk => item_value[2].CLK
|
2739 |
|
|
clk => item_value[1].CLK
|
2740 |
|
|
clk => item_value[0].CLK
|
2741 |
|
|
clk => map_raddr[9].CLK
|
2742 |
|
|
clk => map_raddr[8].CLK
|
2743 |
|
|
clk => map_raddr[7].CLK
|
2744 |
|
|
clk => map_raddr[6].CLK
|
2745 |
|
|
clk => map_raddr[5].CLK
|
2746 |
|
|
clk => map_raddr[4].CLK
|
2747 |
|
|
clk => map_raddr[3].CLK
|
2748 |
|
|
clk => map_raddr[2].CLK
|
2749 |
|
|
clk => map_raddr[1].CLK
|
2750 |
|
|
clk => map_raddr[0].CLK
|
2751 |
|
|
clk => map_waddr[9].CLK
|
2752 |
|
|
clk => map_waddr[8].CLK
|
2753 |
|
|
clk => map_waddr[7].CLK
|
2754 |
|
|
clk => map_waddr[6].CLK
|
2755 |
|
|
clk => map_waddr[5].CLK
|
2756 |
|
|
clk => map_waddr[4].CLK
|
2757 |
|
|
clk => map_waddr[3].CLK
|
2758 |
|
|
clk => map_waddr[2].CLK
|
2759 |
|
|
clk => map_waddr[1].CLK
|
2760 |
|
|
clk => map_waddr[0].CLK
|
2761 |
|
|
clk => map_value[9].CLK
|
2762 |
|
|
clk => map_value[8].CLK
|
2763 |
|
|
clk => map_value[7].CLK
|
2764 |
|
|
clk => map_value[6].CLK
|
2765 |
|
|
clk => map_value[5].CLK
|
2766 |
|
|
clk => map_value[4].CLK
|
2767 |
|
|
clk => map_value[3].CLK
|
2768 |
|
|
clk => map_value[2].CLK
|
2769 |
|
|
clk => map_value[1].CLK
|
2770 |
|
|
clk => map_value[0].CLK
|
2771 |
|
|
clk => map_wr_en.CLK
|
2772 |
|
|
clk => cnt[9].CLK
|
2773 |
|
|
clk => cnt[8].CLK
|
2774 |
|
|
clk => cnt[7].CLK
|
2775 |
|
|
clk => cnt[6].CLK
|
2776 |
|
|
clk => cnt[5].CLK
|
2777 |
|
|
clk => cnt[4].CLK
|
2778 |
|
|
clk => cnt[3].CLK
|
2779 |
|
|
clk => cnt[2].CLK
|
2780 |
|
|
clk => cnt[1].CLK
|
2781 |
|
|
clk => cnt[0].CLK
|
2782 |
|
|
clk => cnt1[9].CLK
|
2783 |
|
|
clk => cnt1[8].CLK
|
2784 |
|
|
clk => cnt1[7].CLK
|
2785 |
|
|
clk => cnt1[6].CLK
|
2786 |
|
|
clk => cnt1[5].CLK
|
2787 |
|
|
clk => cnt1[4].CLK
|
2788 |
|
|
clk => cnt1[3].CLK
|
2789 |
|
|
clk => cnt1[2].CLK
|
2790 |
|
|
clk => cnt1[1].CLK
|
2791 |
|
|
clk => cnt1[0].CLK
|
2792 |
|
|
clk => small_fifo:write_command_Inst.clk
|
2793 |
|
|
clk => state~0.IN1
|
2794 |
|
|
reset => small_fifo:read_command_Inst.reset
|
2795 |
|
|
reset => small_fifo:remove_command_Inst.reset
|
2796 |
|
|
reset => small_fifo:write_command_Inst.reset
|
2797 |
|
|
reset => cnt~29.OUTPUTSELECT
|
2798 |
|
|
reset => cnt~28.OUTPUTSELECT
|
2799 |
|
|
reset => cnt~27.OUTPUTSELECT
|
2800 |
|
|
reset => cnt~26.OUTPUTSELECT
|
2801 |
|
|
reset => cnt~25.OUTPUTSELECT
|
2802 |
|
|
reset => cnt~24.OUTPUTSELECT
|
2803 |
|
|
reset => cnt~23.OUTPUTSELECT
|
2804 |
|
|
reset => cnt~22.OUTPUTSELECT
|
2805 |
|
|
reset => cnt~21.OUTPUTSELECT
|
2806 |
|
|
reset => cnt~20.OUTPUTSELECT
|
2807 |
|
|
reset => out_rdy~reg0.ENA
|
2808 |
|
|
reset => out_rdy_ii.ENA
|
2809 |
|
|
reset => state~1.IN1
|
2810 |
|
|
in_wr_address[0] => small_fifo:write_command_Inst.din[0]
|
2811 |
|
|
in_wr_address[1] => small_fifo:write_command_Inst.din[1]
|
2812 |
|
|
in_wr_address[2] => small_fifo:write_command_Inst.din[2]
|
2813 |
|
|
in_wr_address[3] => small_fifo:write_command_Inst.din[3]
|
2814 |
|
|
in_wr_address[4] => small_fifo:write_command_Inst.din[4]
|
2815 |
|
|
in_wr_address[5] => small_fifo:write_command_Inst.din[5]
|
2816 |
|
|
in_wr_address[6] => small_fifo:write_command_Inst.din[6]
|
2817 |
|
|
in_wr_address[7] => small_fifo:write_command_Inst.din[7]
|
2818 |
|
|
in_wr_address[8] => small_fifo:write_command_Inst.din[8]
|
2819 |
|
|
in_wr_address[9] => small_fifo:write_command_Inst.din[9]
|
2820 |
|
|
in_wr => small_fifo:write_command_Inst.wr_en
|
2821 |
|
|
in_rd => small_fifo:read_command_Inst.wr_en
|
2822 |
|
|
in_key[0] => ~NO_FANOUT~
|
2823 |
|
|
in_key[1] => ~NO_FANOUT~
|
2824 |
|
|
in_key[2] => ~NO_FANOUT~
|
2825 |
|
|
in_key[3] => ~NO_FANOUT~
|
2826 |
|
|
in_key[4] => ~NO_FANOUT~
|
2827 |
|
|
in_key[5] => ~NO_FANOUT~
|
2828 |
|
|
in_key[6] => ~NO_FANOUT~
|
2829 |
|
|
in_key[7] => ~NO_FANOUT~
|
2830 |
|
|
in_key[8] => ~NO_FANOUT~
|
2831 |
|
|
in_key[9] => ~NO_FANOUT~
|
2832 |
|
|
in_rm_address_no[0] => small_fifo:remove_command_Inst.din[0]
|
2833 |
|
|
in_rm_address_no[1] => small_fifo:remove_command_Inst.din[1]
|
2834 |
|
|
in_rm_address_no[2] => small_fifo:remove_command_Inst.din[2]
|
2835 |
|
|
in_rm_address_no[3] => small_fifo:remove_command_Inst.din[3]
|
2836 |
|
|
in_rm_address_no[4] => small_fifo:remove_command_Inst.din[4]
|
2837 |
|
|
in_rm_address_no[5] => small_fifo:remove_command_Inst.din[5]
|
2838 |
|
|
in_rm_address_no[6] => small_fifo:remove_command_Inst.din[6]
|
2839 |
|
|
in_rm_address_no[7] => small_fifo:remove_command_Inst.din[7]
|
2840 |
|
|
in_rm_address_no[8] => small_fifo:remove_command_Inst.din[8]
|
2841 |
|
|
in_rm_address_no[9] => small_fifo:remove_command_Inst.din[9]
|
2842 |
|
|
in_rm => small_fifo:remove_command_Inst.wr_en
|
2843 |
|
|
out_address[0] <= ram_256x48:valid_mac_256x48_Inst.q[0]
|
2844 |
|
|
out_address[1] <= ram_256x48:valid_mac_256x48_Inst.q[1]
|
2845 |
|
|
out_address[2] <= ram_256x48:valid_mac_256x48_Inst.q[2]
|
2846 |
|
|
out_address[3] <= ram_256x48:valid_mac_256x48_Inst.q[3]
|
2847 |
|
|
out_address[4] <= ram_256x48:valid_mac_256x48_Inst.q[4]
|
2848 |
|
|
out_address[5] <= ram_256x48:valid_mac_256x48_Inst.q[5]
|
2849 |
|
|
out_address[6] <= ram_256x48:valid_mac_256x48_Inst.q[6]
|
2850 |
|
|
out_address[7] <= ram_256x48:valid_mac_256x48_Inst.q[7]
|
2851 |
|
|
out_address[8] <= ram_256x48:valid_mac_256x48_Inst.q[8]
|
2852 |
|
|
out_address[9] <= ram_256x48:valid_mac_256x48_Inst.q[9]
|
2853 |
|
|
out_rdy <= out_rdy~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2854 |
|
|
|
2855 |
|
|
|
2856 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst
|
2857 |
|
|
din[0] => queue.data_a[0].DATAIN
|
2858 |
|
|
din[0] => queue.DATAIN
|
2859 |
|
|
din[1] => queue.data_a[1].DATAIN
|
2860 |
|
|
din[1] => queue.DATAIN1
|
2861 |
|
|
din[2] => queue.data_a[2].DATAIN
|
2862 |
|
|
din[2] => queue.DATAIN2
|
2863 |
|
|
din[3] => queue.data_a[3].DATAIN
|
2864 |
|
|
din[3] => queue.DATAIN3
|
2865 |
|
|
din[4] => queue.data_a[4].DATAIN
|
2866 |
|
|
din[4] => queue.DATAIN4
|
2867 |
|
|
din[5] => queue.data_a[5].DATAIN
|
2868 |
|
|
din[5] => queue.DATAIN5
|
2869 |
|
|
din[6] => queue.data_a[6].DATAIN
|
2870 |
|
|
din[6] => queue.DATAIN6
|
2871 |
|
|
din[7] => queue.data_a[7].DATAIN
|
2872 |
|
|
din[7] => queue.DATAIN7
|
2873 |
|
|
din[8] => queue.data_a[8].DATAIN
|
2874 |
|
|
din[8] => queue.DATAIN8
|
2875 |
|
|
din[9] => queue.data_a[9].DATAIN
|
2876 |
|
|
din[9] => queue.DATAIN9
|
2877 |
|
|
wr_en => always0~0.DATAIN
|
2878 |
|
|
wr_en => always1~0.IN0
|
2879 |
|
|
wr_en => wr_ptr~4.OUTPUTSELECT
|
2880 |
|
|
wr_en => wr_ptr~3.OUTPUTSELECT
|
2881 |
|
|
wr_en => wr_ptr~2.OUTPUTSELECT
|
2882 |
|
|
wr_en => wr_ptr~1.OUTPUTSELECT
|
2883 |
|
|
wr_en => wr_ptr~0.OUTPUTSELECT
|
2884 |
|
|
wr_en => always1~1.IN0
|
2885 |
|
|
wr_en => queue.WE
|
2886 |
|
|
rd_en => always1~1.IN1
|
2887 |
|
|
rd_en => rd_ptr~4.OUTPUTSELECT
|
2888 |
|
|
rd_en => rd_ptr~3.OUTPUTSELECT
|
2889 |
|
|
rd_en => rd_ptr~2.OUTPUTSELECT
|
2890 |
|
|
rd_en => rd_ptr~1.OUTPUTSELECT
|
2891 |
|
|
rd_en => rd_ptr~0.OUTPUTSELECT
|
2892 |
|
|
rd_en => always1~0.IN1
|
2893 |
|
|
rd_en => dout[0]~reg0.ENA
|
2894 |
|
|
rd_en => dout[1]~reg0.ENA
|
2895 |
|
|
rd_en => dout[2]~reg0.ENA
|
2896 |
|
|
rd_en => dout[3]~reg0.ENA
|
2897 |
|
|
rd_en => dout[4]~reg0.ENA
|
2898 |
|
|
rd_en => dout[5]~reg0.ENA
|
2899 |
|
|
rd_en => dout[6]~reg0.ENA
|
2900 |
|
|
rd_en => dout[7]~reg0.ENA
|
2901 |
|
|
rd_en => dout[8]~reg0.ENA
|
2902 |
|
|
rd_en => dout[9]~reg0.ENA
|
2903 |
|
|
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2904 |
|
|
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2905 |
|
|
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2906 |
|
|
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2907 |
|
|
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2908 |
|
|
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2909 |
|
|
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2910 |
|
|
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2911 |
|
|
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2912 |
|
|
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
2913 |
|
|
full <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
2914 |
|
|
nearly_full <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
|
2915 |
|
|
empty <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
|
2916 |
|
|
reset => depth~17.OUTPUTSELECT
|
2917 |
|
|
reset => depth~16.OUTPUTSELECT
|
2918 |
|
|
reset => depth~15.OUTPUTSELECT
|
2919 |
|
|
reset => depth~14.OUTPUTSELECT
|
2920 |
|
|
reset => depth~13.OUTPUTSELECT
|
2921 |
|
|
reset => depth~12.OUTPUTSELECT
|
2922 |
|
|
reset => wr_ptr~9.OUTPUTSELECT
|
2923 |
|
|
reset => wr_ptr~8.OUTPUTSELECT
|
2924 |
|
|
reset => wr_ptr~7.OUTPUTSELECT
|
2925 |
|
|
reset => wr_ptr~6.OUTPUTSELECT
|
2926 |
|
|
reset => wr_ptr~5.OUTPUTSELECT
|
2927 |
|
|
reset => rd_ptr~9.OUTPUTSELECT
|
2928 |
|
|
reset => rd_ptr~8.OUTPUTSELECT
|
2929 |
|
|
reset => rd_ptr~7.OUTPUTSELECT
|
2930 |
|
|
reset => rd_ptr~6.OUTPUTSELECT
|
2931 |
|
|
reset => rd_ptr~5.OUTPUTSELECT
|
2932 |
|
|
clk => dout[9]~reg0.CLK
|
2933 |
|
|
clk => dout[8]~reg0.CLK
|
2934 |
|
|
clk => dout[7]~reg0.CLK
|
2935 |
|
|
clk => dout[6]~reg0.CLK
|
2936 |
|
|
clk => dout[5]~reg0.CLK
|
2937 |
|
|
clk => dout[4]~reg0.CLK
|
2938 |
|
|
clk => dout[3]~reg0.CLK
|
2939 |
|
|
clk => dout[2]~reg0.CLK
|
2940 |
|
|
clk => dout[1]~reg0.CLK
|
2941 |
|
|
clk => dout[0]~reg0.CLK
|
2942 |
|
|
clk => rd_ptr[4].CLK
|
2943 |
|
|
clk => rd_ptr[3].CLK
|
2944 |
|
|
clk => rd_ptr[2].CLK
|
2945 |
|
|
clk => rd_ptr[1].CLK
|
2946 |
|
|
clk => rd_ptr[0].CLK
|
2947 |
|
|
clk => wr_ptr[4].CLK
|
2948 |
|
|
clk => wr_ptr[3].CLK
|
2949 |
|
|
clk => wr_ptr[2].CLK
|
2950 |
|
|
clk => wr_ptr[1].CLK
|
2951 |
|
|
clk => wr_ptr[0].CLK
|
2952 |
|
|
clk => depth[5].CLK
|
2953 |
|
|
clk => depth[4].CLK
|
2954 |
|
|
clk => depth[3].CLK
|
2955 |
|
|
clk => depth[2].CLK
|
2956 |
|
|
clk => depth[1].CLK
|
2957 |
|
|
clk => depth[0].CLK
|
2958 |
|
|
clk => queue.data_a[0].CLK
|
2959 |
|
|
clk => queue.data_a[1].CLK
|
2960 |
|
|
clk => queue.data_a[2].CLK
|
2961 |
|
|
clk => queue.data_a[3].CLK
|
2962 |
|
|
clk => queue.data_a[4].CLK
|
2963 |
|
|
clk => queue.data_a[5].CLK
|
2964 |
|
|
clk => queue.data_a[6].CLK
|
2965 |
|
|
clk => queue.data_a[7].CLK
|
2966 |
|
|
clk => queue.data_a[8].CLK
|
2967 |
|
|
clk => queue.data_a[9].CLK
|
2968 |
|
|
clk => queue.waddr_a[0].CLK
|
2969 |
|
|
clk => queue.waddr_a[1].CLK
|
2970 |
|
|
clk => queue.waddr_a[2].CLK
|
2971 |
|
|
clk => queue.waddr_a[3].CLK
|
2972 |
|
|
clk => queue.waddr_a[4].CLK
|
2973 |
|
|
clk => always0~0.CLK
|
2974 |
|
|
clk => queue.CLK0
|
2975 |
|
|
|
2976 |
|
|
|
2977 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst
|
2978 |
|
|
din[0] => queue.data_a[0].DATAIN
|
2979 |
|
|
din[0] => queue.DATAIN
|
2980 |
|
|
din[1] => queue.data_a[1].DATAIN
|
2981 |
|
|
din[1] => queue.DATAIN1
|
2982 |
|
|
din[2] => queue.data_a[2].DATAIN
|
2983 |
|
|
din[2] => queue.DATAIN2
|
2984 |
|
|
din[3] => queue.data_a[3].DATAIN
|
2985 |
|
|
din[3] => queue.DATAIN3
|
2986 |
|
|
din[4] => queue.data_a[4].DATAIN
|
2987 |
|
|
din[4] => queue.DATAIN4
|
2988 |
|
|
din[5] => queue.data_a[5].DATAIN
|
2989 |
|
|
din[5] => queue.DATAIN5
|
2990 |
|
|
din[6] => queue.data_a[6].DATAIN
|
2991 |
|
|
din[6] => queue.DATAIN6
|
2992 |
|
|
din[7] => queue.data_a[7].DATAIN
|
2993 |
|
|
din[7] => queue.DATAIN7
|
2994 |
|
|
din[8] => queue.data_a[8].DATAIN
|
2995 |
|
|
din[8] => queue.DATAIN8
|
2996 |
|
|
din[9] => queue.data_a[9].DATAIN
|
2997 |
|
|
din[9] => queue.DATAIN9
|
2998 |
|
|
wr_en => always0~0.DATAIN
|
2999 |
|
|
wr_en => always1~0.IN0
|
3000 |
|
|
wr_en => wr_ptr~4.OUTPUTSELECT
|
3001 |
|
|
wr_en => wr_ptr~3.OUTPUTSELECT
|
3002 |
|
|
wr_en => wr_ptr~2.OUTPUTSELECT
|
3003 |
|
|
wr_en => wr_ptr~1.OUTPUTSELECT
|
3004 |
|
|
wr_en => wr_ptr~0.OUTPUTSELECT
|
3005 |
|
|
wr_en => always1~1.IN0
|
3006 |
|
|
wr_en => queue.WE
|
3007 |
|
|
rd_en => always1~1.IN1
|
3008 |
|
|
rd_en => rd_ptr~4.OUTPUTSELECT
|
3009 |
|
|
rd_en => rd_ptr~3.OUTPUTSELECT
|
3010 |
|
|
rd_en => rd_ptr~2.OUTPUTSELECT
|
3011 |
|
|
rd_en => rd_ptr~1.OUTPUTSELECT
|
3012 |
|
|
rd_en => rd_ptr~0.OUTPUTSELECT
|
3013 |
|
|
rd_en => always1~0.IN1
|
3014 |
|
|
rd_en => dout[0]~reg0.ENA
|
3015 |
|
|
rd_en => dout[1]~reg0.ENA
|
3016 |
|
|
rd_en => dout[2]~reg0.ENA
|
3017 |
|
|
rd_en => dout[3]~reg0.ENA
|
3018 |
|
|
rd_en => dout[4]~reg0.ENA
|
3019 |
|
|
rd_en => dout[5]~reg0.ENA
|
3020 |
|
|
rd_en => dout[6]~reg0.ENA
|
3021 |
|
|
rd_en => dout[7]~reg0.ENA
|
3022 |
|
|
rd_en => dout[8]~reg0.ENA
|
3023 |
|
|
rd_en => dout[9]~reg0.ENA
|
3024 |
|
|
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3025 |
|
|
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3026 |
|
|
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3027 |
|
|
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3028 |
|
|
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3029 |
|
|
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3030 |
|
|
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3031 |
|
|
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3032 |
|
|
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3033 |
|
|
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3034 |
|
|
full <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
3035 |
|
|
nearly_full <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
|
3036 |
|
|
empty <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
|
3037 |
|
|
reset => depth~17.OUTPUTSELECT
|
3038 |
|
|
reset => depth~16.OUTPUTSELECT
|
3039 |
|
|
reset => depth~15.OUTPUTSELECT
|
3040 |
|
|
reset => depth~14.OUTPUTSELECT
|
3041 |
|
|
reset => depth~13.OUTPUTSELECT
|
3042 |
|
|
reset => depth~12.OUTPUTSELECT
|
3043 |
|
|
reset => wr_ptr~9.OUTPUTSELECT
|
3044 |
|
|
reset => wr_ptr~8.OUTPUTSELECT
|
3045 |
|
|
reset => wr_ptr~7.OUTPUTSELECT
|
3046 |
|
|
reset => wr_ptr~6.OUTPUTSELECT
|
3047 |
|
|
reset => wr_ptr~5.OUTPUTSELECT
|
3048 |
|
|
reset => rd_ptr~9.OUTPUTSELECT
|
3049 |
|
|
reset => rd_ptr~8.OUTPUTSELECT
|
3050 |
|
|
reset => rd_ptr~7.OUTPUTSELECT
|
3051 |
|
|
reset => rd_ptr~6.OUTPUTSELECT
|
3052 |
|
|
reset => rd_ptr~5.OUTPUTSELECT
|
3053 |
|
|
clk => dout[9]~reg0.CLK
|
3054 |
|
|
clk => dout[8]~reg0.CLK
|
3055 |
|
|
clk => dout[7]~reg0.CLK
|
3056 |
|
|
clk => dout[6]~reg0.CLK
|
3057 |
|
|
clk => dout[5]~reg0.CLK
|
3058 |
|
|
clk => dout[4]~reg0.CLK
|
3059 |
|
|
clk => dout[3]~reg0.CLK
|
3060 |
|
|
clk => dout[2]~reg0.CLK
|
3061 |
|
|
clk => dout[1]~reg0.CLK
|
3062 |
|
|
clk => dout[0]~reg0.CLK
|
3063 |
|
|
clk => rd_ptr[4].CLK
|
3064 |
|
|
clk => rd_ptr[3].CLK
|
3065 |
|
|
clk => rd_ptr[2].CLK
|
3066 |
|
|
clk => rd_ptr[1].CLK
|
3067 |
|
|
clk => rd_ptr[0].CLK
|
3068 |
|
|
clk => wr_ptr[4].CLK
|
3069 |
|
|
clk => wr_ptr[3].CLK
|
3070 |
|
|
clk => wr_ptr[2].CLK
|
3071 |
|
|
clk => wr_ptr[1].CLK
|
3072 |
|
|
clk => wr_ptr[0].CLK
|
3073 |
|
|
clk => depth[5].CLK
|
3074 |
|
|
clk => depth[4].CLK
|
3075 |
|
|
clk => depth[3].CLK
|
3076 |
|
|
clk => depth[2].CLK
|
3077 |
|
|
clk => depth[1].CLK
|
3078 |
|
|
clk => depth[0].CLK
|
3079 |
|
|
clk => queue.data_a[0].CLK
|
3080 |
|
|
clk => queue.data_a[1].CLK
|
3081 |
|
|
clk => queue.data_a[2].CLK
|
3082 |
|
|
clk => queue.data_a[3].CLK
|
3083 |
|
|
clk => queue.data_a[4].CLK
|
3084 |
|
|
clk => queue.data_a[5].CLK
|
3085 |
|
|
clk => queue.data_a[6].CLK
|
3086 |
|
|
clk => queue.data_a[7].CLK
|
3087 |
|
|
clk => queue.data_a[8].CLK
|
3088 |
|
|
clk => queue.data_a[9].CLK
|
3089 |
|
|
clk => queue.waddr_a[0].CLK
|
3090 |
|
|
clk => queue.waddr_a[1].CLK
|
3091 |
|
|
clk => queue.waddr_a[2].CLK
|
3092 |
|
|
clk => queue.waddr_a[3].CLK
|
3093 |
|
|
clk => queue.waddr_a[4].CLK
|
3094 |
|
|
clk => always0~0.CLK
|
3095 |
|
|
clk => queue.CLK0
|
3096 |
|
|
|
3097 |
|
|
|
3098 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst
|
3099 |
|
|
din[0] => queue.data_a[0].DATAIN
|
3100 |
|
|
din[0] => queue.DATAIN
|
3101 |
|
|
wr_en => always0~0.DATAIN
|
3102 |
|
|
wr_en => always1~0.IN0
|
3103 |
|
|
wr_en => wr_ptr~4.OUTPUTSELECT
|
3104 |
|
|
wr_en => wr_ptr~3.OUTPUTSELECT
|
3105 |
|
|
wr_en => wr_ptr~2.OUTPUTSELECT
|
3106 |
|
|
wr_en => wr_ptr~1.OUTPUTSELECT
|
3107 |
|
|
wr_en => wr_ptr~0.OUTPUTSELECT
|
3108 |
|
|
wr_en => always1~1.IN0
|
3109 |
|
|
wr_en => queue.WE
|
3110 |
|
|
rd_en => always1~1.IN1
|
3111 |
|
|
rd_en => rd_ptr~4.OUTPUTSELECT
|
3112 |
|
|
rd_en => rd_ptr~3.OUTPUTSELECT
|
3113 |
|
|
rd_en => rd_ptr~2.OUTPUTSELECT
|
3114 |
|
|
rd_en => rd_ptr~1.OUTPUTSELECT
|
3115 |
|
|
rd_en => rd_ptr~0.OUTPUTSELECT
|
3116 |
|
|
rd_en => always1~0.IN1
|
3117 |
|
|
rd_en => dout[0]~reg0.ENA
|
3118 |
|
|
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3119 |
|
|
full <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
3120 |
|
|
nearly_full <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
|
3121 |
|
|
empty <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
|
3122 |
|
|
reset => depth~17.OUTPUTSELECT
|
3123 |
|
|
reset => depth~16.OUTPUTSELECT
|
3124 |
|
|
reset => depth~15.OUTPUTSELECT
|
3125 |
|
|
reset => depth~14.OUTPUTSELECT
|
3126 |
|
|
reset => depth~13.OUTPUTSELECT
|
3127 |
|
|
reset => depth~12.OUTPUTSELECT
|
3128 |
|
|
reset => wr_ptr~9.OUTPUTSELECT
|
3129 |
|
|
reset => wr_ptr~8.OUTPUTSELECT
|
3130 |
|
|
reset => wr_ptr~7.OUTPUTSELECT
|
3131 |
|
|
reset => wr_ptr~6.OUTPUTSELECT
|
3132 |
|
|
reset => wr_ptr~5.OUTPUTSELECT
|
3133 |
|
|
reset => rd_ptr~9.OUTPUTSELECT
|
3134 |
|
|
reset => rd_ptr~8.OUTPUTSELECT
|
3135 |
|
|
reset => rd_ptr~7.OUTPUTSELECT
|
3136 |
|
|
reset => rd_ptr~6.OUTPUTSELECT
|
3137 |
|
|
reset => rd_ptr~5.OUTPUTSELECT
|
3138 |
|
|
clk => dout[0]~reg0.CLK
|
3139 |
|
|
clk => rd_ptr[4].CLK
|
3140 |
|
|
clk => rd_ptr[3].CLK
|
3141 |
|
|
clk => rd_ptr[2].CLK
|
3142 |
|
|
clk => rd_ptr[1].CLK
|
3143 |
|
|
clk => rd_ptr[0].CLK
|
3144 |
|
|
clk => wr_ptr[4].CLK
|
3145 |
|
|
clk => wr_ptr[3].CLK
|
3146 |
|
|
clk => wr_ptr[2].CLK
|
3147 |
|
|
clk => wr_ptr[1].CLK
|
3148 |
|
|
clk => wr_ptr[0].CLK
|
3149 |
|
|
clk => depth[5].CLK
|
3150 |
|
|
clk => depth[4].CLK
|
3151 |
|
|
clk => depth[3].CLK
|
3152 |
|
|
clk => depth[2].CLK
|
3153 |
|
|
clk => depth[1].CLK
|
3154 |
|
|
clk => depth[0].CLK
|
3155 |
|
|
clk => queue.data_a[0].CLK
|
3156 |
|
|
clk => queue.waddr_a[0].CLK
|
3157 |
|
|
clk => queue.waddr_a[1].CLK
|
3158 |
|
|
clk => queue.waddr_a[2].CLK
|
3159 |
|
|
clk => queue.waddr_a[3].CLK
|
3160 |
|
|
clk => queue.waddr_a[4].CLK
|
3161 |
|
|
clk => always0~0.CLK
|
3162 |
|
|
clk => queue.CLK0
|
3163 |
|
|
|
3164 |
|
|
|
3165 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_Map_256x48_Inst
|
3166 |
|
|
clk => q[9]~reg0.CLK
|
3167 |
|
|
clk => q[8]~reg0.CLK
|
3168 |
|
|
clk => q[7]~reg0.CLK
|
3169 |
|
|
clk => q[6]~reg0.CLK
|
3170 |
|
|
clk => q[5]~reg0.CLK
|
3171 |
|
|
clk => q[4]~reg0.CLK
|
3172 |
|
|
clk => q[3]~reg0.CLK
|
3173 |
|
|
clk => q[2]~reg0.CLK
|
3174 |
|
|
clk => q[1]~reg0.CLK
|
3175 |
|
|
clk => q[0]~reg0.CLK
|
3176 |
|
|
clk => ram~19.CLK
|
3177 |
|
|
clk => ram~18.CLK
|
3178 |
|
|
clk => ram~17.CLK
|
3179 |
|
|
clk => ram~16.CLK
|
3180 |
|
|
clk => ram~15.CLK
|
3181 |
|
|
clk => ram~14.CLK
|
3182 |
|
|
clk => ram~13.CLK
|
3183 |
|
|
clk => ram~12.CLK
|
3184 |
|
|
clk => ram~11.CLK
|
3185 |
|
|
clk => ram~10.CLK
|
3186 |
|
|
clk => ram~9.CLK
|
3187 |
|
|
clk => ram~8.CLK
|
3188 |
|
|
clk => ram~7.CLK
|
3189 |
|
|
clk => ram~6.CLK
|
3190 |
|
|
clk => ram~5.CLK
|
3191 |
|
|
clk => ram~4.CLK
|
3192 |
|
|
clk => ram~3.CLK
|
3193 |
|
|
clk => ram~2.CLK
|
3194 |
|
|
clk => ram~1.CLK
|
3195 |
|
|
clk => ram~0.CLK
|
3196 |
|
|
clk => ram~20.CLK
|
3197 |
|
|
clk => ram.CLK0
|
3198 |
|
|
raddr[0] => ram.RADDR
|
3199 |
|
|
raddr[1] => ram.RADDR1
|
3200 |
|
|
raddr[2] => ram.RADDR2
|
3201 |
|
|
raddr[3] => ram.RADDR3
|
3202 |
|
|
raddr[4] => ram.RADDR4
|
3203 |
|
|
raddr[5] => ram.RADDR5
|
3204 |
|
|
raddr[6] => ram.RADDR6
|
3205 |
|
|
raddr[7] => ram.RADDR7
|
3206 |
|
|
raddr[8] => ram.RADDR8
|
3207 |
|
|
raddr[9] => ram.RADDR9
|
3208 |
|
|
waddr[0] => ram~9.DATAIN
|
3209 |
|
|
waddr[0] => ram.WADDR
|
3210 |
|
|
waddr[1] => ram~8.DATAIN
|
3211 |
|
|
waddr[1] => ram.WADDR1
|
3212 |
|
|
waddr[2] => ram~7.DATAIN
|
3213 |
|
|
waddr[2] => ram.WADDR2
|
3214 |
|
|
waddr[3] => ram~6.DATAIN
|
3215 |
|
|
waddr[3] => ram.WADDR3
|
3216 |
|
|
waddr[4] => ram~5.DATAIN
|
3217 |
|
|
waddr[4] => ram.WADDR4
|
3218 |
|
|
waddr[5] => ram~4.DATAIN
|
3219 |
|
|
waddr[5] => ram.WADDR5
|
3220 |
|
|
waddr[6] => ram~3.DATAIN
|
3221 |
|
|
waddr[6] => ram.WADDR6
|
3222 |
|
|
waddr[7] => ram~2.DATAIN
|
3223 |
|
|
waddr[7] => ram.WADDR7
|
3224 |
|
|
waddr[8] => ram~1.DATAIN
|
3225 |
|
|
waddr[8] => ram.WADDR8
|
3226 |
|
|
waddr[9] => ram~0.DATAIN
|
3227 |
|
|
waddr[9] => ram.WADDR9
|
3228 |
|
|
data[0] => ram~19.DATAIN
|
3229 |
|
|
data[0] => ram.DATAIN
|
3230 |
|
|
data[1] => ram~18.DATAIN
|
3231 |
|
|
data[1] => ram.DATAIN1
|
3232 |
|
|
data[2] => ram~17.DATAIN
|
3233 |
|
|
data[2] => ram.DATAIN2
|
3234 |
|
|
data[3] => ram~16.DATAIN
|
3235 |
|
|
data[3] => ram.DATAIN3
|
3236 |
|
|
data[4] => ram~15.DATAIN
|
3237 |
|
|
data[4] => ram.DATAIN4
|
3238 |
|
|
data[5] => ram~14.DATAIN
|
3239 |
|
|
data[5] => ram.DATAIN5
|
3240 |
|
|
data[6] => ram~13.DATAIN
|
3241 |
|
|
data[6] => ram.DATAIN6
|
3242 |
|
|
data[7] => ram~12.DATAIN
|
3243 |
|
|
data[7] => ram.DATAIN7
|
3244 |
|
|
data[8] => ram~11.DATAIN
|
3245 |
|
|
data[8] => ram.DATAIN8
|
3246 |
|
|
data[9] => ram~10.DATAIN
|
3247 |
|
|
data[9] => ram.DATAIN9
|
3248 |
|
|
we => ram~20.DATAIN
|
3249 |
|
|
we => ram.WE
|
3250 |
|
|
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3251 |
|
|
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3252 |
|
|
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3253 |
|
|
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3254 |
|
|
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3255 |
|
|
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3256 |
|
|
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3257 |
|
|
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3258 |
|
|
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3259 |
|
|
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3260 |
|
|
|
3261 |
|
|
|
3262 |
|
|
|LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst
|
3263 |
|
|
clk => q[9]~reg0.CLK
|
3264 |
|
|
clk => q[8]~reg0.CLK
|
3265 |
|
|
clk => q[7]~reg0.CLK
|
3266 |
|
|
clk => q[6]~reg0.CLK
|
3267 |
|
|
clk => q[5]~reg0.CLK
|
3268 |
|
|
clk => q[4]~reg0.CLK
|
3269 |
|
|
clk => q[3]~reg0.CLK
|
3270 |
|
|
clk => q[2]~reg0.CLK
|
3271 |
|
|
clk => q[1]~reg0.CLK
|
3272 |
|
|
clk => q[0]~reg0.CLK
|
3273 |
|
|
clk => ram~19.CLK
|
3274 |
|
|
clk => ram~18.CLK
|
3275 |
|
|
clk => ram~17.CLK
|
3276 |
|
|
clk => ram~16.CLK
|
3277 |
|
|
clk => ram~15.CLK
|
3278 |
|
|
clk => ram~14.CLK
|
3279 |
|
|
clk => ram~13.CLK
|
3280 |
|
|
clk => ram~12.CLK
|
3281 |
|
|
clk => ram~11.CLK
|
3282 |
|
|
clk => ram~10.CLK
|
3283 |
|
|
clk => ram~9.CLK
|
3284 |
|
|
clk => ram~8.CLK
|
3285 |
|
|
clk => ram~7.CLK
|
3286 |
|
|
clk => ram~6.CLK
|
3287 |
|
|
clk => ram~5.CLK
|
3288 |
|
|
clk => ram~4.CLK
|
3289 |
|
|
clk => ram~3.CLK
|
3290 |
|
|
clk => ram~2.CLK
|
3291 |
|
|
clk => ram~1.CLK
|
3292 |
|
|
clk => ram~0.CLK
|
3293 |
|
|
clk => ram~20.CLK
|
3294 |
|
|
clk => ram.CLK0
|
3295 |
|
|
raddr[0] => ram.RADDR
|
3296 |
|
|
raddr[1] => ram.RADDR1
|
3297 |
|
|
raddr[2] => ram.RADDR2
|
3298 |
|
|
raddr[3] => ram.RADDR3
|
3299 |
|
|
raddr[4] => ram.RADDR4
|
3300 |
|
|
raddr[5] => ram.RADDR5
|
3301 |
|
|
raddr[6] => ram.RADDR6
|
3302 |
|
|
raddr[7] => ram.RADDR7
|
3303 |
|
|
raddr[8] => ram.RADDR8
|
3304 |
|
|
raddr[9] => ram.RADDR9
|
3305 |
|
|
waddr[0] => ram~9.DATAIN
|
3306 |
|
|
waddr[0] => ram.WADDR
|
3307 |
|
|
waddr[1] => ram~8.DATAIN
|
3308 |
|
|
waddr[1] => ram.WADDR1
|
3309 |
|
|
waddr[2] => ram~7.DATAIN
|
3310 |
|
|
waddr[2] => ram.WADDR2
|
3311 |
|
|
waddr[3] => ram~6.DATAIN
|
3312 |
|
|
waddr[3] => ram.WADDR3
|
3313 |
|
|
waddr[4] => ram~5.DATAIN
|
3314 |
|
|
waddr[4] => ram.WADDR4
|
3315 |
|
|
waddr[5] => ram~4.DATAIN
|
3316 |
|
|
waddr[5] => ram.WADDR5
|
3317 |
|
|
waddr[6] => ram~3.DATAIN
|
3318 |
|
|
waddr[6] => ram.WADDR6
|
3319 |
|
|
waddr[7] => ram~2.DATAIN
|
3320 |
|
|
waddr[7] => ram.WADDR7
|
3321 |
|
|
waddr[8] => ram~1.DATAIN
|
3322 |
|
|
waddr[8] => ram.WADDR8
|
3323 |
|
|
waddr[9] => ram~0.DATAIN
|
3324 |
|
|
waddr[9] => ram.WADDR9
|
3325 |
|
|
data[0] => ram~19.DATAIN
|
3326 |
|
|
data[0] => ram.DATAIN
|
3327 |
|
|
data[1] => ram~18.DATAIN
|
3328 |
|
|
data[1] => ram.DATAIN1
|
3329 |
|
|
data[2] => ram~17.DATAIN
|
3330 |
|
|
data[2] => ram.DATAIN2
|
3331 |
|
|
data[3] => ram~16.DATAIN
|
3332 |
|
|
data[3] => ram.DATAIN3
|
3333 |
|
|
data[4] => ram~15.DATAIN
|
3334 |
|
|
data[4] => ram.DATAIN4
|
3335 |
|
|
data[5] => ram~14.DATAIN
|
3336 |
|
|
data[5] => ram.DATAIN5
|
3337 |
|
|
data[6] => ram~13.DATAIN
|
3338 |
|
|
data[6] => ram.DATAIN6
|
3339 |
|
|
data[7] => ram~12.DATAIN
|
3340 |
|
|
data[7] => ram.DATAIN7
|
3341 |
|
|
data[8] => ram~11.DATAIN
|
3342 |
|
|
data[8] => ram.DATAIN8
|
3343 |
|
|
data[9] => ram~10.DATAIN
|
3344 |
|
|
data[9] => ram.DATAIN9
|
3345 |
|
|
we => ram~20.DATAIN
|
3346 |
|
|
we => ram.WE
|
3347 |
|
|
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3348 |
|
|
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3349 |
|
|
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3350 |
|
|
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3351 |
|
|
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3352 |
|
|
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3353 |
|
|
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3354 |
|
|
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3355 |
|
|
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3356 |
|
|
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
3357 |
|
|
|
3358 |
|
|
|