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[/] [loadbalancer/] [trunk/] [db/] [altsyncram_94j1.tdf] - Blame information for rev 2

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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=4096 NUMWORDS_B=4096 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=48 WIDTH_B=48 WIDTHAD_A=12 WIDTHAD_B=12 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
2
--VERSION_BEGIN 7.2SP3 cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END
3
 
4
 
5
-- Copyright (C) 1991-2007 Altera Corporation
6
--  Your use of Altera Corporation's design tools, logic functions
7
--  and other software and tools, and its AMPP partner logic
8
--  functions, and any output files from any of the foregoing
9
--  (including device programming or simulation files), and any
10
--  associated documentation or information are expressly subject
11
--  to the terms and conditions of the Altera Program License
12
--  Subscription Agreement, Altera MegaCore Function License
13
--  Agreement, or other applicable license agreement, including,
14
--  without limitation, that your use is for the sole purpose of
15
--  programming logic devices manufactured by Altera and sold by
16
--  Altera or its authorized distributors.  Please refer to the
17
--  applicable agreement for further details.
18
 
19
 
20
FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
21
WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
22
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
23
 
24
--synthesis_resources = ram_bits (AUTO) 196608
25
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
26
 
27
SUBDESIGN altsyncram_94j1
28
(
29
        address_a[11..0]        :       input;
30
        address_b[11..0]        :       input;
31
        clock0  :       input;
32
        data_a[47..0]   :       input;
33
        q_b[47..0]      :       output;
34
        wren_a  :       input;
35
)
36
VARIABLE
37
        ram_block1a0 : stratixii_ram_block
38
                WITH (
39
                        CONNECTIVITY_CHECKING = "OFF",
40
                        DONT_POWER_OPTIMIZE = "ON",
41
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
42
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
43
                        OPERATION_MODE = "dual_port",
44
                        PORT_A_ADDRESS_WIDTH = 12,
45
                        PORT_A_DATA_WIDTH = 1,
46
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
47
                        PORT_A_FIRST_ADDRESS = 0,
48
                        PORT_A_FIRST_BIT_NUMBER = 0,
49
                        PORT_A_LAST_ADDRESS = 4095,
50
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
51
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
52
                        PORT_B_ADDRESS_CLOCK = "clock0",
53
                        PORT_B_ADDRESS_WIDTH = 12,
54
                        PORT_B_DATA_OUT_CLEAR = "none",
55
                        PORT_B_DATA_OUT_CLOCK = "none",
56
                        PORT_B_DATA_WIDTH = 1,
57
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
58
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
59
                        PORT_B_FIRST_ADDRESS = 0,
60
                        PORT_B_FIRST_BIT_NUMBER = 0,
61
                        PORT_B_LAST_ADDRESS = 4095,
62
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
63
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
64
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
65
                        RAM_BLOCK_TYPE = "AUTO"
66
                );
67
        ram_block1a1 : stratixii_ram_block
68
                WITH (
69
                        CONNECTIVITY_CHECKING = "OFF",
70
                        DONT_POWER_OPTIMIZE = "ON",
71
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
72
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
73
                        OPERATION_MODE = "dual_port",
74
                        PORT_A_ADDRESS_WIDTH = 12,
75
                        PORT_A_DATA_WIDTH = 1,
76
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
77
                        PORT_A_FIRST_ADDRESS = 0,
78
                        PORT_A_FIRST_BIT_NUMBER = 1,
79
                        PORT_A_LAST_ADDRESS = 4095,
80
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
81
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
82
                        PORT_B_ADDRESS_CLOCK = "clock0",
83
                        PORT_B_ADDRESS_WIDTH = 12,
84
                        PORT_B_DATA_OUT_CLEAR = "none",
85
                        PORT_B_DATA_OUT_CLOCK = "none",
86
                        PORT_B_DATA_WIDTH = 1,
87
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
88
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
89
                        PORT_B_FIRST_ADDRESS = 0,
90
                        PORT_B_FIRST_BIT_NUMBER = 1,
91
                        PORT_B_LAST_ADDRESS = 4095,
92
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
93
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
94
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
95
                        RAM_BLOCK_TYPE = "AUTO"
96
                );
97
        ram_block1a2 : stratixii_ram_block
98
                WITH (
99
                        CONNECTIVITY_CHECKING = "OFF",
100
                        DONT_POWER_OPTIMIZE = "ON",
101
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
102
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
103
                        OPERATION_MODE = "dual_port",
104
                        PORT_A_ADDRESS_WIDTH = 12,
105
                        PORT_A_DATA_WIDTH = 1,
106
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
107
                        PORT_A_FIRST_ADDRESS = 0,
108
                        PORT_A_FIRST_BIT_NUMBER = 2,
109
                        PORT_A_LAST_ADDRESS = 4095,
110
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
111
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
112
                        PORT_B_ADDRESS_CLOCK = "clock0",
113
                        PORT_B_ADDRESS_WIDTH = 12,
114
                        PORT_B_DATA_OUT_CLEAR = "none",
115
                        PORT_B_DATA_OUT_CLOCK = "none",
116
                        PORT_B_DATA_WIDTH = 1,
117
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
118
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
119
                        PORT_B_FIRST_ADDRESS = 0,
120
                        PORT_B_FIRST_BIT_NUMBER = 2,
121
                        PORT_B_LAST_ADDRESS = 4095,
122
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
123
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
124
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
125
                        RAM_BLOCK_TYPE = "AUTO"
126
                );
127
        ram_block1a3 : stratixii_ram_block
128
                WITH (
129
                        CONNECTIVITY_CHECKING = "OFF",
130
                        DONT_POWER_OPTIMIZE = "ON",
131
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
132
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
133
                        OPERATION_MODE = "dual_port",
134
                        PORT_A_ADDRESS_WIDTH = 12,
135
                        PORT_A_DATA_WIDTH = 1,
136
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
137
                        PORT_A_FIRST_ADDRESS = 0,
138
                        PORT_A_FIRST_BIT_NUMBER = 3,
139
                        PORT_A_LAST_ADDRESS = 4095,
140
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
141
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
142
                        PORT_B_ADDRESS_CLOCK = "clock0",
143
                        PORT_B_ADDRESS_WIDTH = 12,
144
                        PORT_B_DATA_OUT_CLEAR = "none",
145
                        PORT_B_DATA_OUT_CLOCK = "none",
146
                        PORT_B_DATA_WIDTH = 1,
147
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
148
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
149
                        PORT_B_FIRST_ADDRESS = 0,
150
                        PORT_B_FIRST_BIT_NUMBER = 3,
151
                        PORT_B_LAST_ADDRESS = 4095,
152
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
153
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
154
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
155
                        RAM_BLOCK_TYPE = "AUTO"
156
                );
157
        ram_block1a4 : stratixii_ram_block
158
                WITH (
159
                        CONNECTIVITY_CHECKING = "OFF",
160
                        DONT_POWER_OPTIMIZE = "ON",
161
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
162
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
163
                        OPERATION_MODE = "dual_port",
164
                        PORT_A_ADDRESS_WIDTH = 12,
165
                        PORT_A_DATA_WIDTH = 1,
166
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
167
                        PORT_A_FIRST_ADDRESS = 0,
168
                        PORT_A_FIRST_BIT_NUMBER = 4,
169
                        PORT_A_LAST_ADDRESS = 4095,
170
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
171
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
172
                        PORT_B_ADDRESS_CLOCK = "clock0",
173
                        PORT_B_ADDRESS_WIDTH = 12,
174
                        PORT_B_DATA_OUT_CLEAR = "none",
175
                        PORT_B_DATA_OUT_CLOCK = "none",
176
                        PORT_B_DATA_WIDTH = 1,
177
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
178
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
179
                        PORT_B_FIRST_ADDRESS = 0,
180
                        PORT_B_FIRST_BIT_NUMBER = 4,
181
                        PORT_B_LAST_ADDRESS = 4095,
182
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
183
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
184
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
185
                        RAM_BLOCK_TYPE = "AUTO"
186
                );
187
        ram_block1a5 : stratixii_ram_block
188
                WITH (
189
                        CONNECTIVITY_CHECKING = "OFF",
190
                        DONT_POWER_OPTIMIZE = "ON",
191
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
192
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
193
                        OPERATION_MODE = "dual_port",
194
                        PORT_A_ADDRESS_WIDTH = 12,
195
                        PORT_A_DATA_WIDTH = 1,
196
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
197
                        PORT_A_FIRST_ADDRESS = 0,
198
                        PORT_A_FIRST_BIT_NUMBER = 5,
199
                        PORT_A_LAST_ADDRESS = 4095,
200
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
201
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
202
                        PORT_B_ADDRESS_CLOCK = "clock0",
203
                        PORT_B_ADDRESS_WIDTH = 12,
204
                        PORT_B_DATA_OUT_CLEAR = "none",
205
                        PORT_B_DATA_OUT_CLOCK = "none",
206
                        PORT_B_DATA_WIDTH = 1,
207
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
208
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
209
                        PORT_B_FIRST_ADDRESS = 0,
210
                        PORT_B_FIRST_BIT_NUMBER = 5,
211
                        PORT_B_LAST_ADDRESS = 4095,
212
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
213
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
214
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
215
                        RAM_BLOCK_TYPE = "AUTO"
216
                );
217
        ram_block1a6 : stratixii_ram_block
218
                WITH (
219
                        CONNECTIVITY_CHECKING = "OFF",
220
                        DONT_POWER_OPTIMIZE = "ON",
221
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
222
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
223
                        OPERATION_MODE = "dual_port",
224
                        PORT_A_ADDRESS_WIDTH = 12,
225
                        PORT_A_DATA_WIDTH = 1,
226
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
227
                        PORT_A_FIRST_ADDRESS = 0,
228
                        PORT_A_FIRST_BIT_NUMBER = 6,
229
                        PORT_A_LAST_ADDRESS = 4095,
230
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
231
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
232
                        PORT_B_ADDRESS_CLOCK = "clock0",
233
                        PORT_B_ADDRESS_WIDTH = 12,
234
                        PORT_B_DATA_OUT_CLEAR = "none",
235
                        PORT_B_DATA_OUT_CLOCK = "none",
236
                        PORT_B_DATA_WIDTH = 1,
237
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
238
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
239
                        PORT_B_FIRST_ADDRESS = 0,
240
                        PORT_B_FIRST_BIT_NUMBER = 6,
241
                        PORT_B_LAST_ADDRESS = 4095,
242
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
243
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
244
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
245
                        RAM_BLOCK_TYPE = "AUTO"
246
                );
247
        ram_block1a7 : stratixii_ram_block
248
                WITH (
249
                        CONNECTIVITY_CHECKING = "OFF",
250
                        DONT_POWER_OPTIMIZE = "ON",
251
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
252
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
253
                        OPERATION_MODE = "dual_port",
254
                        PORT_A_ADDRESS_WIDTH = 12,
255
                        PORT_A_DATA_WIDTH = 1,
256
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
257
                        PORT_A_FIRST_ADDRESS = 0,
258
                        PORT_A_FIRST_BIT_NUMBER = 7,
259
                        PORT_A_LAST_ADDRESS = 4095,
260
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
261
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
262
                        PORT_B_ADDRESS_CLOCK = "clock0",
263
                        PORT_B_ADDRESS_WIDTH = 12,
264
                        PORT_B_DATA_OUT_CLEAR = "none",
265
                        PORT_B_DATA_OUT_CLOCK = "none",
266
                        PORT_B_DATA_WIDTH = 1,
267
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
268
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
269
                        PORT_B_FIRST_ADDRESS = 0,
270
                        PORT_B_FIRST_BIT_NUMBER = 7,
271
                        PORT_B_LAST_ADDRESS = 4095,
272
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
273
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
274
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
275
                        RAM_BLOCK_TYPE = "AUTO"
276
                );
277
        ram_block1a8 : stratixii_ram_block
278
                WITH (
279
                        CONNECTIVITY_CHECKING = "OFF",
280
                        DONT_POWER_OPTIMIZE = "ON",
281
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
282
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
283
                        OPERATION_MODE = "dual_port",
284
                        PORT_A_ADDRESS_WIDTH = 12,
285
                        PORT_A_DATA_WIDTH = 1,
286
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
287
                        PORT_A_FIRST_ADDRESS = 0,
288
                        PORT_A_FIRST_BIT_NUMBER = 8,
289
                        PORT_A_LAST_ADDRESS = 4095,
290
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
291
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
292
                        PORT_B_ADDRESS_CLOCK = "clock0",
293
                        PORT_B_ADDRESS_WIDTH = 12,
294
                        PORT_B_DATA_OUT_CLEAR = "none",
295
                        PORT_B_DATA_OUT_CLOCK = "none",
296
                        PORT_B_DATA_WIDTH = 1,
297
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
298
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
299
                        PORT_B_FIRST_ADDRESS = 0,
300
                        PORT_B_FIRST_BIT_NUMBER = 8,
301
                        PORT_B_LAST_ADDRESS = 4095,
302
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
303
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
304
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
305
                        RAM_BLOCK_TYPE = "AUTO"
306
                );
307
        ram_block1a9 : stratixii_ram_block
308
                WITH (
309
                        CONNECTIVITY_CHECKING = "OFF",
310
                        DONT_POWER_OPTIMIZE = "ON",
311
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
312
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
313
                        OPERATION_MODE = "dual_port",
314
                        PORT_A_ADDRESS_WIDTH = 12,
315
                        PORT_A_DATA_WIDTH = 1,
316
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
317
                        PORT_A_FIRST_ADDRESS = 0,
318
                        PORT_A_FIRST_BIT_NUMBER = 9,
319
                        PORT_A_LAST_ADDRESS = 4095,
320
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
321
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
322
                        PORT_B_ADDRESS_CLOCK = "clock0",
323
                        PORT_B_ADDRESS_WIDTH = 12,
324
                        PORT_B_DATA_OUT_CLEAR = "none",
325
                        PORT_B_DATA_OUT_CLOCK = "none",
326
                        PORT_B_DATA_WIDTH = 1,
327
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
328
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
329
                        PORT_B_FIRST_ADDRESS = 0,
330
                        PORT_B_FIRST_BIT_NUMBER = 9,
331
                        PORT_B_LAST_ADDRESS = 4095,
332
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
333
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
334
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
335
                        RAM_BLOCK_TYPE = "AUTO"
336
                );
337
        ram_block1a10 : stratixii_ram_block
338
                WITH (
339
                        CONNECTIVITY_CHECKING = "OFF",
340
                        DONT_POWER_OPTIMIZE = "ON",
341
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
342
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
343
                        OPERATION_MODE = "dual_port",
344
                        PORT_A_ADDRESS_WIDTH = 12,
345
                        PORT_A_DATA_WIDTH = 1,
346
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
347
                        PORT_A_FIRST_ADDRESS = 0,
348
                        PORT_A_FIRST_BIT_NUMBER = 10,
349
                        PORT_A_LAST_ADDRESS = 4095,
350
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
351
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
352
                        PORT_B_ADDRESS_CLOCK = "clock0",
353
                        PORT_B_ADDRESS_WIDTH = 12,
354
                        PORT_B_DATA_OUT_CLEAR = "none",
355
                        PORT_B_DATA_OUT_CLOCK = "none",
356
                        PORT_B_DATA_WIDTH = 1,
357
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
358
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
359
                        PORT_B_FIRST_ADDRESS = 0,
360
                        PORT_B_FIRST_BIT_NUMBER = 10,
361
                        PORT_B_LAST_ADDRESS = 4095,
362
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
363
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
364
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
365
                        RAM_BLOCK_TYPE = "AUTO"
366
                );
367
        ram_block1a11 : stratixii_ram_block
368
                WITH (
369
                        CONNECTIVITY_CHECKING = "OFF",
370
                        DONT_POWER_OPTIMIZE = "ON",
371
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
372
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
373
                        OPERATION_MODE = "dual_port",
374
                        PORT_A_ADDRESS_WIDTH = 12,
375
                        PORT_A_DATA_WIDTH = 1,
376
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
377
                        PORT_A_FIRST_ADDRESS = 0,
378
                        PORT_A_FIRST_BIT_NUMBER = 11,
379
                        PORT_A_LAST_ADDRESS = 4095,
380
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
381
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
382
                        PORT_B_ADDRESS_CLOCK = "clock0",
383
                        PORT_B_ADDRESS_WIDTH = 12,
384
                        PORT_B_DATA_OUT_CLEAR = "none",
385
                        PORT_B_DATA_OUT_CLOCK = "none",
386
                        PORT_B_DATA_WIDTH = 1,
387
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
388
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
389
                        PORT_B_FIRST_ADDRESS = 0,
390
                        PORT_B_FIRST_BIT_NUMBER = 11,
391
                        PORT_B_LAST_ADDRESS = 4095,
392
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
393
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
394
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
395
                        RAM_BLOCK_TYPE = "AUTO"
396
                );
397
        ram_block1a12 : stratixii_ram_block
398
                WITH (
399
                        CONNECTIVITY_CHECKING = "OFF",
400
                        DONT_POWER_OPTIMIZE = "ON",
401
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
402
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
403
                        OPERATION_MODE = "dual_port",
404
                        PORT_A_ADDRESS_WIDTH = 12,
405
                        PORT_A_DATA_WIDTH = 1,
406
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
407
                        PORT_A_FIRST_ADDRESS = 0,
408
                        PORT_A_FIRST_BIT_NUMBER = 12,
409
                        PORT_A_LAST_ADDRESS = 4095,
410
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
411
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
412
                        PORT_B_ADDRESS_CLOCK = "clock0",
413
                        PORT_B_ADDRESS_WIDTH = 12,
414
                        PORT_B_DATA_OUT_CLEAR = "none",
415
                        PORT_B_DATA_OUT_CLOCK = "none",
416
                        PORT_B_DATA_WIDTH = 1,
417
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
418
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
419
                        PORT_B_FIRST_ADDRESS = 0,
420
                        PORT_B_FIRST_BIT_NUMBER = 12,
421
                        PORT_B_LAST_ADDRESS = 4095,
422
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
423
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
424
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
425
                        RAM_BLOCK_TYPE = "AUTO"
426
                );
427
        ram_block1a13 : stratixii_ram_block
428
                WITH (
429
                        CONNECTIVITY_CHECKING = "OFF",
430
                        DONT_POWER_OPTIMIZE = "ON",
431
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
432
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
433
                        OPERATION_MODE = "dual_port",
434
                        PORT_A_ADDRESS_WIDTH = 12,
435
                        PORT_A_DATA_WIDTH = 1,
436
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
437
                        PORT_A_FIRST_ADDRESS = 0,
438
                        PORT_A_FIRST_BIT_NUMBER = 13,
439
                        PORT_A_LAST_ADDRESS = 4095,
440
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
441
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
442
                        PORT_B_ADDRESS_CLOCK = "clock0",
443
                        PORT_B_ADDRESS_WIDTH = 12,
444
                        PORT_B_DATA_OUT_CLEAR = "none",
445
                        PORT_B_DATA_OUT_CLOCK = "none",
446
                        PORT_B_DATA_WIDTH = 1,
447
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
448
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
449
                        PORT_B_FIRST_ADDRESS = 0,
450
                        PORT_B_FIRST_BIT_NUMBER = 13,
451
                        PORT_B_LAST_ADDRESS = 4095,
452
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
453
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
454
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
455
                        RAM_BLOCK_TYPE = "AUTO"
456
                );
457
        ram_block1a14 : stratixii_ram_block
458
                WITH (
459
                        CONNECTIVITY_CHECKING = "OFF",
460
                        DONT_POWER_OPTIMIZE = "ON",
461
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
462
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
463
                        OPERATION_MODE = "dual_port",
464
                        PORT_A_ADDRESS_WIDTH = 12,
465
                        PORT_A_DATA_WIDTH = 1,
466
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
467
                        PORT_A_FIRST_ADDRESS = 0,
468
                        PORT_A_FIRST_BIT_NUMBER = 14,
469
                        PORT_A_LAST_ADDRESS = 4095,
470
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
471
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
472
                        PORT_B_ADDRESS_CLOCK = "clock0",
473
                        PORT_B_ADDRESS_WIDTH = 12,
474
                        PORT_B_DATA_OUT_CLEAR = "none",
475
                        PORT_B_DATA_OUT_CLOCK = "none",
476
                        PORT_B_DATA_WIDTH = 1,
477
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
478
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
479
                        PORT_B_FIRST_ADDRESS = 0,
480
                        PORT_B_FIRST_BIT_NUMBER = 14,
481
                        PORT_B_LAST_ADDRESS = 4095,
482
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
483
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
484
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
485
                        RAM_BLOCK_TYPE = "AUTO"
486
                );
487
        ram_block1a15 : stratixii_ram_block
488
                WITH (
489
                        CONNECTIVITY_CHECKING = "OFF",
490
                        DONT_POWER_OPTIMIZE = "ON",
491
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
492
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
493
                        OPERATION_MODE = "dual_port",
494
                        PORT_A_ADDRESS_WIDTH = 12,
495
                        PORT_A_DATA_WIDTH = 1,
496
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
497
                        PORT_A_FIRST_ADDRESS = 0,
498
                        PORT_A_FIRST_BIT_NUMBER = 15,
499
                        PORT_A_LAST_ADDRESS = 4095,
500
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
501
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
502
                        PORT_B_ADDRESS_CLOCK = "clock0",
503
                        PORT_B_ADDRESS_WIDTH = 12,
504
                        PORT_B_DATA_OUT_CLEAR = "none",
505
                        PORT_B_DATA_OUT_CLOCK = "none",
506
                        PORT_B_DATA_WIDTH = 1,
507
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
508
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
509
                        PORT_B_FIRST_ADDRESS = 0,
510
                        PORT_B_FIRST_BIT_NUMBER = 15,
511
                        PORT_B_LAST_ADDRESS = 4095,
512
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
513
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
514
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
515
                        RAM_BLOCK_TYPE = "AUTO"
516
                );
517
        ram_block1a16 : stratixii_ram_block
518
                WITH (
519
                        CONNECTIVITY_CHECKING = "OFF",
520
                        DONT_POWER_OPTIMIZE = "ON",
521
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
522
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
523
                        OPERATION_MODE = "dual_port",
524
                        PORT_A_ADDRESS_WIDTH = 12,
525
                        PORT_A_DATA_WIDTH = 1,
526
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
527
                        PORT_A_FIRST_ADDRESS = 0,
528
                        PORT_A_FIRST_BIT_NUMBER = 16,
529
                        PORT_A_LAST_ADDRESS = 4095,
530
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
531
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
532
                        PORT_B_ADDRESS_CLOCK = "clock0",
533
                        PORT_B_ADDRESS_WIDTH = 12,
534
                        PORT_B_DATA_OUT_CLEAR = "none",
535
                        PORT_B_DATA_OUT_CLOCK = "none",
536
                        PORT_B_DATA_WIDTH = 1,
537
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
538
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
539
                        PORT_B_FIRST_ADDRESS = 0,
540
                        PORT_B_FIRST_BIT_NUMBER = 16,
541
                        PORT_B_LAST_ADDRESS = 4095,
542
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
543
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
544
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
545
                        RAM_BLOCK_TYPE = "AUTO"
546
                );
547
        ram_block1a17 : stratixii_ram_block
548
                WITH (
549
                        CONNECTIVITY_CHECKING = "OFF",
550
                        DONT_POWER_OPTIMIZE = "ON",
551
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
552
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
553
                        OPERATION_MODE = "dual_port",
554
                        PORT_A_ADDRESS_WIDTH = 12,
555
                        PORT_A_DATA_WIDTH = 1,
556
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
557
                        PORT_A_FIRST_ADDRESS = 0,
558
                        PORT_A_FIRST_BIT_NUMBER = 17,
559
                        PORT_A_LAST_ADDRESS = 4095,
560
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
561
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
562
                        PORT_B_ADDRESS_CLOCK = "clock0",
563
                        PORT_B_ADDRESS_WIDTH = 12,
564
                        PORT_B_DATA_OUT_CLEAR = "none",
565
                        PORT_B_DATA_OUT_CLOCK = "none",
566
                        PORT_B_DATA_WIDTH = 1,
567
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
568
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
569
                        PORT_B_FIRST_ADDRESS = 0,
570
                        PORT_B_FIRST_BIT_NUMBER = 17,
571
                        PORT_B_LAST_ADDRESS = 4095,
572
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
573
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
574
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
575
                        RAM_BLOCK_TYPE = "AUTO"
576
                );
577
        ram_block1a18 : stratixii_ram_block
578
                WITH (
579
                        CONNECTIVITY_CHECKING = "OFF",
580
                        DONT_POWER_OPTIMIZE = "ON",
581
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
582
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
583
                        OPERATION_MODE = "dual_port",
584
                        PORT_A_ADDRESS_WIDTH = 12,
585
                        PORT_A_DATA_WIDTH = 1,
586
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
587
                        PORT_A_FIRST_ADDRESS = 0,
588
                        PORT_A_FIRST_BIT_NUMBER = 18,
589
                        PORT_A_LAST_ADDRESS = 4095,
590
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
591
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
592
                        PORT_B_ADDRESS_CLOCK = "clock0",
593
                        PORT_B_ADDRESS_WIDTH = 12,
594
                        PORT_B_DATA_OUT_CLEAR = "none",
595
                        PORT_B_DATA_OUT_CLOCK = "none",
596
                        PORT_B_DATA_WIDTH = 1,
597
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
598
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
599
                        PORT_B_FIRST_ADDRESS = 0,
600
                        PORT_B_FIRST_BIT_NUMBER = 18,
601
                        PORT_B_LAST_ADDRESS = 4095,
602
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
603
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
604
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
605
                        RAM_BLOCK_TYPE = "AUTO"
606
                );
607
        ram_block1a19 : stratixii_ram_block
608
                WITH (
609
                        CONNECTIVITY_CHECKING = "OFF",
610
                        DONT_POWER_OPTIMIZE = "ON",
611
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
612
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
613
                        OPERATION_MODE = "dual_port",
614
                        PORT_A_ADDRESS_WIDTH = 12,
615
                        PORT_A_DATA_WIDTH = 1,
616
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
617
                        PORT_A_FIRST_ADDRESS = 0,
618
                        PORT_A_FIRST_BIT_NUMBER = 19,
619
                        PORT_A_LAST_ADDRESS = 4095,
620
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
621
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
622
                        PORT_B_ADDRESS_CLOCK = "clock0",
623
                        PORT_B_ADDRESS_WIDTH = 12,
624
                        PORT_B_DATA_OUT_CLEAR = "none",
625
                        PORT_B_DATA_OUT_CLOCK = "none",
626
                        PORT_B_DATA_WIDTH = 1,
627
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
628
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
629
                        PORT_B_FIRST_ADDRESS = 0,
630
                        PORT_B_FIRST_BIT_NUMBER = 19,
631
                        PORT_B_LAST_ADDRESS = 4095,
632
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
633
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
634
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
635
                        RAM_BLOCK_TYPE = "AUTO"
636
                );
637
        ram_block1a20 : stratixii_ram_block
638
                WITH (
639
                        CONNECTIVITY_CHECKING = "OFF",
640
                        DONT_POWER_OPTIMIZE = "ON",
641
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
642
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
643
                        OPERATION_MODE = "dual_port",
644
                        PORT_A_ADDRESS_WIDTH = 12,
645
                        PORT_A_DATA_WIDTH = 1,
646
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
647
                        PORT_A_FIRST_ADDRESS = 0,
648
                        PORT_A_FIRST_BIT_NUMBER = 20,
649
                        PORT_A_LAST_ADDRESS = 4095,
650
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
651
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
652
                        PORT_B_ADDRESS_CLOCK = "clock0",
653
                        PORT_B_ADDRESS_WIDTH = 12,
654
                        PORT_B_DATA_OUT_CLEAR = "none",
655
                        PORT_B_DATA_OUT_CLOCK = "none",
656
                        PORT_B_DATA_WIDTH = 1,
657
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
658
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
659
                        PORT_B_FIRST_ADDRESS = 0,
660
                        PORT_B_FIRST_BIT_NUMBER = 20,
661
                        PORT_B_LAST_ADDRESS = 4095,
662
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
663
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
664
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
665
                        RAM_BLOCK_TYPE = "AUTO"
666
                );
667
        ram_block1a21 : stratixii_ram_block
668
                WITH (
669
                        CONNECTIVITY_CHECKING = "OFF",
670
                        DONT_POWER_OPTIMIZE = "ON",
671
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
672
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
673
                        OPERATION_MODE = "dual_port",
674
                        PORT_A_ADDRESS_WIDTH = 12,
675
                        PORT_A_DATA_WIDTH = 1,
676
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
677
                        PORT_A_FIRST_ADDRESS = 0,
678
                        PORT_A_FIRST_BIT_NUMBER = 21,
679
                        PORT_A_LAST_ADDRESS = 4095,
680
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
681
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
682
                        PORT_B_ADDRESS_CLOCK = "clock0",
683
                        PORT_B_ADDRESS_WIDTH = 12,
684
                        PORT_B_DATA_OUT_CLEAR = "none",
685
                        PORT_B_DATA_OUT_CLOCK = "none",
686
                        PORT_B_DATA_WIDTH = 1,
687
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
688
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
689
                        PORT_B_FIRST_ADDRESS = 0,
690
                        PORT_B_FIRST_BIT_NUMBER = 21,
691
                        PORT_B_LAST_ADDRESS = 4095,
692
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
693
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
694
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
695
                        RAM_BLOCK_TYPE = "AUTO"
696
                );
697
        ram_block1a22 : stratixii_ram_block
698
                WITH (
699
                        CONNECTIVITY_CHECKING = "OFF",
700
                        DONT_POWER_OPTIMIZE = "ON",
701
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
702
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
703
                        OPERATION_MODE = "dual_port",
704
                        PORT_A_ADDRESS_WIDTH = 12,
705
                        PORT_A_DATA_WIDTH = 1,
706
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
707
                        PORT_A_FIRST_ADDRESS = 0,
708
                        PORT_A_FIRST_BIT_NUMBER = 22,
709
                        PORT_A_LAST_ADDRESS = 4095,
710
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
711
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
712
                        PORT_B_ADDRESS_CLOCK = "clock0",
713
                        PORT_B_ADDRESS_WIDTH = 12,
714
                        PORT_B_DATA_OUT_CLEAR = "none",
715
                        PORT_B_DATA_OUT_CLOCK = "none",
716
                        PORT_B_DATA_WIDTH = 1,
717
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
718
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
719
                        PORT_B_FIRST_ADDRESS = 0,
720
                        PORT_B_FIRST_BIT_NUMBER = 22,
721
                        PORT_B_LAST_ADDRESS = 4095,
722
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
723
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
724
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
725
                        RAM_BLOCK_TYPE = "AUTO"
726
                );
727
        ram_block1a23 : stratixii_ram_block
728
                WITH (
729
                        CONNECTIVITY_CHECKING = "OFF",
730
                        DONT_POWER_OPTIMIZE = "ON",
731
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
732
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
733
                        OPERATION_MODE = "dual_port",
734
                        PORT_A_ADDRESS_WIDTH = 12,
735
                        PORT_A_DATA_WIDTH = 1,
736
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
737
                        PORT_A_FIRST_ADDRESS = 0,
738
                        PORT_A_FIRST_BIT_NUMBER = 23,
739
                        PORT_A_LAST_ADDRESS = 4095,
740
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
741
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
742
                        PORT_B_ADDRESS_CLOCK = "clock0",
743
                        PORT_B_ADDRESS_WIDTH = 12,
744
                        PORT_B_DATA_OUT_CLEAR = "none",
745
                        PORT_B_DATA_OUT_CLOCK = "none",
746
                        PORT_B_DATA_WIDTH = 1,
747
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
748
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
749
                        PORT_B_FIRST_ADDRESS = 0,
750
                        PORT_B_FIRST_BIT_NUMBER = 23,
751
                        PORT_B_LAST_ADDRESS = 4095,
752
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
753
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
754
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
755
                        RAM_BLOCK_TYPE = "AUTO"
756
                );
757
        ram_block1a24 : stratixii_ram_block
758
                WITH (
759
                        CONNECTIVITY_CHECKING = "OFF",
760
                        DONT_POWER_OPTIMIZE = "ON",
761
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
762
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
763
                        OPERATION_MODE = "dual_port",
764
                        PORT_A_ADDRESS_WIDTH = 12,
765
                        PORT_A_DATA_WIDTH = 1,
766
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
767
                        PORT_A_FIRST_ADDRESS = 0,
768
                        PORT_A_FIRST_BIT_NUMBER = 24,
769
                        PORT_A_LAST_ADDRESS = 4095,
770
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
771
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
772
                        PORT_B_ADDRESS_CLOCK = "clock0",
773
                        PORT_B_ADDRESS_WIDTH = 12,
774
                        PORT_B_DATA_OUT_CLEAR = "none",
775
                        PORT_B_DATA_OUT_CLOCK = "none",
776
                        PORT_B_DATA_WIDTH = 1,
777
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
778
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
779
                        PORT_B_FIRST_ADDRESS = 0,
780
                        PORT_B_FIRST_BIT_NUMBER = 24,
781
                        PORT_B_LAST_ADDRESS = 4095,
782
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
783
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
784
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
785
                        RAM_BLOCK_TYPE = "AUTO"
786
                );
787
        ram_block1a25 : stratixii_ram_block
788
                WITH (
789
                        CONNECTIVITY_CHECKING = "OFF",
790
                        DONT_POWER_OPTIMIZE = "ON",
791
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
792
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
793
                        OPERATION_MODE = "dual_port",
794
                        PORT_A_ADDRESS_WIDTH = 12,
795
                        PORT_A_DATA_WIDTH = 1,
796
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
797
                        PORT_A_FIRST_ADDRESS = 0,
798
                        PORT_A_FIRST_BIT_NUMBER = 25,
799
                        PORT_A_LAST_ADDRESS = 4095,
800
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
801
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
802
                        PORT_B_ADDRESS_CLOCK = "clock0",
803
                        PORT_B_ADDRESS_WIDTH = 12,
804
                        PORT_B_DATA_OUT_CLEAR = "none",
805
                        PORT_B_DATA_OUT_CLOCK = "none",
806
                        PORT_B_DATA_WIDTH = 1,
807
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
808
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
809
                        PORT_B_FIRST_ADDRESS = 0,
810
                        PORT_B_FIRST_BIT_NUMBER = 25,
811
                        PORT_B_LAST_ADDRESS = 4095,
812
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
813
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
814
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
815
                        RAM_BLOCK_TYPE = "AUTO"
816
                );
817
        ram_block1a26 : stratixii_ram_block
818
                WITH (
819
                        CONNECTIVITY_CHECKING = "OFF",
820
                        DONT_POWER_OPTIMIZE = "ON",
821
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
822
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
823
                        OPERATION_MODE = "dual_port",
824
                        PORT_A_ADDRESS_WIDTH = 12,
825
                        PORT_A_DATA_WIDTH = 1,
826
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
827
                        PORT_A_FIRST_ADDRESS = 0,
828
                        PORT_A_FIRST_BIT_NUMBER = 26,
829
                        PORT_A_LAST_ADDRESS = 4095,
830
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
831
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
832
                        PORT_B_ADDRESS_CLOCK = "clock0",
833
                        PORT_B_ADDRESS_WIDTH = 12,
834
                        PORT_B_DATA_OUT_CLEAR = "none",
835
                        PORT_B_DATA_OUT_CLOCK = "none",
836
                        PORT_B_DATA_WIDTH = 1,
837
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
838
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
839
                        PORT_B_FIRST_ADDRESS = 0,
840
                        PORT_B_FIRST_BIT_NUMBER = 26,
841
                        PORT_B_LAST_ADDRESS = 4095,
842
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
843
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
844
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
845
                        RAM_BLOCK_TYPE = "AUTO"
846
                );
847
        ram_block1a27 : stratixii_ram_block
848
                WITH (
849
                        CONNECTIVITY_CHECKING = "OFF",
850
                        DONT_POWER_OPTIMIZE = "ON",
851
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
852
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
853
                        OPERATION_MODE = "dual_port",
854
                        PORT_A_ADDRESS_WIDTH = 12,
855
                        PORT_A_DATA_WIDTH = 1,
856
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
857
                        PORT_A_FIRST_ADDRESS = 0,
858
                        PORT_A_FIRST_BIT_NUMBER = 27,
859
                        PORT_A_LAST_ADDRESS = 4095,
860
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
861
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
862
                        PORT_B_ADDRESS_CLOCK = "clock0",
863
                        PORT_B_ADDRESS_WIDTH = 12,
864
                        PORT_B_DATA_OUT_CLEAR = "none",
865
                        PORT_B_DATA_OUT_CLOCK = "none",
866
                        PORT_B_DATA_WIDTH = 1,
867
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
868
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
869
                        PORT_B_FIRST_ADDRESS = 0,
870
                        PORT_B_FIRST_BIT_NUMBER = 27,
871
                        PORT_B_LAST_ADDRESS = 4095,
872
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
873
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
874
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
875
                        RAM_BLOCK_TYPE = "AUTO"
876
                );
877
        ram_block1a28 : stratixii_ram_block
878
                WITH (
879
                        CONNECTIVITY_CHECKING = "OFF",
880
                        DONT_POWER_OPTIMIZE = "ON",
881
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
882
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
883
                        OPERATION_MODE = "dual_port",
884
                        PORT_A_ADDRESS_WIDTH = 12,
885
                        PORT_A_DATA_WIDTH = 1,
886
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
887
                        PORT_A_FIRST_ADDRESS = 0,
888
                        PORT_A_FIRST_BIT_NUMBER = 28,
889
                        PORT_A_LAST_ADDRESS = 4095,
890
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
891
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
892
                        PORT_B_ADDRESS_CLOCK = "clock0",
893
                        PORT_B_ADDRESS_WIDTH = 12,
894
                        PORT_B_DATA_OUT_CLEAR = "none",
895
                        PORT_B_DATA_OUT_CLOCK = "none",
896
                        PORT_B_DATA_WIDTH = 1,
897
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
898
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
899
                        PORT_B_FIRST_ADDRESS = 0,
900
                        PORT_B_FIRST_BIT_NUMBER = 28,
901
                        PORT_B_LAST_ADDRESS = 4095,
902
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
903
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
904
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
905
                        RAM_BLOCK_TYPE = "AUTO"
906
                );
907
        ram_block1a29 : stratixii_ram_block
908
                WITH (
909
                        CONNECTIVITY_CHECKING = "OFF",
910
                        DONT_POWER_OPTIMIZE = "ON",
911
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
912
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
913
                        OPERATION_MODE = "dual_port",
914
                        PORT_A_ADDRESS_WIDTH = 12,
915
                        PORT_A_DATA_WIDTH = 1,
916
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
917
                        PORT_A_FIRST_ADDRESS = 0,
918
                        PORT_A_FIRST_BIT_NUMBER = 29,
919
                        PORT_A_LAST_ADDRESS = 4095,
920
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
921
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
922
                        PORT_B_ADDRESS_CLOCK = "clock0",
923
                        PORT_B_ADDRESS_WIDTH = 12,
924
                        PORT_B_DATA_OUT_CLEAR = "none",
925
                        PORT_B_DATA_OUT_CLOCK = "none",
926
                        PORT_B_DATA_WIDTH = 1,
927
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
928
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
929
                        PORT_B_FIRST_ADDRESS = 0,
930
                        PORT_B_FIRST_BIT_NUMBER = 29,
931
                        PORT_B_LAST_ADDRESS = 4095,
932
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
933
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
934
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
935
                        RAM_BLOCK_TYPE = "AUTO"
936
                );
937
        ram_block1a30 : stratixii_ram_block
938
                WITH (
939
                        CONNECTIVITY_CHECKING = "OFF",
940
                        DONT_POWER_OPTIMIZE = "ON",
941
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
942
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
943
                        OPERATION_MODE = "dual_port",
944
                        PORT_A_ADDRESS_WIDTH = 12,
945
                        PORT_A_DATA_WIDTH = 1,
946
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
947
                        PORT_A_FIRST_ADDRESS = 0,
948
                        PORT_A_FIRST_BIT_NUMBER = 30,
949
                        PORT_A_LAST_ADDRESS = 4095,
950
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
951
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
952
                        PORT_B_ADDRESS_CLOCK = "clock0",
953
                        PORT_B_ADDRESS_WIDTH = 12,
954
                        PORT_B_DATA_OUT_CLEAR = "none",
955
                        PORT_B_DATA_OUT_CLOCK = "none",
956
                        PORT_B_DATA_WIDTH = 1,
957
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
958
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
959
                        PORT_B_FIRST_ADDRESS = 0,
960
                        PORT_B_FIRST_BIT_NUMBER = 30,
961
                        PORT_B_LAST_ADDRESS = 4095,
962
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
963
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
964
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
965
                        RAM_BLOCK_TYPE = "AUTO"
966
                );
967
        ram_block1a31 : stratixii_ram_block
968
                WITH (
969
                        CONNECTIVITY_CHECKING = "OFF",
970
                        DONT_POWER_OPTIMIZE = "ON",
971
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
972
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
973
                        OPERATION_MODE = "dual_port",
974
                        PORT_A_ADDRESS_WIDTH = 12,
975
                        PORT_A_DATA_WIDTH = 1,
976
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
977
                        PORT_A_FIRST_ADDRESS = 0,
978
                        PORT_A_FIRST_BIT_NUMBER = 31,
979
                        PORT_A_LAST_ADDRESS = 4095,
980
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
981
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
982
                        PORT_B_ADDRESS_CLOCK = "clock0",
983
                        PORT_B_ADDRESS_WIDTH = 12,
984
                        PORT_B_DATA_OUT_CLEAR = "none",
985
                        PORT_B_DATA_OUT_CLOCK = "none",
986
                        PORT_B_DATA_WIDTH = 1,
987
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
988
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
989
                        PORT_B_FIRST_ADDRESS = 0,
990
                        PORT_B_FIRST_BIT_NUMBER = 31,
991
                        PORT_B_LAST_ADDRESS = 4095,
992
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
993
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
994
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
995
                        RAM_BLOCK_TYPE = "AUTO"
996
                );
997
        ram_block1a32 : stratixii_ram_block
998
                WITH (
999
                        CONNECTIVITY_CHECKING = "OFF",
1000
                        DONT_POWER_OPTIMIZE = "ON",
1001
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1002
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1003
                        OPERATION_MODE = "dual_port",
1004
                        PORT_A_ADDRESS_WIDTH = 12,
1005
                        PORT_A_DATA_WIDTH = 1,
1006
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1007
                        PORT_A_FIRST_ADDRESS = 0,
1008
                        PORT_A_FIRST_BIT_NUMBER = 32,
1009
                        PORT_A_LAST_ADDRESS = 4095,
1010
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1011
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1012
                        PORT_B_ADDRESS_CLOCK = "clock0",
1013
                        PORT_B_ADDRESS_WIDTH = 12,
1014
                        PORT_B_DATA_OUT_CLEAR = "none",
1015
                        PORT_B_DATA_OUT_CLOCK = "none",
1016
                        PORT_B_DATA_WIDTH = 1,
1017
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1018
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1019
                        PORT_B_FIRST_ADDRESS = 0,
1020
                        PORT_B_FIRST_BIT_NUMBER = 32,
1021
                        PORT_B_LAST_ADDRESS = 4095,
1022
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1023
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1024
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1025
                        RAM_BLOCK_TYPE = "AUTO"
1026
                );
1027
        ram_block1a33 : stratixii_ram_block
1028
                WITH (
1029
                        CONNECTIVITY_CHECKING = "OFF",
1030
                        DONT_POWER_OPTIMIZE = "ON",
1031
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1032
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1033
                        OPERATION_MODE = "dual_port",
1034
                        PORT_A_ADDRESS_WIDTH = 12,
1035
                        PORT_A_DATA_WIDTH = 1,
1036
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1037
                        PORT_A_FIRST_ADDRESS = 0,
1038
                        PORT_A_FIRST_BIT_NUMBER = 33,
1039
                        PORT_A_LAST_ADDRESS = 4095,
1040
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1041
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1042
                        PORT_B_ADDRESS_CLOCK = "clock0",
1043
                        PORT_B_ADDRESS_WIDTH = 12,
1044
                        PORT_B_DATA_OUT_CLEAR = "none",
1045
                        PORT_B_DATA_OUT_CLOCK = "none",
1046
                        PORT_B_DATA_WIDTH = 1,
1047
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1048
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1049
                        PORT_B_FIRST_ADDRESS = 0,
1050
                        PORT_B_FIRST_BIT_NUMBER = 33,
1051
                        PORT_B_LAST_ADDRESS = 4095,
1052
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1053
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1054
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1055
                        RAM_BLOCK_TYPE = "AUTO"
1056
                );
1057
        ram_block1a34 : stratixii_ram_block
1058
                WITH (
1059
                        CONNECTIVITY_CHECKING = "OFF",
1060
                        DONT_POWER_OPTIMIZE = "ON",
1061
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1062
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1063
                        OPERATION_MODE = "dual_port",
1064
                        PORT_A_ADDRESS_WIDTH = 12,
1065
                        PORT_A_DATA_WIDTH = 1,
1066
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1067
                        PORT_A_FIRST_ADDRESS = 0,
1068
                        PORT_A_FIRST_BIT_NUMBER = 34,
1069
                        PORT_A_LAST_ADDRESS = 4095,
1070
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1071
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1072
                        PORT_B_ADDRESS_CLOCK = "clock0",
1073
                        PORT_B_ADDRESS_WIDTH = 12,
1074
                        PORT_B_DATA_OUT_CLEAR = "none",
1075
                        PORT_B_DATA_OUT_CLOCK = "none",
1076
                        PORT_B_DATA_WIDTH = 1,
1077
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1078
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1079
                        PORT_B_FIRST_ADDRESS = 0,
1080
                        PORT_B_FIRST_BIT_NUMBER = 34,
1081
                        PORT_B_LAST_ADDRESS = 4095,
1082
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1083
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1084
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1085
                        RAM_BLOCK_TYPE = "AUTO"
1086
                );
1087
        ram_block1a35 : stratixii_ram_block
1088
                WITH (
1089
                        CONNECTIVITY_CHECKING = "OFF",
1090
                        DONT_POWER_OPTIMIZE = "ON",
1091
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1092
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1093
                        OPERATION_MODE = "dual_port",
1094
                        PORT_A_ADDRESS_WIDTH = 12,
1095
                        PORT_A_DATA_WIDTH = 1,
1096
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1097
                        PORT_A_FIRST_ADDRESS = 0,
1098
                        PORT_A_FIRST_BIT_NUMBER = 35,
1099
                        PORT_A_LAST_ADDRESS = 4095,
1100
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1101
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1102
                        PORT_B_ADDRESS_CLOCK = "clock0",
1103
                        PORT_B_ADDRESS_WIDTH = 12,
1104
                        PORT_B_DATA_OUT_CLEAR = "none",
1105
                        PORT_B_DATA_OUT_CLOCK = "none",
1106
                        PORT_B_DATA_WIDTH = 1,
1107
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1108
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1109
                        PORT_B_FIRST_ADDRESS = 0,
1110
                        PORT_B_FIRST_BIT_NUMBER = 35,
1111
                        PORT_B_LAST_ADDRESS = 4095,
1112
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1113
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1114
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1115
                        RAM_BLOCK_TYPE = "AUTO"
1116
                );
1117
        ram_block1a36 : stratixii_ram_block
1118
                WITH (
1119
                        CONNECTIVITY_CHECKING = "OFF",
1120
                        DONT_POWER_OPTIMIZE = "ON",
1121
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1122
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1123
                        OPERATION_MODE = "dual_port",
1124
                        PORT_A_ADDRESS_WIDTH = 12,
1125
                        PORT_A_DATA_WIDTH = 1,
1126
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1127
                        PORT_A_FIRST_ADDRESS = 0,
1128
                        PORT_A_FIRST_BIT_NUMBER = 36,
1129
                        PORT_A_LAST_ADDRESS = 4095,
1130
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1131
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1132
                        PORT_B_ADDRESS_CLOCK = "clock0",
1133
                        PORT_B_ADDRESS_WIDTH = 12,
1134
                        PORT_B_DATA_OUT_CLEAR = "none",
1135
                        PORT_B_DATA_OUT_CLOCK = "none",
1136
                        PORT_B_DATA_WIDTH = 1,
1137
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1138
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1139
                        PORT_B_FIRST_ADDRESS = 0,
1140
                        PORT_B_FIRST_BIT_NUMBER = 36,
1141
                        PORT_B_LAST_ADDRESS = 4095,
1142
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1143
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1144
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1145
                        RAM_BLOCK_TYPE = "AUTO"
1146
                );
1147
        ram_block1a37 : stratixii_ram_block
1148
                WITH (
1149
                        CONNECTIVITY_CHECKING = "OFF",
1150
                        DONT_POWER_OPTIMIZE = "ON",
1151
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1152
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1153
                        OPERATION_MODE = "dual_port",
1154
                        PORT_A_ADDRESS_WIDTH = 12,
1155
                        PORT_A_DATA_WIDTH = 1,
1156
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1157
                        PORT_A_FIRST_ADDRESS = 0,
1158
                        PORT_A_FIRST_BIT_NUMBER = 37,
1159
                        PORT_A_LAST_ADDRESS = 4095,
1160
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1161
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1162
                        PORT_B_ADDRESS_CLOCK = "clock0",
1163
                        PORT_B_ADDRESS_WIDTH = 12,
1164
                        PORT_B_DATA_OUT_CLEAR = "none",
1165
                        PORT_B_DATA_OUT_CLOCK = "none",
1166
                        PORT_B_DATA_WIDTH = 1,
1167
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1168
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1169
                        PORT_B_FIRST_ADDRESS = 0,
1170
                        PORT_B_FIRST_BIT_NUMBER = 37,
1171
                        PORT_B_LAST_ADDRESS = 4095,
1172
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1173
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1174
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1175
                        RAM_BLOCK_TYPE = "AUTO"
1176
                );
1177
        ram_block1a38 : stratixii_ram_block
1178
                WITH (
1179
                        CONNECTIVITY_CHECKING = "OFF",
1180
                        DONT_POWER_OPTIMIZE = "ON",
1181
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1182
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1183
                        OPERATION_MODE = "dual_port",
1184
                        PORT_A_ADDRESS_WIDTH = 12,
1185
                        PORT_A_DATA_WIDTH = 1,
1186
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1187
                        PORT_A_FIRST_ADDRESS = 0,
1188
                        PORT_A_FIRST_BIT_NUMBER = 38,
1189
                        PORT_A_LAST_ADDRESS = 4095,
1190
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1191
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1192
                        PORT_B_ADDRESS_CLOCK = "clock0",
1193
                        PORT_B_ADDRESS_WIDTH = 12,
1194
                        PORT_B_DATA_OUT_CLEAR = "none",
1195
                        PORT_B_DATA_OUT_CLOCK = "none",
1196
                        PORT_B_DATA_WIDTH = 1,
1197
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1198
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1199
                        PORT_B_FIRST_ADDRESS = 0,
1200
                        PORT_B_FIRST_BIT_NUMBER = 38,
1201
                        PORT_B_LAST_ADDRESS = 4095,
1202
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1203
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1204
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1205
                        RAM_BLOCK_TYPE = "AUTO"
1206
                );
1207
        ram_block1a39 : stratixii_ram_block
1208
                WITH (
1209
                        CONNECTIVITY_CHECKING = "OFF",
1210
                        DONT_POWER_OPTIMIZE = "ON",
1211
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1212
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1213
                        OPERATION_MODE = "dual_port",
1214
                        PORT_A_ADDRESS_WIDTH = 12,
1215
                        PORT_A_DATA_WIDTH = 1,
1216
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1217
                        PORT_A_FIRST_ADDRESS = 0,
1218
                        PORT_A_FIRST_BIT_NUMBER = 39,
1219
                        PORT_A_LAST_ADDRESS = 4095,
1220
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1221
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1222
                        PORT_B_ADDRESS_CLOCK = "clock0",
1223
                        PORT_B_ADDRESS_WIDTH = 12,
1224
                        PORT_B_DATA_OUT_CLEAR = "none",
1225
                        PORT_B_DATA_OUT_CLOCK = "none",
1226
                        PORT_B_DATA_WIDTH = 1,
1227
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1228
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1229
                        PORT_B_FIRST_ADDRESS = 0,
1230
                        PORT_B_FIRST_BIT_NUMBER = 39,
1231
                        PORT_B_LAST_ADDRESS = 4095,
1232
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1233
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1234
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1235
                        RAM_BLOCK_TYPE = "AUTO"
1236
                );
1237
        ram_block1a40 : stratixii_ram_block
1238
                WITH (
1239
                        CONNECTIVITY_CHECKING = "OFF",
1240
                        DONT_POWER_OPTIMIZE = "ON",
1241
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1242
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1243
                        OPERATION_MODE = "dual_port",
1244
                        PORT_A_ADDRESS_WIDTH = 12,
1245
                        PORT_A_DATA_WIDTH = 1,
1246
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1247
                        PORT_A_FIRST_ADDRESS = 0,
1248
                        PORT_A_FIRST_BIT_NUMBER = 40,
1249
                        PORT_A_LAST_ADDRESS = 4095,
1250
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1251
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1252
                        PORT_B_ADDRESS_CLOCK = "clock0",
1253
                        PORT_B_ADDRESS_WIDTH = 12,
1254
                        PORT_B_DATA_OUT_CLEAR = "none",
1255
                        PORT_B_DATA_OUT_CLOCK = "none",
1256
                        PORT_B_DATA_WIDTH = 1,
1257
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1258
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1259
                        PORT_B_FIRST_ADDRESS = 0,
1260
                        PORT_B_FIRST_BIT_NUMBER = 40,
1261
                        PORT_B_LAST_ADDRESS = 4095,
1262
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1263
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1264
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1265
                        RAM_BLOCK_TYPE = "AUTO"
1266
                );
1267
        ram_block1a41 : stratixii_ram_block
1268
                WITH (
1269
                        CONNECTIVITY_CHECKING = "OFF",
1270
                        DONT_POWER_OPTIMIZE = "ON",
1271
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1272
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1273
                        OPERATION_MODE = "dual_port",
1274
                        PORT_A_ADDRESS_WIDTH = 12,
1275
                        PORT_A_DATA_WIDTH = 1,
1276
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1277
                        PORT_A_FIRST_ADDRESS = 0,
1278
                        PORT_A_FIRST_BIT_NUMBER = 41,
1279
                        PORT_A_LAST_ADDRESS = 4095,
1280
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1281
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1282
                        PORT_B_ADDRESS_CLOCK = "clock0",
1283
                        PORT_B_ADDRESS_WIDTH = 12,
1284
                        PORT_B_DATA_OUT_CLEAR = "none",
1285
                        PORT_B_DATA_OUT_CLOCK = "none",
1286
                        PORT_B_DATA_WIDTH = 1,
1287
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1288
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1289
                        PORT_B_FIRST_ADDRESS = 0,
1290
                        PORT_B_FIRST_BIT_NUMBER = 41,
1291
                        PORT_B_LAST_ADDRESS = 4095,
1292
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1293
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1294
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1295
                        RAM_BLOCK_TYPE = "AUTO"
1296
                );
1297
        ram_block1a42 : stratixii_ram_block
1298
                WITH (
1299
                        CONNECTIVITY_CHECKING = "OFF",
1300
                        DONT_POWER_OPTIMIZE = "ON",
1301
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1302
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1303
                        OPERATION_MODE = "dual_port",
1304
                        PORT_A_ADDRESS_WIDTH = 12,
1305
                        PORT_A_DATA_WIDTH = 1,
1306
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1307
                        PORT_A_FIRST_ADDRESS = 0,
1308
                        PORT_A_FIRST_BIT_NUMBER = 42,
1309
                        PORT_A_LAST_ADDRESS = 4095,
1310
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1311
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1312
                        PORT_B_ADDRESS_CLOCK = "clock0",
1313
                        PORT_B_ADDRESS_WIDTH = 12,
1314
                        PORT_B_DATA_OUT_CLEAR = "none",
1315
                        PORT_B_DATA_OUT_CLOCK = "none",
1316
                        PORT_B_DATA_WIDTH = 1,
1317
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1318
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1319
                        PORT_B_FIRST_ADDRESS = 0,
1320
                        PORT_B_FIRST_BIT_NUMBER = 42,
1321
                        PORT_B_LAST_ADDRESS = 4095,
1322
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1323
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1324
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1325
                        RAM_BLOCK_TYPE = "AUTO"
1326
                );
1327
        ram_block1a43 : stratixii_ram_block
1328
                WITH (
1329
                        CONNECTIVITY_CHECKING = "OFF",
1330
                        DONT_POWER_OPTIMIZE = "ON",
1331
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1332
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1333
                        OPERATION_MODE = "dual_port",
1334
                        PORT_A_ADDRESS_WIDTH = 12,
1335
                        PORT_A_DATA_WIDTH = 1,
1336
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1337
                        PORT_A_FIRST_ADDRESS = 0,
1338
                        PORT_A_FIRST_BIT_NUMBER = 43,
1339
                        PORT_A_LAST_ADDRESS = 4095,
1340
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1341
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1342
                        PORT_B_ADDRESS_CLOCK = "clock0",
1343
                        PORT_B_ADDRESS_WIDTH = 12,
1344
                        PORT_B_DATA_OUT_CLEAR = "none",
1345
                        PORT_B_DATA_OUT_CLOCK = "none",
1346
                        PORT_B_DATA_WIDTH = 1,
1347
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1348
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1349
                        PORT_B_FIRST_ADDRESS = 0,
1350
                        PORT_B_FIRST_BIT_NUMBER = 43,
1351
                        PORT_B_LAST_ADDRESS = 4095,
1352
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1353
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1354
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1355
                        RAM_BLOCK_TYPE = "AUTO"
1356
                );
1357
        ram_block1a44 : stratixii_ram_block
1358
                WITH (
1359
                        CONNECTIVITY_CHECKING = "OFF",
1360
                        DONT_POWER_OPTIMIZE = "ON",
1361
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1362
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1363
                        OPERATION_MODE = "dual_port",
1364
                        PORT_A_ADDRESS_WIDTH = 12,
1365
                        PORT_A_DATA_WIDTH = 1,
1366
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1367
                        PORT_A_FIRST_ADDRESS = 0,
1368
                        PORT_A_FIRST_BIT_NUMBER = 44,
1369
                        PORT_A_LAST_ADDRESS = 4095,
1370
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1371
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1372
                        PORT_B_ADDRESS_CLOCK = "clock0",
1373
                        PORT_B_ADDRESS_WIDTH = 12,
1374
                        PORT_B_DATA_OUT_CLEAR = "none",
1375
                        PORT_B_DATA_OUT_CLOCK = "none",
1376
                        PORT_B_DATA_WIDTH = 1,
1377
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1378
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1379
                        PORT_B_FIRST_ADDRESS = 0,
1380
                        PORT_B_FIRST_BIT_NUMBER = 44,
1381
                        PORT_B_LAST_ADDRESS = 4095,
1382
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1383
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1384
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1385
                        RAM_BLOCK_TYPE = "AUTO"
1386
                );
1387
        ram_block1a45 : stratixii_ram_block
1388
                WITH (
1389
                        CONNECTIVITY_CHECKING = "OFF",
1390
                        DONT_POWER_OPTIMIZE = "ON",
1391
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1392
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1393
                        OPERATION_MODE = "dual_port",
1394
                        PORT_A_ADDRESS_WIDTH = 12,
1395
                        PORT_A_DATA_WIDTH = 1,
1396
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1397
                        PORT_A_FIRST_ADDRESS = 0,
1398
                        PORT_A_FIRST_BIT_NUMBER = 45,
1399
                        PORT_A_LAST_ADDRESS = 4095,
1400
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1401
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1402
                        PORT_B_ADDRESS_CLOCK = "clock0",
1403
                        PORT_B_ADDRESS_WIDTH = 12,
1404
                        PORT_B_DATA_OUT_CLEAR = "none",
1405
                        PORT_B_DATA_OUT_CLOCK = "none",
1406
                        PORT_B_DATA_WIDTH = 1,
1407
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1408
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1409
                        PORT_B_FIRST_ADDRESS = 0,
1410
                        PORT_B_FIRST_BIT_NUMBER = 45,
1411
                        PORT_B_LAST_ADDRESS = 4095,
1412
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1413
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1414
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1415
                        RAM_BLOCK_TYPE = "AUTO"
1416
                );
1417
        ram_block1a46 : stratixii_ram_block
1418
                WITH (
1419
                        CONNECTIVITY_CHECKING = "OFF",
1420
                        DONT_POWER_OPTIMIZE = "ON",
1421
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1422
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1423
                        OPERATION_MODE = "dual_port",
1424
                        PORT_A_ADDRESS_WIDTH = 12,
1425
                        PORT_A_DATA_WIDTH = 1,
1426
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1427
                        PORT_A_FIRST_ADDRESS = 0,
1428
                        PORT_A_FIRST_BIT_NUMBER = 46,
1429
                        PORT_A_LAST_ADDRESS = 4095,
1430
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1431
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1432
                        PORT_B_ADDRESS_CLOCK = "clock0",
1433
                        PORT_B_ADDRESS_WIDTH = 12,
1434
                        PORT_B_DATA_OUT_CLEAR = "none",
1435
                        PORT_B_DATA_OUT_CLOCK = "none",
1436
                        PORT_B_DATA_WIDTH = 1,
1437
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1438
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1439
                        PORT_B_FIRST_ADDRESS = 0,
1440
                        PORT_B_FIRST_BIT_NUMBER = 46,
1441
                        PORT_B_LAST_ADDRESS = 4095,
1442
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1443
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1444
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1445
                        RAM_BLOCK_TYPE = "AUTO"
1446
                );
1447
        ram_block1a47 : stratixii_ram_block
1448
                WITH (
1449
                        CONNECTIVITY_CHECKING = "OFF",
1450
                        DONT_POWER_OPTIMIZE = "ON",
1451
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
1452
                        MIXED_PORT_FEED_THROUGH_MODE = "old",
1453
                        OPERATION_MODE = "dual_port",
1454
                        PORT_A_ADDRESS_WIDTH = 12,
1455
                        PORT_A_DATA_WIDTH = 1,
1456
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1457
                        PORT_A_FIRST_ADDRESS = 0,
1458
                        PORT_A_FIRST_BIT_NUMBER = 47,
1459
                        PORT_A_LAST_ADDRESS = 4095,
1460
                        PORT_A_LOGICAL_RAM_DEPTH = 4096,
1461
                        PORT_A_LOGICAL_RAM_WIDTH = 48,
1462
                        PORT_B_ADDRESS_CLOCK = "clock0",
1463
                        PORT_B_ADDRESS_WIDTH = 12,
1464
                        PORT_B_DATA_OUT_CLEAR = "none",
1465
                        PORT_B_DATA_OUT_CLOCK = "none",
1466
                        PORT_B_DATA_WIDTH = 1,
1467
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
1468
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
1469
                        PORT_B_FIRST_ADDRESS = 0,
1470
                        PORT_B_FIRST_BIT_NUMBER = 47,
1471
                        PORT_B_LAST_ADDRESS = 4095,
1472
                        PORT_B_LOGICAL_RAM_DEPTH = 4096,
1473
                        PORT_B_LOGICAL_RAM_WIDTH = 48,
1474
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
1475
                        RAM_BLOCK_TYPE = "AUTO"
1476
                );
1477
        address_a_wire[11..0]   : WIRE;
1478
        address_b_wire[11..0]   : WIRE;
1479
 
1480
BEGIN
1481
        ram_block1a[47..0].clk0 = clock0;
1482
        ram_block1a[47..0].portaaddr[] = ( address_a_wire[11..0]);
1483
        ram_block1a[0].portadatain[] = ( data_a[0..0]);
1484
        ram_block1a[1].portadatain[] = ( data_a[1..1]);
1485
        ram_block1a[2].portadatain[] = ( data_a[2..2]);
1486
        ram_block1a[3].portadatain[] = ( data_a[3..3]);
1487
        ram_block1a[4].portadatain[] = ( data_a[4..4]);
1488
        ram_block1a[5].portadatain[] = ( data_a[5..5]);
1489
        ram_block1a[6].portadatain[] = ( data_a[6..6]);
1490
        ram_block1a[7].portadatain[] = ( data_a[7..7]);
1491
        ram_block1a[8].portadatain[] = ( data_a[8..8]);
1492
        ram_block1a[9].portadatain[] = ( data_a[9..9]);
1493
        ram_block1a[10].portadatain[] = ( data_a[10..10]);
1494
        ram_block1a[11].portadatain[] = ( data_a[11..11]);
1495
        ram_block1a[12].portadatain[] = ( data_a[12..12]);
1496
        ram_block1a[13].portadatain[] = ( data_a[13..13]);
1497
        ram_block1a[14].portadatain[] = ( data_a[14..14]);
1498
        ram_block1a[15].portadatain[] = ( data_a[15..15]);
1499
        ram_block1a[16].portadatain[] = ( data_a[16..16]);
1500
        ram_block1a[17].portadatain[] = ( data_a[17..17]);
1501
        ram_block1a[18].portadatain[] = ( data_a[18..18]);
1502
        ram_block1a[19].portadatain[] = ( data_a[19..19]);
1503
        ram_block1a[20].portadatain[] = ( data_a[20..20]);
1504
        ram_block1a[21].portadatain[] = ( data_a[21..21]);
1505
        ram_block1a[22].portadatain[] = ( data_a[22..22]);
1506
        ram_block1a[23].portadatain[] = ( data_a[23..23]);
1507
        ram_block1a[24].portadatain[] = ( data_a[24..24]);
1508
        ram_block1a[25].portadatain[] = ( data_a[25..25]);
1509
        ram_block1a[26].portadatain[] = ( data_a[26..26]);
1510
        ram_block1a[27].portadatain[] = ( data_a[27..27]);
1511
        ram_block1a[28].portadatain[] = ( data_a[28..28]);
1512
        ram_block1a[29].portadatain[] = ( data_a[29..29]);
1513
        ram_block1a[30].portadatain[] = ( data_a[30..30]);
1514
        ram_block1a[31].portadatain[] = ( data_a[31..31]);
1515
        ram_block1a[32].portadatain[] = ( data_a[32..32]);
1516
        ram_block1a[33].portadatain[] = ( data_a[33..33]);
1517
        ram_block1a[34].portadatain[] = ( data_a[34..34]);
1518
        ram_block1a[35].portadatain[] = ( data_a[35..35]);
1519
        ram_block1a[36].portadatain[] = ( data_a[36..36]);
1520
        ram_block1a[37].portadatain[] = ( data_a[37..37]);
1521
        ram_block1a[38].portadatain[] = ( data_a[38..38]);
1522
        ram_block1a[39].portadatain[] = ( data_a[39..39]);
1523
        ram_block1a[40].portadatain[] = ( data_a[40..40]);
1524
        ram_block1a[41].portadatain[] = ( data_a[41..41]);
1525
        ram_block1a[42].portadatain[] = ( data_a[42..42]);
1526
        ram_block1a[43].portadatain[] = ( data_a[43..43]);
1527
        ram_block1a[44].portadatain[] = ( data_a[44..44]);
1528
        ram_block1a[45].portadatain[] = ( data_a[45..45]);
1529
        ram_block1a[46].portadatain[] = ( data_a[46..46]);
1530
        ram_block1a[47].portadatain[] = ( data_a[47..47]);
1531
        ram_block1a[47..0].portawe = wren_a;
1532
        ram_block1a[47..0].portbaddr[] = ( address_b_wire[11..0]);
1533
        ram_block1a[47..0].portbrewe = B"111111111111111111111111111111111111111111111111";
1534
        address_a_wire[] = address_a[];
1535
        address_b_wire[] = address_b[];
1536
        q_b[] = ( ram_block1a[47..0].portbdataout[0..0]);
1537
END;
1538
--VALID FILE

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