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[/] [loadbalancer/] [trunk/] [int2ext/] [int2ext_top.vhd] - Blame information for rev 2

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--------------------------------------------------------
        LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        use ieee.numeric_std.all;
        use IEEE.STD_LOGIC_ARITH.ALL;
        use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------
        ENTITY int2ext_top IS
        GENERIC(DATA_WIDTH :INTEGER := 64;
                        CTRL_WIDTH :INTEGER := 8);
        PORT(
                SIGNAL          in_data                            :    IN      STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
                SIGNAL          in_ctrl                            :    IN      STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
                SIGNAL          in_wr                           :       IN              STD_LOGIC       ;
                SIGNAL          in_rdy                          :       OUT     STD_LOGIC       ;
 
                SIGNAL          out_data                        :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
                SIGNAL          out_ctrl                        :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
                SIGNAL          out_wr                          :       OUT     STD_LOGIC       ;
                SIGNAL          out_rdy                            :    IN              STD_LOGIC       ;
--              SIGNAL          fifo_data_out                   :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
--              SIGNAL          latch_word_out                  :       OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)   ;
--              SIGNAL          fifo_ctrl_out                   :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)    ;
                SIGNAL      en                                  : IN STD_LOGIC;
                SIGNAL          reset                           :       IN              STD_LOGIC       ;
                SIGNAL          clk                             :       IN              STD_LOGIC
        );
        END ENTITY int2ext_top;
 
 ------------------------------------------------------
        ARCHITECTURE behavior OF int2ext_top IS
-------COMPONENET SMALL FIFO
                COMPONENT  small_fifo IS
                                GENERIC(WIDTH :INTEGER := 72;
                                                MAX_DEPTH_BITS :INTEGER := 3);
                                PORT(
                                         SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                         SIGNAL wr_en : IN STD_LOGIC;
                                         SIGNAL rd_en : IN STD_LOGIC;
                                         SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                         SIGNAL full : OUT STD_LOGIC;
                                         SIGNAL nearly_full : OUT STD_LOGIC;
                                         SIGNAL empty : OUT STD_LOGIC;
                                         SIGNAL reset :IN STD_LOGIC;
                                         SIGNAL clk   :IN STD_LOGIC
                                );
                END COMPONENT;
-------COMPONENET SMALL FIFO
------COMPONENT vlan2ext
        COMPONENT vlan2ext IS
                GENERIC(DATA_WIDTH :INTEGER := 64;
                                CTRL_WIDTH :INTEGER := 8);
                                PORT(
                                        SIGNAL          in_data                         :       IN      STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
                                        SIGNAL          in_ctrl                         :       IN      STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
                                        SIGNAL          in_wr                           :       IN              STD_LOGIC       ;
                                        SIGNAL          exit_port                       :       OUT     STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
                                        SIGNAL          done                            :       OUT     STD_LOGIC       ;
                                         --- Misc                                       
                                        SIGNAL          reset                           :       IN              STD_LOGIC       ;
                                        SIGNAL          clk                             :       IN              STD_LOGIC
                                        );
        END COMPONENT;
------COMPONENT vlan2ext
------------ one hot encoding state definition
 
        TYPE state_type IS (IDLE, START, IN_MODULE_HDRS, WORD_1, WORD_2,WORD_3, IN_PACKET,LAST);
        ATTRIBUTE enum_encoding: STRING;
        ATTRIBUTE enum_encoding of state_type : type is "onehot";
 
        SIGNAL state, state_NEXT : state_type;
 
------------end state machine definition
 
----------------------FIFO        
          SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
          SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);
          SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_rd_en : STD_LOGIC;
          SIGNAL in_fifo_go : STD_LOGIC;
          SIGNAL in_fifo_rd_en_p : STD_LOGIC;
      SIGNAL in_fifo_dout  : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL in_fifo_full : STD_LOGIC;
      SIGNAL in_fifo_nearly_full : STD_LOGIC;
      SIGNAL in_fifo_empty : STD_LOGIC;
------------------------------
          SIGNAL ctrl_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);
      SIGNAL ctrl_fifo_rd : STD_LOGIC;
      SIGNAL ctrl_fifo_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
      SIGNAL ctrl_fifo_full : STD_LOGIC;
      SIGNAL ctrl_fifo_nearly_full : STD_LOGIC;
      SIGNAL ctrl_fifo_empty : STD_LOGIC;
--        SIGNAL cnt : INTEGER; 
 
          SIGNAL                out_data_i                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
          SIGNAL                out_ctrl_i                      :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                out_wr_i                        :               STD_LOGIC       ;
          SIGNAL                in_data_i                       :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
          SIGNAL                in_ctrl_i                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                in_fifo_in_i            :               STD_LOGIC_VECTOR(71 DOWNTO 0)    ;
          SIGNAL                wr_en_i                         :               STD_LOGIC       ;
          SIGNAL                exit_port                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                done                            :               STD_LOGIC       ;
          SIGNAL                words_cnt                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                words_cnt_ch            :               STD_LOGIC;
          SIGNAL                bytes_cnt                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                cnt                                     :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                last_ctrl                       :               STD_LOGIC_VECTOR(7 DOWNTO 0)     ;
          SIGNAL                cnt_en                          :               STD_LOGIC       ;
          SIGNAL                cnt_rst                         :               STD_LOGIC       ;
          SIGNAL                header_rdy                      :               STD_LOGIC       ;
          SIGNAL                latch                           :               STD_LOGIC       ;
          SIGNAL                latch_word                      :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
          SIGNAL                latch_word_p                    :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
          SIGNAL                fifo_data_p                     :               STD_LOGIC_VECTOR(63 DOWNTO 0)    ;
          SIGNAL                wr_en                           : STD_LOGIC;
         SIGNAL                 out_wr_t_i                              : STD_LOGIC;
---------------------------------------------------
        BEGIN
 
 
        ------PORT MAP open_header
        vlan2extr_Inst : vlan2ext
        GENERIC MAP (DATA_WIDTH  => 64,
                        CTRL_WIDTH => 8)
        PORT MAP(
                        in_data                            =>   in_data_i,
                        in_ctrl                            => in_ctrl_i ,
                in_wr                           =>      wr_en_i,
                        exit_port                       =>  exit_port,
                        done                               =>  done,
                reset                           =>      reset,
                clk                             =>      clk
        );
 
        ------PORT MAP open_header
 
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst1 :  small_fifo
                GENERIC MAP(WIDTH  => 72,
                                MAX_DEPTH_BITS  => 5)
                        PORT MAP(
                                  din =>in_fifo_in_i,
                                  wr_en =>wr_en_i,
                                  rd_en => in_fifo_rd_en,
                                  dout =>in_fifo_dout,
                                  full =>in_fifo_full,
                                  nearly_full =>in_fifo_nearly_full,
                                  empty => in_fifo_empty,
                                  reset => reset ,
                                  clk  => clk
                        );
 
 
 
-------PORT MAP SMALL FIFO
                -------PORT MAP SMALL FIFO DATA
                small_fifo_Inst_ctrl :  small_fifo
        GENERIC MAP(WIDTH  => 8,
                        MAX_DEPTH_BITS  => 5)
                                PORT MAP(
                                  din =>exit_port,
                                  wr_en => done,
                                  rd_en => ctrl_fifo_rd,
                                  dout =>ctrl_fifo_dout,
                                  full =>ctrl_fifo_full,
                                  nearly_full =>ctrl_fifo_nearly_full,
                                  empty => ctrl_fifo_empty,
                                  reset => reset ,
                                  clk  => clk
                                );
 
 
-----------------------
 
 
                                in_fifo_in_i    <=              in_fifo_in;
                                wr_en_i                 <=      wr_en;
                                in_data_i               <=              in_data;
                                in_ctrl_i               <=              in_ctrl;
 
        in_fifo_in      <=      in_data & in_ctrl ;
                fifo_data        <=        in_fifo_dout(71 DOWNTO 8)    ;
                fifo_ctrl       <=      in_fifo_dout(7 DOWNTO 0) ;
--              in_fifo_rd_en <=out_rdy AND (NOT in_fifo_empty) AND in_fifo_go;
--           fifo_rd <= ctrl_fifo_empty OR in_fifo_go;
                 in_rdy         <=      (NOT in_fifo_nearly_full) AND (NOT ctrl_fifo_nearly_full)       ;
                wr_en  <= en  AND in_wr;
                PROCESS(clk,reset)
                BEGIN
                        IF (reset ='1') THEN
                                state <=IDLE;
                                ELSIF clk'EVENT AND clk ='1' THEN
                                state<=state_next;
                                in_fifo_rd_en_p <= in_fifo_rd_en;
                        END IF;
                END PROCESS;
 
--              out_cnt <= cnt;
PROCESS(state, ctrl_fifo_empty ,fifo_data, fifo_ctrl,in_fifo_empty)
        BEGIN
                                                        state_next                              <=      state;
--                                                      out_data_i                              <= fifo_data    ;
--                                                      out_ctrl_i                              <= fifo_ctrl;
                                                        out_wr_i                                <=              '0';
                                                        ctrl_fifo_rd                    <=              '0'      ;
                                                        in_fifo_rd_en                   <=              '0'      ;
                                                        header_rdy                              <=              '0'      ;
 
                CASE state IS
                        WHEN IDLE =>
                           IF(ctrl_fifo_empty = '0'  ) THEN
                                                   ctrl_fifo_rd                         <=      '1'     ;
                                                   in_fifo_rd_en                        <=      '1'     ;
                                                   state_next                           <=  START;
                                END IF;
                        WHEN START                      =>
 
                                                        header_rdy                              <=      '1'     ;
                                                        state_next                              <=  IN_MODULE_HDRS;
                        WHEN IN_MODULE_HDRS =>
 
                                                        IF(out_rdy = '1'  ) THEN
                                                                IF (fifo_ctrl=X"FF")    THEN
                                                                END IF;
                                                        out_wr_i                                <=      '1';
                                                        in_fifo_rd_en                   <=      '1'     ;
                                                        state_next              <=  WORD_1;
                                                        END IF;
 
 
                        WHEN WORD_1             =>
 
                                                IF(out_rdy = '1'  AND   in_fifo_empty ='0') THEN
 
                                                        out_wr_i                                <=      '1';
                                                        in_fifo_rd_en                   <=      '1'     ;
                                                        state_next              <=  WORD_2;
                                                        END IF;
                        WHEN WORD_2             =>IF(out_rdy = '1'  AND   in_fifo_empty ='0') THEN
 
--                                                      out_wr_i                                <=      '1';
                                                        in_fifo_rd_en                   <=      '1'     ;
                                                        state_next              <=  WORD_3;
                                                        END IF;
 
                        WHEN WORD_3             =>
                                                        IF(out_rdy = '1'  AND   in_fifo_empty ='0') THEN
                                                        out_wr_i                                <=      '1';
                                                        in_fifo_rd_en                   <=      '1'     ;
                                                        state_next              <=  IN_PACKET;
                                                        END IF;
 
 
                        WHEN IN_PACKET  =>
 
 
                                                        IF ( fifo_ctrl /= X"00" ) THEN
 
                                                                IF (   out_rdy = '1' ) THEN
                                                                                out_wr_i                                <=      '1';
                                                                                        IF (   words_cnt_ch = '1' ) THEN
                                                                                        state_next               <= IDLE;
                                                                                        ELSE
                                                                                                state_next               <= LAST;
                                                                                END IF;
                                                                                END IF;
                                                        ELSIF(out_rdy = '1'  AND   in_fifo_empty ='0') THEN
                                                                out_wr_i                                        <=      '1';
                                                                in_fifo_rd_en                   <=      '1'     ;
 
                                                                state_next              <=  IN_PACKET;
                                                        END IF;
 
                        WHEN LAST =>    IF (   out_rdy = '1' ) THEN
                                                                out_wr_i                                <=      '1';
                                                                state_next               <= IDLE;
                                                                END IF;
 
                        END CASE;
        END PROCESS;
 
 
 
---------------Register output
 
 
        WITH state SELECT
                out_data_i <=
                X"00" & ctrl_fifo_dout & X"00"& words_cnt & fifo_data(31 downto 16) & X"00"& bytes_cnt WHEN  IN_MODULE_HDRS,
                fifo_data WHEN WORD_1,
                latch_word(63 downto 32) &  fifo_data(63 downto 32)WHEN WORD_3,
                latch_word(31 downto 0)  &  fifo_data(63 downto 32) WHEN  IN_PACKET | LAST,
                (OTHERS=>'0') WHEN OTHERS;
 
 
        out_ctrl_i <= X"FF" when state = IN_MODULE_HDRS else
                                  last_ctrl  when state = IN_PACKET AND fifo_ctrl /= X"00" AND words_cnt_ch='1' else
                                  last_ctrl  when state = LAST else
                                  X"00" ;
--      WITH state SELECT 
--              out_wr_i <=
--              out_rdy  WHEN  IN_MODULE_HDRS,
--              in_fifo_rd_en_p WHEN WORD_1,
--              in_fifo_rd_en_p WHEN WORD_3,
--              in_fifo_rd_en_p   WHEN  IN_PACKET ,
--               out_rdy  WHEN LAST,
--              '0' WHEN OTHERS;        
--      out_wr_t_i      <=     word_cnt_up when word_cnt >= 1  AND word_cnt <= 21 else
--                                                               '0';                   
                PROCESS(clk,reset)
                BEGIN
 
                        IF clk'EVENT AND clk ='1' THEN
                                        IF header_rdy = '1' THEN
                                                        bytes_cnt <= fifo_data(7 downto 0)- X"04";
                                        IF (fifo_data(15 downto 0)-X"0004") > (fifo_data(45 downto 32)&"000" - X"0008") THEN
                                                                        words_cnt       <=      fifo_data(39 downto 32)  ;
                                                                        words_cnt_ch <= '0';
                                                        ELSE
                                                                        words_cnt       <=      fifo_data(39 downto 32) - '1' ;
                                                                        words_cnt_ch <= '1';
                                                        END IF;
                                        END IF;
                                                IF in_fifo_rd_en='1' THEN
                                                latch_word <= fifo_data;
                                                END IF;
 
                        END IF;
                END PROCESS;
        WITH bytes_cnt(2 DOWNTO 0)SELECT
                        last_ctrl <= "00000010" WHEN "111",
                                                 "00000100" WHEN "110",
                                                 "00001000" WHEN "101",
                                                 "00010000" WHEN "100",
                                                 "00100000" WHEN "011",
                                                 "01000000" WHEN "010",
                                                 "10000000" WHEN "001",
                                                 "00000001" WHEN others;
 
 
 
                PROCESS(clk,reset)
                BEGIN
--                      
                        IF clk'EVENT AND clk ='1' THEN
                                                                        out_data                                <=      out_data_i;
                                                                        out_ctrl                                <=      out_ctrl_i;
                                                                        out_wr                                  <=      out_wr_i;
                        END IF;
                END PROCESS;
--              fifo_ctrl_out <=fifo_ctrl;
--              fifo_data_out <=fifo_data;
--              latch_word_out <= latch_word;
END behavior;
 

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[/] [loadbalancer/] [trunk/] [int2ext/] [int2ext_top.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	atalla	`--------------------------------------------------------`
2			`LIBRARY IEEE;`
3			`USE IEEE.STD_LOGIC_1164.ALL;`
4			`use ieee.numeric_std.all;`
5			`use IEEE.STD_LOGIC_ARITH.ALL;`
6			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
7
8			`-------------------------------`
9			`ENTITY int2ext_top IS`
10			`GENERIC(DATA_WIDTH :INTEGER := 64;`
11			`CTRL_WIDTH :INTEGER := 8);`
12			`PORT(`
13			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
14			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
15			`SIGNAL in_wr : IN STD_LOGIC ;`
16			`SIGNAL in_rdy : OUT STD_LOGIC ;`
17
18			`SIGNAL out_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
19			`SIGNAL out_ctrl : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
20			`SIGNAL out_wr : OUT STD_LOGIC ;`
21			`SIGNAL out_rdy : IN STD_LOGIC ;`
22			`-- SIGNAL fifo_data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
23			`-- SIGNAL latch_word_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
24			`-- SIGNAL fifo_ctrl_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
25			`SIGNAL en : IN STD_LOGIC;`
26			`SIGNAL reset : IN STD_LOGIC ;`
27			`SIGNAL clk : IN STD_LOGIC`
28			`);`
29			`END ENTITY int2ext_top;`
30
31			`------------------------------------------------------`
32			`ARCHITECTURE behavior OF int2ext_top IS`
33			`-------COMPONENET SMALL FIFO`
34			`COMPONENT small_fifo IS`
35			`GENERIC(WIDTH :INTEGER := 72;`
36			`MAX_DEPTH_BITS :INTEGER := 3);`
37			`PORT(`
38			`SIGNAL din : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);`
39			`SIGNAL wr_en : IN STD_LOGIC;`
40			`SIGNAL rd_en : IN STD_LOGIC;`
41			`SIGNAL dout :OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);`
42			`SIGNAL full : OUT STD_LOGIC;`
43			`SIGNAL nearly_full : OUT STD_LOGIC;`
44			`SIGNAL empty : OUT STD_LOGIC;`
45			`SIGNAL reset :IN STD_LOGIC;`
46			`SIGNAL clk :IN STD_LOGIC`
47			`);`
48			`END COMPONENT;`
49			`-------COMPONENET SMALL FIFO`
50			`------COMPONENT vlan2ext`
51			`COMPONENT vlan2ext IS`
52			`GENERIC(DATA_WIDTH :INTEGER := 64;`
53			`CTRL_WIDTH :INTEGER := 8);`
54			`PORT(`
55			`SIGNAL in_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
56			`SIGNAL in_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
57			`SIGNAL in_wr : IN STD_LOGIC ;`
58			`SIGNAL exit_port : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
59			`SIGNAL done : OUT STD_LOGIC ;`
60			`--- Misc`
61			`SIGNAL reset : IN STD_LOGIC ;`
62			`SIGNAL clk : IN STD_LOGIC`
63			`);`
64			`END COMPONENT;`
65			`------COMPONENT vlan2ext`
66			`------------ one hot encoding state definition`
67
68			`TYPE state_type IS (IDLE, START, IN_MODULE_HDRS, WORD_1, WORD_2,WORD_3, IN_PACKET,LAST);`
69			`ATTRIBUTE enum_encoding: STRING;`
70			`ATTRIBUTE enum_encoding of state_type : type is "onehot";`
71
72			`SIGNAL state, state_NEXT : state_type;`
73
74			`------------end state machine definition`
75
76			`----------------------FIFO`
77			`SIGNAL fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);`
78			`SIGNAL fifo_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0);`
79			`SIGNAL in_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
80			`SIGNAL in_fifo_rd_en : STD_LOGIC;`
81			`SIGNAL in_fifo_go : STD_LOGIC;`
82			`SIGNAL in_fifo_rd_en_p : STD_LOGIC;`
83			`SIGNAL in_fifo_dout : STD_LOGIC_VECTOR(71 DOWNTO 0);`
84			`SIGNAL in_fifo_full : STD_LOGIC;`
85			`SIGNAL in_fifo_nearly_full : STD_LOGIC;`
86			`SIGNAL in_fifo_empty : STD_LOGIC;`
87			`------------------------------`
88			`SIGNAL ctrl_fifo_in : STD_LOGIC_VECTOR(71 DOWNTO 0);`
89			`SIGNAL ctrl_fifo_rd : STD_LOGIC;`
90			`SIGNAL ctrl_fifo_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);`
91			`SIGNAL ctrl_fifo_full : STD_LOGIC;`
92			`SIGNAL ctrl_fifo_nearly_full : STD_LOGIC;`
93			`SIGNAL ctrl_fifo_empty : STD_LOGIC;`
94			`-- SIGNAL cnt : INTEGER;`
95
96			`SIGNAL out_data_i : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
97			`SIGNAL out_ctrl_i : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
98			`SIGNAL out_wr_i : STD_LOGIC ;`
99			`SIGNAL in_data_i : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
100			`SIGNAL in_ctrl_i : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
101			`SIGNAL in_fifo_in_i : STD_LOGIC_VECTOR(71 DOWNTO 0) ;`
102			`SIGNAL wr_en_i : STD_LOGIC ;`
103			`SIGNAL exit_port : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
104			`SIGNAL done : STD_LOGIC ;`
105			`SIGNAL words_cnt : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
106			`SIGNAL words_cnt_ch : STD_LOGIC;`
107			`SIGNAL bytes_cnt : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
108			`SIGNAL cnt : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
109			`SIGNAL last_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0) ;`
110			`SIGNAL cnt_en : STD_LOGIC ;`
111			`SIGNAL cnt_rst : STD_LOGIC ;`
112			`SIGNAL header_rdy : STD_LOGIC ;`
113			`SIGNAL latch : STD_LOGIC ;`
114			`SIGNAL latch_word : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
115			`SIGNAL latch_word_p : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
116			`SIGNAL fifo_data_p : STD_LOGIC_VECTOR(63 DOWNTO 0) ;`
117			`SIGNAL wr_en : STD_LOGIC;`
118			`SIGNAL out_wr_t_i : STD_LOGIC;`
119			`---------------------------------------------------`
120			`BEGIN`
121
122
123			`------PORT MAP open_header`
124			`vlan2extr_Inst : vlan2ext`
125			`GENERIC MAP (DATA_WIDTH => 64,`
126			`CTRL_WIDTH => 8)`
127			`PORT MAP(`
128			`in_data => in_data_i,`
129			`in_ctrl => in_ctrl_i ,`
130			`in_wr => wr_en_i,`
131			`exit_port => exit_port,`
132			`done => done,`
133			`reset => reset,`
134			`clk => clk`
135			`);`
136
137			`------PORT MAP open_header`
138
139			`-------PORT MAP SMALL FIFO DATA`
140			`small_fifo_Inst1 : small_fifo`
141			`GENERIC MAP(WIDTH => 72,`
142			`MAX_DEPTH_BITS => 5)`
143			`PORT MAP(`
144			`din =>in_fifo_in_i,`
145			`wr_en =>wr_en_i,`
146			`rd_en => in_fifo_rd_en,`
147			`dout =>in_fifo_dout,`
148			`full =>in_fifo_full,`
149			`nearly_full =>in_fifo_nearly_full,`
150			`empty => in_fifo_empty,`
151			`reset => reset ,`
152			`clk => clk`
153			`);`
154
155
156
157			`-------PORT MAP SMALL FIFO`
158			`-------PORT MAP SMALL FIFO DATA`
159			`small_fifo_Inst_ctrl : small_fifo`
160			`GENERIC MAP(WIDTH => 8,`
161			`MAX_DEPTH_BITS => 5)`
162			`PORT MAP(`
163			`din =>exit_port,`
164			`wr_en => done,`
165			`rd_en => ctrl_fifo_rd,`
166			`dout =>ctrl_fifo_dout,`
167			`full =>ctrl_fifo_full,`
168			`nearly_full =>ctrl_fifo_nearly_full,`
169			`empty => ctrl_fifo_empty,`
170			`reset => reset ,`
171			`clk => clk`
172			`);`
173
174
175			`-----------------------`
176
177
178			`in_fifo_in_i <= in_fifo_in;`
179			`wr_en_i <= wr_en;`
180			`in_data_i <= in_data;`
181			`in_ctrl_i <= in_ctrl;`
182
183			`in_fifo_in <= in_data & in_ctrl ;`
184			`fifo_data <= in_fifo_dout(71 DOWNTO 8) ;`
185			`fifo_ctrl <= in_fifo_dout(7 DOWNTO 0) ;`
186			`-- in_fifo_rd_en <=out_rdy AND (NOT in_fifo_empty) AND in_fifo_go;`
187			`-- fifo_rd <= ctrl_fifo_empty OR in_fifo_go;`
188			`in_rdy <= (NOT in_fifo_nearly_full) AND (NOT ctrl_fifo_nearly_full) ;`
189			`wr_en <= en AND in_wr;`
190			`PROCESS(clk,reset)`
191			`BEGIN`
192			`IF (reset ='1') THEN`
193			`state <=IDLE;`
194			`ELSIF clk'EVENT AND clk ='1' THEN`
195			`state<=state_next;`
196			`in_fifo_rd_en_p <= in_fifo_rd_en;`
197			`END IF;`
198			`END PROCESS;`
199
200			`-- out_cnt <= cnt;`
201			`PROCESS(state, ctrl_fifo_empty ,fifo_data, fifo_ctrl,in_fifo_empty)`
202			`BEGIN`
203			`state_next <= state;`
204			`-- out_data_i <= fifo_data ;`
205			`-- out_ctrl_i <= fifo_ctrl;`
206			`out_wr_i <= '0';`
207			`ctrl_fifo_rd <= '0' ;`
208			`in_fifo_rd_en <= '0' ;`
209			`header_rdy <= '0' ;`
210
211			`CASE state IS`
212			`WHEN IDLE =>`
213			`IF(ctrl_fifo_empty = '0' ) THEN`
214			`ctrl_fifo_rd <= '1' ;`
215			`in_fifo_rd_en <= '1' ;`
216			`state_next <= START;`
217			`END IF;`
218			`WHEN START =>`
219
220			`header_rdy <= '1' ;`
221			`state_next <= IN_MODULE_HDRS;`
222			`WHEN IN_MODULE_HDRS =>`
223
224			`IF(out_rdy = '1' ) THEN`
225			`IF (fifo_ctrl=X"FF") THEN`
226			`END IF;`
227			`out_wr_i <= '1';`
228			`in_fifo_rd_en <= '1' ;`
229			`state_next <= WORD_1;`
230			`END IF;`
231
232
233			`WHEN WORD_1 =>`
234
235			`IF(out_rdy = '1' AND in_fifo_empty ='0') THEN`
236
237			`out_wr_i <= '1';`
238			`in_fifo_rd_en <= '1' ;`
239			`state_next <= WORD_2;`
240			`END IF;`
241			`WHEN WORD_2 =>IF(out_rdy = '1' AND in_fifo_empty ='0') THEN`
242
243			`-- out_wr_i <= '1';`
244			`in_fifo_rd_en <= '1' ;`
245			`state_next <= WORD_3;`
246			`END IF;`
247
248			`WHEN WORD_3 =>`
249			`IF(out_rdy = '1' AND in_fifo_empty ='0') THEN`
250			`out_wr_i <= '1';`
251			`in_fifo_rd_en <= '1' ;`
252			`state_next <= IN_PACKET;`
253			`END IF;`
254
255
256			`WHEN IN_PACKET =>`
257
258
259			`IF ( fifo_ctrl /= X"00" ) THEN`
260
261			`IF ( out_rdy = '1' ) THEN`
262			`out_wr_i <= '1';`
263			`IF ( words_cnt_ch = '1' ) THEN`
264			`state_next <= IDLE;`
265			`ELSE`
266			`state_next <= LAST;`
267			`END IF;`
268			`END IF;`
269			`ELSIF(out_rdy = '1' AND in_fifo_empty ='0') THEN`
270			`out_wr_i <= '1';`
271			`in_fifo_rd_en <= '1' ;`
272
273			`state_next <= IN_PACKET;`
274			`END IF;`
275
276			`WHEN LAST => IF ( out_rdy = '1' ) THEN`
277			`out_wr_i <= '1';`
278			`state_next <= IDLE;`
279			`END IF;`
280
281			`END CASE;`
282			`END PROCESS;`
283
284
285
286			`---------------Register output`
287
288
289			`WITH state SELECT`
290			`out_data_i <=`
291			`X"00" & ctrl_fifo_dout & X"00"& words_cnt & fifo_data(31 downto 16) & X"00"& bytes_cnt WHEN IN_MODULE_HDRS,`
292			`fifo_data WHEN WORD_1,`
293			`latch_word(63 downto 32) & fifo_data(63 downto 32)WHEN WORD_3,`
294			`latch_word(31 downto 0) & fifo_data(63 downto 32) WHEN IN_PACKET \| LAST,`
295			`(OTHERS=>'0') WHEN OTHERS;`
296
297
298			`out_ctrl_i <= X"FF" when state = IN_MODULE_HDRS else`
299			`last_ctrl when state = IN_PACKET AND fifo_ctrl /= X"00" AND words_cnt_ch='1' else`
300			`last_ctrl when state = LAST else`
301			`X"00" ;`
302			`-- WITH state SELECT`
303			`-- out_wr_i <=`
304			`-- out_rdy WHEN IN_MODULE_HDRS,`
305			`-- in_fifo_rd_en_p WHEN WORD_1,`
306			`-- in_fifo_rd_en_p WHEN WORD_3,`
307			`-- in_fifo_rd_en_p WHEN IN_PACKET ,`
308			`-- out_rdy WHEN LAST,`
309			`-- '0' WHEN OTHERS;`
310			`-- out_wr_t_i <= word_cnt_up when word_cnt >= 1 AND word_cnt <= 21 else`
311			`-- '0';`
312			`PROCESS(clk,reset)`
313			`BEGIN`
314
315			`IF clk'EVENT AND clk ='1' THEN`
316			`IF header_rdy = '1' THEN`
317			`bytes_cnt <= fifo_data(7 downto 0)- X"04";`
318			`IF (fifo_data(15 downto 0)-X"0004") > (fifo_data(45 downto 32)&"000" - X"0008") THEN`
319			`words_cnt <= fifo_data(39 downto 32) ;`
320			`words_cnt_ch <= '0';`
321			`ELSE`
322			`words_cnt <= fifo_data(39 downto 32) - '1' ;`
323			`words_cnt_ch <= '1';`
324			`END IF;`
325			`END IF;`
326			`IF in_fifo_rd_en='1' THEN`
327			`latch_word <= fifo_data;`
328			`END IF;`
329
330			`END IF;`
331			`END PROCESS;`
332			`WITH bytes_cnt(2 DOWNTO 0)SELECT`
333			`last_ctrl <= "00000010" WHEN "111",`
334			`"00000100" WHEN "110",`
335			`"00001000" WHEN "101",`
336			`"00010000" WHEN "100",`
337			`"00100000" WHEN "011",`
338			`"01000000" WHEN "010",`
339			`"10000000" WHEN "001",`
340			`"00000001" WHEN others;`
341
342
343
344			`PROCESS(clk,reset)`
345			`BEGIN`
346			`--`
347			`IF clk'EVENT AND clk ='1' THEN`
348			`out_data <= out_data_i;`
349			`out_ctrl <= out_ctrl_i;`
350			`out_wr <= out_wr_i;`
351			`END IF;`
352			`END PROCESS;`
353			`-- fifo_ctrl_out <=fifo_ctrl;`
354			`-- fifo_data_out <=fifo_data;`
355			`-- latch_word_out <= latch_word;`
356			`END behavior;`
357