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[/] [lp_iir_filter/] [trunk/] [SRC/] [Calculator2.vhd] - Blame information for rev 2

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---------------------------------------------------------------------
----                                                             ----
----  IIR Filter IP core                                         ----
----                                                             ----
----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
----  Company: Unicore Systems http://unicore.co.ua              ----
----                                                             ----
----  Downloaded from: http://www.opencores.org                  ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
---- www.unicore.co.ua                                           ----
---- o.uzenkov@unicore.co.ua                                     ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
----                                                             ----
---------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all,
IEEE.STD_LOGIC_ARITH.all,IEEE.STD_LOGIC_SIGNED.ALL;
 
entity Calculator is
        port(CLK : in STD_LOGIC;
                RST : in STD_LOGIC;
                EF : in STD_LOGIC;
                F : in STD_LOGIC_VECTOR(11 downto 0);
                A0 : out STD_LOGIC_VECTOR(11 downto 0);
                A1 : out STD_LOGIC_VECTOR(11 downto 0);
                B1 : out STD_LOGIC_VECTOR(11 downto 0);
                SH : out STD_LOGIC_VECTOR(3 downto 0));
end Calculator;
 
 
architecture LPF2 of Calculator is
 
        Constant cb:std_logic_vector(11 downto 0):=X"440";
        Constant ca10:std_logic_vector(11 downto 0):=X"0e2"; --1 diap.
        Constant ca11:std_logic_vector(11 downto 0):=X"0f0";
        Constant ca0:std_logic_vector(11 downto 0):=X"028";
        signal a,c,sr,fi : std_logic_vector(11 downto 0);
        signal ac : std_logic_vector(2 downto 0);
        signal q : std_logic_vector(11 downto 0);
        signal st:      std_logic_vector(4 downto 0):="00000";
        type op_t is (add,sub,csubf,csuba);     -- addc, 
        signal op: op_t;
        signal we,wsr,shift,shiftr,eb1,ea1,ea0,esh,ea,ra:STD_logic;
        signal shi:std_logic_vector(3 downto 0):="0001";
        signal shii:std_logic_vector(3 downto 0):="0001";
        signal fn:std_logic_vector(8 downto 0);
 
 
begin
        shi<="0001" when (fi(11)='1' or fi(10)='1') else
        "0010" when fi(9)='1' else
        "0100" when fi(8)='1' else "1000";
        with shi select
        fn<=fi(11 downto 3) when "0001",
        fi(10 downto 2) when "0010",
        fi(9 downto 1) when "0100",
        fi(8 downto 0) when others;
 
 
 
        ROM:with ac select
        c<=X"000" when  "000"|"100",
        cb when "001"|"101",
        ca11 when "010",
        ca10 when "110",
        ca0 when others;
 
        ALU:with op select
        q<=c - ('0'&fn) when csubf,
        a + sr when add,
        a - sr when sub,
        --      a + c  when addc,
        c - a when others;
 
 
        RR:process(CLK,rst)
        begin
                if RST='1' then
                        a<=X"000";
                        sr<=X"000";
                elsif CLK'event and CLK='1' then  --CLK rising edge   
                        if we='1' then
                                a <= q;
                        elsif ra='1' then
                                a<=X"000";
                        end if;
                        if wsr='1' then
                                sr<= a;
                        elsif shift='1' then
                                sr<=sr(10 downto 0)&'0';
                        elsif shiftr='1' then
                                sr<=sr(11)&sr(11 downto 1);
                        end if;
                end if;
        end process;
 
        FSM:process(CLK,RST,st)
        begin
                if RST='1' then
                        st<= "00000";
                elsif CLK'event and CLK='1' then  --CLK rising edge 
                        if EF='1' and st= "00000" then
                                st<= st+1;
                        elsif st/= "00000" then
                                st<= st+1;
                        end if;
                end if;
                op<=add;
                ea<='0';
                ra<='0';
                we<='0';
                eb1<='0';
                ea1<='0';ea0<='0';esh<='0';
                ac(1 downto 0)<="00";
                ac(2)<= shi(0);
                shift<='0';
                shiftr<='0';
                wsr<='0';
                case st is
                        when "00001" =>op<=add; esh<='1';
                        when "00010" =>op<=csubf; eb1<='1'; ac(0)<='1';-- c0-f->b1
                        when "00011" =>op<=csubf; we<='1';  ac(1)<='1';--c1-f->a
                        when "00100" =>op<=csuba;we<='1';               --f-c1 ->a
                        when "00101" =>op<=csuba;wsr<='1';              --f-c1 ->sr
                        when "00110" =>op<=add; shift<='1';
                        when "00111" =>op<=add; we<='1'; shift<='1';    -- a1+2a1->a
                        when "01000" =>op<=add; shift<='1';
                        when "01001" =>op<=add; we<='1'; ea1<='1'; --a1+2a1+8a1->a1,a
                        when "01010" =>op<=add; wsr<='1';                --a1+2a1+8a1->sr
                        when "01011" =>op<=add; shiftr<='1';
                        when "01100" =>op<=add; ra<='1'; shiftr<='1';   --      0->a
                        when "01101" =>op<=add; we<='1'; shiftr<='1';       --c1/4->a
                        when "01110" =>op<=add; we<='1'; shiftr<='1';   --a1/4+a1/8->a
                        when "01111" =>op<=add; shiftr<='1';
                        when "10000" =>op<=add; we<='1';  -- a1/4+a1/8+a1/32->a
                        when "10001" =>op<=csuba;we<='1';ea0<='1';ac(1)<='1';ac(0)<='1';--C0-a->a0
                        when others=> null;
                end case;
 
 
        end process;
 
 
 
        ROUT:process(CLK,RST)
        begin
                if RST='1' then
                        b1<= X"441";
                        a1<= X"c79";
                        a0<= X"1f8";
                        fi<= X"000";
                        shii<="0001";      --0-� �����
                elsif CLK'event and CLK='1' then  --CLK rising edge 
                        if eb1='1' then
                                b1<= q;
                        end if;
                        if ea1='1' then
                                a1<= q;
                        end if;if ea0='1' then
                                a0<= q;
                        end if;
                        if esh='1' then
                                fi<=F;
                        end if;
                        shii<= shi;
                end if;
        end process;
        SH<=shii;
end LPF2;

Line No.	Rev	Author	Line
1	2	unicore	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- IIR Filter IP core ----`
4			`---- ----`
5			`---- Authors: Anatoliy Sergienko, Volodya Lepeha ----`
6			`---- Company: Unicore Systems http://unicore.co.ua ----`
7			`---- ----`
8			`---- Downloaded from: http://www.opencores.org ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2006-2010 Unicore Systems LTD ----`
13			`---- www.unicore.co.ua ----`
14			`---- o.uzenkov@unicore.co.ua ----`
15			`---- ----`
16			`---- This source file may be used and distributed without ----`
17			`---- restriction provided that this copyright statement is not ----`
18			`---- removed from the file and that any derivative work contains ----`
19			`---- the original copyright notice and the associated disclaimer.----`
20			`---- ----`
21			`---- THIS SOFTWARE IS PROVIDED "AS IS" ----`
22			`---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----`
23			`---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----`
24			`---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----`
25			`---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----`
26			`---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----`
27			`---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
28			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----`
29			`---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----`
30			`---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----`
31			`---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----`
32			`---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----`
33			`---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
34			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----`
35			`---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----`
36			`---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----`
37			`---- ----`
38			`---------------------------------------------------------------------`
39			`---------------------------------------------------------------------------------------------------`
40			`library IEEE;`
41			`use IEEE.STD_LOGIC_1164.all,`
42			`IEEE.STD_LOGIC_ARITH.all,IEEE.STD_LOGIC_SIGNED.ALL;`
43
44			`entity Calculator is`
45			`port(CLK : in STD_LOGIC;`
46			`RST : in STD_LOGIC;`
47			`EF : in STD_LOGIC;`
48			`F : in STD_LOGIC_VECTOR(11 downto 0);`
49			`A0 : out STD_LOGIC_VECTOR(11 downto 0);`
50			`A1 : out STD_LOGIC_VECTOR(11 downto 0);`
51			`B1 : out STD_LOGIC_VECTOR(11 downto 0);`
52			`SH : out STD_LOGIC_VECTOR(3 downto 0));`
53			`end Calculator;`
54
55
56			`architecture LPF2 of Calculator is`
57
58			`Constant cb:std_logic_vector(11 downto 0):=X"440";`
59			`Constant ca10:std_logic_vector(11 downto 0):=X"0e2"; --1 diap.`
60			`Constant ca11:std_logic_vector(11 downto 0):=X"0f0";`
61			`Constant ca0:std_logic_vector(11 downto 0):=X"028";`
62			`signal a,c,sr,fi : std_logic_vector(11 downto 0);`
63			`signal ac : std_logic_vector(2 downto 0);`
64			`signal q : std_logic_vector(11 downto 0);`
65			`signal st: std_logic_vector(4 downto 0):="00000";`
66			`type op_t is (add,sub,csubf,csuba); -- addc,`
67			`signal op: op_t;`
68			`signal we,wsr,shift,shiftr,eb1,ea1,ea0,esh,ea,ra:STD_logic;`
69			`signal shi:std_logic_vector(3 downto 0):="0001";`
70			`signal shii:std_logic_vector(3 downto 0):="0001";`
71			`signal fn:std_logic_vector(8 downto 0);`
72
73
74			`begin`
75			`shi<="0001" when (fi(11)='1' or fi(10)='1') else`
76			`"0010" when fi(9)='1' else`
77			`"0100" when fi(8)='1' else "1000";`
78			`with shi select`
79			`fn<=fi(11 downto 3) when "0001",`
80			`fi(10 downto 2) when "0010",`
81			`fi(9 downto 1) when "0100",`
82			`fi(8 downto 0) when others;`
83
84
85
86			`ROM:with ac select`
87			`c<=X"000" when "000"\|"100",`
88			`cb when "001"\|"101",`
89			`ca11 when "010",`
90			`ca10 when "110",`
91			`ca0 when others;`
92
93			`ALU:with op select`
94			`q<=c - ('0'&fn) when csubf,`
95			`a + sr when add,`
96			`a - sr when sub,`
97			`-- a + c when addc,`
98			`c - a when others;`
99
100
101			`RR:process(CLK,rst)`
102			`begin`
103			`if RST='1' then`
104			`a<=X"000";`
105			`sr<=X"000";`
106			`elsif CLK'event and CLK='1' then --CLK rising edge`
107			`if we='1' then`
108			`a <= q;`
109			`elsif ra='1' then`
110			`a<=X"000";`
111			`end if;`
112			`if wsr='1' then`
113			`sr<= a;`
114			`elsif shift='1' then`
115			`sr<=sr(10 downto 0)&'0';`
116			`elsif shiftr='1' then`
117			`sr<=sr(11)&sr(11 downto 1);`
118			`end if;`
119			`end if;`
120			`end process;`
121
122			`FSM:process(CLK,RST,st)`
123			`begin`
124			`if RST='1' then`
125			`st<= "00000";`
126			`elsif CLK'event and CLK='1' then --CLK rising edge`
127			`if EF='1' and st= "00000" then`
128			`st<= st+1;`
129			`elsif st/= "00000" then`
130			`st<= st+1;`
131			`end if;`
132			`end if;`
133			`op<=add;`
134			`ea<='0';`
135			`ra<='0';`
136			`we<='0';`
137			`eb1<='0';`
138			`ea1<='0';ea0<='0';esh<='0';`
139			`ac(1 downto 0)<="00";`
140			`ac(2)<= shi(0);`
141			`shift<='0';`
142			`shiftr<='0';`
143			`wsr<='0';`
144			`case st is`
145			`when "00001" =>op<=add; esh<='1';`
146			`when "00010" =>op<=csubf; eb1<='1'; ac(0)<='1';-- c0-f->b1`
147			`when "00011" =>op<=csubf; we<='1'; ac(1)<='1';--c1-f->a`
148			`when "00100" =>op<=csuba;we<='1'; --f-c1 ->a`
149			`when "00101" =>op<=csuba;wsr<='1'; --f-c1 ->sr`
150			`when "00110" =>op<=add; shift<='1';`
151			`when "00111" =>op<=add; we<='1'; shift<='1'; -- a1+2a1->a`
152			`when "01000" =>op<=add; shift<='1';`
153			`when "01001" =>op<=add; we<='1'; ea1<='1'; --a1+2a1+8a1->a1,a`
154			`when "01010" =>op<=add; wsr<='1'; --a1+2a1+8a1->sr`
155			`when "01011" =>op<=add; shiftr<='1';`
156			`when "01100" =>op<=add; ra<='1'; shiftr<='1'; -- 0->a`
157			`when "01101" =>op<=add; we<='1'; shiftr<='1'; --c1/4->a`
158			`when "01110" =>op<=add; we<='1'; shiftr<='1'; --a1/4+a1/8->a`
159			`when "01111" =>op<=add; shiftr<='1';`
160			`when "10000" =>op<=add; we<='1'; -- a1/4+a1/8+a1/32->a`
161			`when "10001" =>op<=csuba;we<='1';ea0<='1';ac(1)<='1';ac(0)<='1';--C0-a->a0`
162			`when others=> null;`
163			`end case;`
164
165
166			`end process;`
167
168
169
170			`ROUT:process(CLK,RST)`
171			`begin`
172			`if RST='1' then`
173			`b1<= X"441";`
174			`a1<= X"c79";`
175			`a0<= X"1f8";`
176			`fi<= X"000";`
177			`shii<="0001"; --0-� ��`
178			`elsif CLK'event and CLK='1' then --CLK rising edge`
179			`if eb1='1' then`
180			`b1<= q;`
181			`end if;`
182			`if ea1='1' then`
183			`a1<= q;`
184			`end if;if ea0='1' then`
185			`a0<= q;`
186			`end if;`
187			`if esh='1' then`
188			`fi<=F;`
189			`end if;`
190			`shii<= shi;`
191			`end if;`
192			`end process;`
193			`SH<=shii;`
194			`end LPF2;`

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[/] [lp_iir_filter/] [trunk/] [SRC/] [Calculator2.vhd] - Blame information for rev 2