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unicore |
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---- ----
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---- IIR Filter IP core ----
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---- ----
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---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
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---- Company: Unicore Systems http://unicore.co.ua ----
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---- ----
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---- Downloaded from: http://www.opencores.org ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006-2010 Unicore Systems LTD ----
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---- www.unicore.co.ua ----
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---- o.uzenkov@unicore.co.ua ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED "AS IS" ----
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---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
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---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
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---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
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---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
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---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
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---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
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---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
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---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
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---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
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---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
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---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
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---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
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---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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-- Description : FIFO delay
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---------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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--pragma translate_off
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use IEEE.VITAL_Timing.all;
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library UNISIM;
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use UNISIM.VPKG.all;
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--pragma translate_on
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entity DELAY is
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generic(nn:natural:=16;--data width
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l:natural:=8); --FIFO length
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port(
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CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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SE: in STD_LOGIC; --shift enable
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D : in STD_LOGIC_VECTOR(15 downto 0); --Data in
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Q : out STD_LOGIC_VECTOR(15 downto 0) --Data out
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);
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end DELAY;
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architecture SRL_E of DELAY is
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component srl16e
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port(
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D : in std_ulogic;
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CLK : in std_ulogic;
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CE : in std_ulogic;
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A0 : in std_ulogic;
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A1 : in std_ulogic;
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A2 : in std_ulogic;
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A3 : in std_ulogic;
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Q : out std_ulogic);
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end component;
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constant len:std_logic_vector:=CONV_STD_LOGIC_VECTOR(l-1,6);
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constant a0:std_ulogic:=len(0);
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constant a1:std_ulogic:=len(1);
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constant a2:std_ulogic:=len(2);
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constant a3:std_ulogic:=len(3);
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constant a4:std_ulogic:=len(4);
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constant a5:std_ulogic:=len(5);
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constant one:std_ulogic:='1';
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signal di1,di2,di3:std_logic_vector(nn-1 downto 0);
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begin
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D16:if (a5 or a4)='0' generate
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DEL0:for i in 0 to 15 generate
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U_SRL:srl16e port map( D=> D(i),CLK=>CLK,CE=>SE,
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A0=>a0,A1=>a1,A2=>a2,A3=>a3,Q=>Q(i));
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end generate;
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end generate;
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D32:if a5='0' and a4='1' generate
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DEL1:for i in 0 to 15 generate
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U_SRL0:srl16e port map( D=> D(i),CLK=>CLK,CE=>SE,
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A0=>one,A1=>one,A2=>one,A3=>one,Q=>di1(i));
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U_SRL1:srl16e port map( D=> di1(i),CLK=>CLK,CE=>SE,
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A0=>a0,A1=>a1,A2=>a2,A3=>a3,Q=>Q(i));
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end generate;
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end generate;
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D48:if a5='1' and a4='0' generate
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DEL1:for i in 0 to 15 generate
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U_SRL0:srl16e port map( D=> D(i),CLK=>CLK,CE=>SE,
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A0=>one,A1=>one,A2=>one,A3=>one,Q=>di1(i));
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U_SRL1:srl16e port map( D=> di1(i),CLK=>CLK,CE=>SE,
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A0=>one,A1=>one,A2=>one,A3=>one,Q=>di2(i));
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U_SRL2:srl16e port map( D=> di2(i),CLK=>CLK,CE=>SE,
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A0=>a0,A1=>a1,A2=>a2,A3=>a3,Q=>Q(i));
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end generate;
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end generate;
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D64:if a5='1' and a4='1' generate
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DEL1:for i in 0 to 15 generate
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U_SRL0:srl16e port map( D=> D(i),CLK=>CLK,CE=>SE,
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A0=>one,A1=>one,A2=>one,A3=>one,Q=>di1(i));
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U_SRL1:srl16e port map( D=> di1(i),CLK=>CLK,CE=>SE,
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A0=>one,A1=>one,A2=>one,A3=>one,Q=>di2(i));
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U_SRL2:srl16e port map( D=> di2(i),CLK=>CLK,CE=>SE,
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A0=>one,A1=>one,A2=>one,A3=>one,Q=>di3(i));
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U_SRL3:srl16e port map( D=> di3(i),CLK=>CLK,CE=>SE,
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A0=>a0,A1=>a1,A2=>a2,A3=>a3,Q=>Q(i));
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end generate;
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end generate;
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end SRL_E;
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