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[/] [lxp32/] [trunk/] [rtl/] [lxp32_alu.vhd] - Blame information for rev 9

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1 9 ring0_mipt
---------------------------------------------------------------------
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-- Arithmetic logic unit
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--
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-- Part of the LXP32 CPU
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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-- Performs arithmetic and logic operations.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity lxp32_alu is
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        generic(
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                DIVIDER_EN: boolean;
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                MUL_ARCH: string
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        );
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        port(
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                clk_i: in std_logic;
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                rst_i: in std_logic;
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                valid_i: in std_logic;
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                cmd_signed_i: in std_logic;
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                cmd_addsub_i: in std_logic;
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                cmd_mul_i: in std_logic;
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                cmd_div_i: in std_logic;
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                cmd_div_mod_i: in std_logic;
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                cmd_cmp_i: in std_logic;
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                cmd_negate_op2_i: in std_logic;
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                cmd_and_i: in std_logic;
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                cmd_xor_i: in std_logic;
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                cmd_shift_i: in std_logic;
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                cmd_shift_right_i: in std_logic;
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                op1_i: in std_logic_vector(31 downto 0);
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                op2_i: in std_logic_vector(31 downto 0);
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                result_o: out std_logic_vector(31 downto 0);
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                cmp_eq_o: out std_logic;
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                cmp_ug_o: out std_logic;
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                cmp_sg_o: out std_logic;
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                we_o: out std_logic;
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                busy_o: out std_logic
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        );
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end entity;
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architecture rtl of lxp32_alu is
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signal addend1: unsigned(31 downto 0);
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signal addend2: unsigned(31 downto 0);
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signal adder_result: unsigned(32 downto 0);
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signal adder_we: std_logic;
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signal cmp_eq: std_logic;
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signal cmp_carry: std_logic;
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signal cmp_s1: std_logic;
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signal cmp_s2: std_logic;
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signal logic_result: std_logic_vector(31 downto 0);
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signal logic_we: std_logic;
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signal mul_result: std_logic_vector(31 downto 0);
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signal mul_ce: std_logic;
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signal mul_we: std_logic;
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signal div_result: std_logic_vector(31 downto 0);
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signal div_ce: std_logic;
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signal div_we: std_logic;
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signal shift_result: std_logic_vector(31 downto 0);
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signal shift_ce: std_logic;
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signal shift_we: std_logic;
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signal result_mux: std_logic_vector(31 downto 0);
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signal result_we: std_logic;
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signal busy: std_logic:='0';
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begin
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assert MUL_ARCH="dsp" or MUL_ARCH="seq" or MUL_ARCH="opt"
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        report "Invalid MUL_ARCH generic value: dsp, opt or seq expected"
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        severity failure;
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-- Add/subtract
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addend1<=unsigned(op1_i);
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addend2_gen: for i in addend2'range generate
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        addend2(i)<=op2_i(i) xor cmd_negate_op2_i;
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end generate;
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adder_result<=("0"&addend1)+("0"&addend2)+(to_unsigned(0,adder_result'length-1)&cmd_negate_op2_i);
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adder_we<=cmd_addsub_i and valid_i;
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-- Comparator (needs cmd_negate_op2_i to work correctly)
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process (clk_i) is
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begin
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        if rising_edge(clk_i) then
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                if valid_i='1' and cmd_cmp_i='1' then
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                        if op1_i=op2_i then
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                                cmp_eq<='1';
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                        else
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                                cmp_eq<='0';
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                        end if;
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                        cmp_carry<=adder_result(adder_result'high);
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                        cmp_s1<=op1_i(op1_i'high);
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                        cmp_s2<=op2_i(op2_i'high);
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                end if;
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        end if;
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end process;
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cmp_eq_o<=cmp_eq;
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cmp_ug_o<=cmp_carry and not cmp_eq;
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cmp_sg_o<=((cmp_s1 and cmp_s2 and cmp_carry) or
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        (not cmp_s1 and not cmp_s2 and cmp_carry) or
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        (not cmp_s1 and cmp_s2)) and not cmp_eq;
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-- Bitwise operations (and, or, xor)
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-- Note: (a or b) = (a and b) or (a xor b)
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logic_result_gen: for i in logic_result'range generate
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        logic_result(i)<=((op1_i(i) and op2_i(i)) and cmd_and_i) or
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                ((op1_i(i) xor op2_i(i)) and cmd_xor_i);
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end generate;
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logic_we<=(cmd_and_i or cmd_xor_i) and valid_i;
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-- Multiplier
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mul_ce<=cmd_mul_i and valid_i;
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gen_mul_dsp: if MUL_ARCH="dsp" generate
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        mul_inst: entity work.lxp32_mul_dsp(rtl)
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                port map(
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                        clk_i=>clk_i,
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                        rst_i=>rst_i,
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                        ce_i=>mul_ce,
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                        op1_i=>op1_i,
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                        op2_i=>op2_i,
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                        ce_o=>mul_we,
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                        result_o=>mul_result
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                );
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end generate;
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gen_mul_opt: if MUL_ARCH="opt" generate
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        mul_inst: entity work.lxp32_mul_opt(rtl)
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                port map(
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                        clk_i=>clk_i,
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                        rst_i=>rst_i,
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                        ce_i=>mul_ce,
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                        op1_i=>op1_i,
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                        op2_i=>op2_i,
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                        ce_o=>mul_we,
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                        result_o=>mul_result
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                );
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end generate;
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gen_mul_seq: if MUL_ARCH="seq" generate
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        mul_inst: entity work.lxp32_mul_seq(rtl)
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                port map(
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                        clk_i=>clk_i,
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                        rst_i=>rst_i,
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                        ce_i=>mul_ce,
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                        op1_i=>op1_i,
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                        op2_i=>op2_i,
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                        ce_o=>mul_we,
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                        result_o=>mul_result
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                );
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end generate;
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-- Divider
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div_ce<=cmd_div_i and valid_i;
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gen_divider: if DIVIDER_EN generate
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        divider_inst: entity work.lxp32_divider(rtl)
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                port map(
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                        clk_i=>clk_i,
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                        rst_i=>rst_i,
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                        ce_i=>div_ce,
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                        op1_i=>op1_i,
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                        op2_i=>op2_i,
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                        signed_i=>cmd_signed_i,
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                        rem_i=>cmd_div_mod_i,
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                        ce_o=>div_we,
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                        result_o=>div_result
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                );
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end generate;
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gen_no_divider: if not DIVIDER_EN generate
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        div_we<=div_ce;
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        div_result<=(others=>'0');
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end generate;
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-- Shifter
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shift_ce<=cmd_shift_i and valid_i;
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shifter_inst: entity work.lxp32_shifter(rtl)
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        port map(
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                clk_i=>clk_i,
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                rst_i=>rst_i,
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                ce_i=>shift_ce,
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                d_i=>op1_i,
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                s_i=>op2_i(4 downto 0),
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                right_i=>cmd_shift_right_i,
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                sig_i=>cmd_signed_i,
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                ce_o=>shift_we,
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                d_o=>shift_result
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        );
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-- Result multiplexer
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result_mux_gen: for i in result_mux'range generate
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        result_mux(i)<=(adder_result(i) and adder_we) or
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                (logic_result(i) and logic_we) or
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                (mul_result(i) and mul_we) or
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                (div_result(i) and div_we) or
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                (shift_result(i) and shift_we);
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end generate;
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result_o<=result_mux;
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result_we<=adder_we or logic_we or mul_we or div_we or shift_we;
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we_o<=result_we;
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-- Pipeline control
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process (clk_i) is
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begin
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        if rising_edge(clk_i) then
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                if rst_i='1' or result_we='1' then
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                        busy<='0';
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                elsif shift_ce='1' or mul_ce='1' or div_ce='1' then
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                        busy<='1';
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                end if;
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        end if;
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end process;
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busy_o<=busy;
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end architecture;

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