OpenCores
URL https://opencores.org/ocsvn/lxp32/lxp32/trunk

Subversion Repositories lxp32

[/] [lxp32/] [trunk/] [rtl/] [lxp32_ubuf.vhd] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 ring0_mipt
---------------------------------------------------------------------
2
-- Microbuffer
3
--
4
-- Part of the LXP32 CPU
5
--
6
-- Copyright (c) 2016 by Alex I. Kuznetsov
7
--
8
-- A small buffer with a FIFO-like interface, implemented
9
-- using registers.
10
---------------------------------------------------------------------
11
 
12
library ieee;
13
use ieee.std_logic_1164.all;
14
 
15
entity lxp32_ubuf is
16
        generic(
17
                DATA_WIDTH: integer
18
        );
19
        port(
20
                clk_i: in std_logic;
21
                rst_i: in std_logic;
22
 
23
                we_i: in std_logic;
24
                d_i: in std_logic_vector(DATA_WIDTH-1 downto 0);
25
                re_i: in std_logic;
26
                d_o: out std_logic_vector(DATA_WIDTH-1 downto 0);
27
 
28
                empty_o: out std_logic;
29
                full_o: out std_logic
30
        );
31
end entity;
32
 
33
architecture rtl of lxp32_ubuf is
34
 
35
signal we: std_logic;
36
signal re: std_logic;
37
 
38
signal empty: std_logic:='1';
39
signal full: std_logic:='0';
40
 
41
type regs_type is array (1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
42
signal regs: regs_type;
43
signal regs_mux: regs_type;
44
 
45
signal wpointer: std_logic_vector(2 downto 0):="001";
46
 
47
begin
48
 
49
we<=we_i and not full;
50
re<=re_i and not empty;
51
 
52
process (clk_i) is
53
begin
54
        if rising_edge(clk_i) then
55
                if rst_i='1' then
56
                        wpointer<="001";
57
                        empty<='1';
58
                        full<='0';
59
                else
60
                        if re='0' then
61
                                regs<=regs_mux;
62
                        else
63
                                regs(0)<=regs_mux(1);
64
                        end if;
65
 
66
                        if we='1' and re='0' then
67
                                wpointer<=wpointer(1 downto 0)&"0";
68
                                empty<='0';
69
                                full<=wpointer(1);
70
                        elsif we='0' and re='1' then
71
                                wpointer<="0"&wpointer(2 downto 1);
72
                                empty<=wpointer(1);
73
                                full<='0';
74
                        end if;
75
                end if;
76
        end if;
77
end process;
78
 
79
mux: for i in regs_mux'range generate
80
        regs_mux(i)<=regs(i) when we='0' or wpointer(i)='0' else d_i;
81
end generate;
82
 
83
d_o<=regs(0);
84
empty_o<=empty;
85
full_o<=full;
86
 
87
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.