OpenCores
URL https://opencores.org/ocsvn/lzrw1-compressor-core/lzrw1-compressor-core/trunk

Subversion Repositories lzrw1-compressor-core

[/] [lzrw1-compressor-core/] [trunk/] [hw/] [testbench/] [LZRWcompressorTb.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 habicht
--/**************************************************************************************************************
2
--*
3
--*    L Z R W 1   E N C O D E R   C O R E
4
--*
5
--*  A high throughput loss less data compression core.
6
--* 
7
--* Copyright 2012-2013   Lukas Schrittwieser (LS)
8
--*
9
--*    This program is free software: you can redistribute it and/or modify
10
--*    it under the terms of the GNU General Public License as published by
11
--*    the Free Software Foundation, either version 2 of the License, or
12
--*    (at your option) any later version.
13
--*
14
--*    This program is distributed in the hope that it will be useful,
15
--*    but WITHOUT ANY WARRANTY; without even the implied warranty of
16
--*    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
--*    GNU General Public License for more details.
18
--*
19
--*    You should have received a copy of the GNU General Public License
20
--*    along with this program; if not, write to the Free Software
21
--*    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
22
--*    Or see <http://www.gnu.org/licenses/>
23
--*
24
--***************************************************************************************************************
25
--*
26
--* Change Log:
27
--*
28
--* Version 1.0 - 2012/9/16 - LS
29
--*   started file
30
--*
31
--* Version 1.0 - 2013/4/5 - LS
32
--*   release
33
--*
34
--***************************************************************************************************************
35
--*
36
--* Naming convention:  http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
37
--*
38
--***************************************************************************************************************
39
--*
40
--* This is a file based testbench for the LZRW1 compressor core. It reads data
41
--* binary from a configured file, and feeds it int the core. The compressed data
42
--* is stored in a second file for verifycation. (Use the two java programs
43
--* provided with this project to create and verify test vectors)
44
--*
45
--***************************************************************************************************************
46
 
47
library ieee;
48
use ieee.std_logic_1164.all;
49
use IEEE.NUMERIC_STD.all;
50
use std.textio.all;
51
 
52
-------------------------------------------------------------------------------
53
 
54
entity LZRWcompressor_tb is
55
 
56
end LZRWcompressor_tb;
57
 
58
-------------------------------------------------------------------------------
59
 
60
architecture tb of LZRWcompressor_tb is
61
 
62
  component LZRWcompressor
63
    port (
64
      ClkxCI         : in  std_logic;
65
      RstxRI         : in  std_logic;
66
      DataInxDI      : in  std_logic_vector(7 downto 0);
67
      StrobexSI      : in  std_logic;
68
      FlushBufxSI    : in  std_logic;
69
      BusyxSO        : out std_logic;
70
      DonexSO        : out std_logic;
71
      BufOutxDO      : out std_logic_vector(7 downto 0);
72
      OutputValidxSO : out std_logic;
73
      RdStrobexSI    : in  std_logic;
74
      LengthxDO      : out integer range 0 to 1024);
75
  end component;
76
 
77
  -- component ports
78
  signal ClkxCI         : std_logic;
79
  signal RstxRI         : std_logic                    := '1';
80
  signal DInxDI         : std_logic_vector(7 downto 0) := (others => '0');
81
  signal StrobexSI      : std_logic                    := '0';
82
  signal FlushBufxSI    : std_logic                    := '0';
83
  signal BusyxSO        : std_logic;
84
  signal DonexSO        : std_logic;
85
  signal BufOutxDO      : std_logic_vector(7 downto 0);
86
  signal OutputValidxSO : std_logic;
87
  signal RdStrobexSI    : std_logic                    := '0';
88
  signal LengthxDO      : integer range 0 to 1024;
89
 
90
 
91
  -- clock
92
  signal Clk : std_logic := '1';
93
 
94
 
95
  signal TbDone : std_logic := '0';
96
 
97
  -- configuration
98
  constant DATA_IN_FILE_NAME  : string := "../../test files/TVect1.bin";  -- file with stimuli which will be compressed (relative to XST directroy)
99
  constant DATA_OUT_FILE_NAME : string := "../../test files/TVect1.cmp";  -- filename for compressed data
100
 
101
  constant PERIOD : time := 20 ns;
102
 
103
  type binFileType is file of character;
104
 
105
begin  -- tb
106
 
107
  -- component instantiation
108
  DUT : LZRWcompressor
109
    port map (
110
      ClkxCI         => ClkxCI,
111
      RstxRI         => RstxRI,
112
      DataInxDI      => DInxDI,
113
      StrobexSI      => StrobexSI,
114
      FlushBufxSI    => FlushBufxSI,
115
      BusyxSO        => BusyxSO,
116
      DonexSO        => DonexSO,
117
      BufOutxDO      => BufOutxDO,
118
      OutputValidxSO => OutputValidxSO,
119
      RdStrobexSI    => RdStrobexSI,
120
      LengthxDO      => LengthxDO
121
      );
122
 
123
  -- clock generation
124
  Clk    <= not Clk after (PERIOD / 2);
125
  ClkxCI <= Clk;
126
 
127
  -- waveform generation
128
  WaveGen_Proc : process
129
    file srcFile     : binFileType is in DATA_IN_FILE_NAME;  -- uncompressed data input in file
130
    variable srcChar : character;
131
    variable l       : line;
132
  begin
133
    wait for PERIOD;
134
    wait until Clk'event and Clk = '1';
135
    RstxRI <= '0';
136
 
137
    while not endfile(srcFile) loop
138
      read(srcFile, srcChar);
139
--      write(l, "found char ");
140
--      write(l, character'image(srcChar));
141
--      write(l, "   ");
142
--      write(l, character'pos(srcChar));
143
--      writeline(OUTPUT, l);
144
 
145
      wait until Clk'event and Clk = '1';
146
      if BusyxSO = '0' then
147
        DInxDI    <= std_logic_vector(to_unsigned(character'pos(srcChar), 8));
148
        StrobexSI <= '1';
149
      end if;
150
      wait until Clk'event and Clk = '1';
151
      StrobexSI <= '0';
152
      DInxDI    <= "--------";
153
 
154
    end loop;
155
    StrobexSI <= '0';
156
 
157
    for i in 0 to 10 loop
158
      wait until Clk'event and Clk = '1';
159
    end loop;
160
 
161
    --wait until Clk'event and Clk = '1';
162
    FlushBufxSI <= '1';
163
    wait until Clk'event and Clk = '1';
164
    FlushBufxSI <= '0';
165
 
166
    file_close(srcFile);
167
 
168
    for i in 0 to 10 loop
169
      wait until Clk'event and Clk = '1';
170
    end loop;
171
 
172
    TbDone <= '1';
173
 
174
    wait;
175
 
176
  end process WaveGen_Proc;
177
 
178
  -- process to receive compressed data from the core and store it in a file
179
  pickupPrcs : process
180
    file destFile     : binFileType is out DATA_OUT_FILE_NAME;  -- receives compressed data
181
    variable destChar : character;
182
    variable l        : line;
183
  begin
184
 
185
    while true loop
186
      wait until Clk'event and Clk = '1';
187
      if LengthxDO > 0 then
188
        RdStrobexSI <= '1';
189
      else
190
        RdStrobexSI <= '0';
191
      end if;
192
      if OutputValidxSO = '1' then
193
        --     wait until Clk'event and Clk = '1';
194
        destChar := character'val(to_integer(unsigned(BufOutxDO)));
195
        write(destFile, destChar);
196
      end if;
197
    end loop;
198
 
199
    file_close(destFile);
200
    wait;
201
  end process;
202
 
203
 
204
end tb;
205
 
206
-------------------------------------------------------------------------------
207
 
208
configuration LZRWcompressor_tb_tb_cfg of LZRWcompressor_tb is
209
  for tb
210
  end for;
211
end LZRWcompressor_tb_tb_cfg;
212
 
213
-------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.