URL https://opencores.org/ocsvn/lzrw1-compressor-core/lzrw1-compressor-core/trunk

Subversion Repositories lzrw1-compressor-core

[/] [lzrw1-compressor-core/] [trunk/] [hw/] [xst_14_2/] [iseconfig/] [LZRWcompressor.projectmgr] - Blame information for rev 2

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         2
      
      
         LZRWcompressor.ucf (/home/lukas/e-/logic-analyzer/LZRW-compressor/hw/xst_14_2/LZRWcompressor.ucf)
      
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      LZRWcompressor.ucf (/home/lukas/e-/logic-analyzer/LZRW-compressor/hw/xst_14_2/LZRWcompressor.ucf)
   
   
      
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         1
         Configure Target Device
         Design Utilities
         Implement Design/Map
         Implement Design/Place & Route/Back-annotate Pin Locations
         Implement Design/Place & Route/Generate IBIS Model
         Implement Design/Place & Route/Generate Post-Place & Route Static Timing
         Implement Design/Translate
         User Constraints
      
      
         Analyze Timing / Floorplan Design (PlanAhead)
      
      8
      0
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      Analyze Timing / Floorplan Design (PlanAhead)
   
   
      
         2
         /CompressorTop_tb - TB |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|CompressorTopTb.vhd
         /CompressorTop_tb - TB |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|CompressorTopTb.vhd/DUT - CompressorTop - Behavioral/LZRWcompressorInst - LZRWcompressor - Behavioral
         /HashTable_tb - tb D:|e-|logic-analyzer|compression-test|hw|testbench|TbHash.vhd
         /HashTable_tb - tb G:|e-|logic-analyzer|LZRW-compressor|hw|testbench|TbHash.vhd
         /HashTable_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|TbHash.vhd
         /InputFIFO_tb - tb D:|e-|logic-analyzer|compression-test|hw|testbench|InputFIFOTb.vhd
         /InputFIFO_tb - tb G:|e-|logic-analyzer|LZRW-compressor|hw|testbench|InputFIFOTb.vhd
         /InputFIFO_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|InputFIFOTb.vhd
         /LZRWcompressor_tb - tb D:|e-|logic-analyzer|compression-test|hw|testbench|LZRWcompressorTb.vhd
         /LZRWcompressor_tb - tb G:|e-|logic-analyzer|LZRW-compressor|hw|testbench|LZRWcompressorTb.vhd
         /LZRWcompressor_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|LZRWcompressorTb.vhd
         /comparator_tb - Tb D:|e-|logic-analyzer|compression-test|hw|HDL|comparator_tb.vhd
         /comparator_tb - Tb G:|e-|logic-analyzer|LZRW-compressor|hw|HDL|comparator_tb.vhd
         /comparator_tb - Tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|HDL|comparator_tb.vhd
         /historyBuffer_tb - tb D:|e-|logic-analyzer|compression-test|hw|HDL|historyTb.vhd
         /historyBuffer_tb - tb G:|e-|logic-analyzer|LZRW-compressor|hw|HDL|historyTb.vhd
         /historyBuffer_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|HDL|historyTb.vhd
         /outputEncoder_tb - Tb D:|e-|logic-analyzer|compression-test|hw|testbench|outputEncoderTb.vhd
         /outputEncoder_tb - Tb G:|e-|logic-analyzer|LZRW-compressor|hw|testbench|outputEncoderTb.vhd
         /outputEncoder_tb - Tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|outputEncoderTb.vhd
         /outputFIFO_tb - tb D:|e-|logic-analyzer|compression-test|hw|testbench|outputFIFOTb.vhd
         /outputFIFO_tb - tb G:|e-|logic-analyzer|LZRW-compressor|hw|testbench|outputFIFOTb.vhd
         /outputFIFO_tb - tb |home|lukas|e-|logic-analyzer|LZRW-compressor|hw|testbench|outputFIFOTb.vhd
      
      
         Unassigned User Library Modules
      
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         Simulate Behavioral Model
      
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      Simulate Behavioral Model
   
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         1
      
      
         Edit Constraints (Text)
      
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Line No.	Rev	Author	Line
1	2	habicht
2
3
4
5
6
7
8
9			`2`
10
11
12			`LZRWcompressor.ucf (/home/lukas/e-/logic-analyzer/LZRW-compressor/hw/xst_14_2/LZRWcompressor.ucf)`
13
14			`0`
15			`0`
16			`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000011e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000011e0000000100000000000000000000000100000000`
17			`true`
18			`LZRWcompressor.ucf (/home/lukas/e-/logic-analyzer/LZRW-compressor/hw/xst_14_2/LZRWcompressor.ucf)`
19
20
21
22			`1`
23			`Design Utilities`
24
25
26
27
28			`0`
29			`0`
30			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000012d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012d0000000100000000`
31			`false`
32
33
34
35
36			`1`
37
38
39			`0`
40			`0`
41			`000000ff000000000000000100000000000000000100000000000000000000000000000000000002af000000040101000100000000000000000000000064ffffffff000000810000000000000004000000510000000100000000000000290000000100000000000000840000000100000000000001b10000000100000000`
42			`false`
43			`hash.vhd`
44
45
46
47			`1`
48			`work`
49
50
51			`0`
52			`0`
53			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000`
54			`false`
55			`work`
56
57
58
59			`1`
60			`Configure Target Device`
61			`Design Utilities`
62			`Implement Design/Map`
63			`Implement Design/Place & Route/Back-annotate Pin Locations`
64			`Implement Design/Place & Route/Generate IBIS Model`
65			`Implement Design/Place & Route/Generate Post-Place & Route Static Timing`
66			`Implement Design/Translate`
67			`User Constraints`
68
69
70			`Analyze Timing / Floorplan Design (PlanAhead)`
71
72			`8`
73			`0`
74			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000`
75			`false`
76			`Analyze Timing / Floorplan Design (PlanAhead)`
77
78
79
80			`2`
81			`/CompressorTop_tb - TB \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|CompressorTopTb.vhd`
82			`/CompressorTop_tb - TB \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|CompressorTopTb.vhd/DUT - CompressorTop - Behavioral/LZRWcompressorInst - LZRWcompressor - Behavioral`
83			`/HashTable_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|TbHash.vhd`
84			`/HashTable_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|TbHash.vhd`
85			`/HashTable_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|TbHash.vhd`
86			`/InputFIFO_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|InputFIFOTb.vhd`
87			`/InputFIFO_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|InputFIFOTb.vhd`
88			`/InputFIFO_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|InputFIFOTb.vhd`
89			`/LZRWcompressor_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|LZRWcompressorTb.vhd`
90			`/LZRWcompressor_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|LZRWcompressorTb.vhd`
91			`/LZRWcompressor_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|LZRWcompressorTb.vhd`
92			`/comparator_tb - Tb D:\|e-\|logic-analyzer\|compression-test\|hw\|HDL\|comparator_tb.vhd`
93			`/comparator_tb - Tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|comparator_tb.vhd`
94			`/comparator_tb - Tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|comparator_tb.vhd`
95			`/historyBuffer_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|HDL\|historyTb.vhd`
96			`/historyBuffer_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|historyTb.vhd`
97			`/historyBuffer_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|HDL\|historyTb.vhd`
98			`/outputEncoder_tb - Tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|outputEncoderTb.vhd`
99			`/outputEncoder_tb - Tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputEncoderTb.vhd`
100			`/outputEncoder_tb - Tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputEncoderTb.vhd`
101			`/outputFIFO_tb - tb D:\|e-\|logic-analyzer\|compression-test\|hw\|testbench\|outputFIFOTb.vhd`
102			`/outputFIFO_tb - tb G:\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputFIFOTb.vhd`
103			`/outputFIFO_tb - tb \|home\|lukas\|e-\|logic-analyzer\|LZRW-compressor\|hw\|testbench\|outputFIFOTb.vhd`
104
105
106			`Unassigned User Library Modules`
107
108			`0`
109			`0`
110			`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000018e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000018e0000000100000000000000000000000100000000`
111			`false`
112			`Unassigned User Library Modules`
113
114
115
116			`1`
117			`Design Utilities`
118
119
120
121
122			`0`
123			`0`
124			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000`
125			`false`
126
127
128
129
130			`1`
131
132
133			`Simulate Behavioral Model`
134
135			`0`
136			`0`
137			`000000ff000000000000000100000001000000000000000000000000000000000000000000000001ab000000010000000100000000000000000000000064ffffffff000000810000000000000001000001ab0000000100000000`
138			`false`
139			`Simulate Behavioral Model`
140
141			`000000ff0000000000000002000000c20000008b01000000060100000002`
142			`Behavioral Simulation`
143
144
145			`1`
146
147
148			`Edit Constraints (Text)`
149
150			`0`
151			`0`
152			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000`
153			`false`
154			`Edit Constraints (Text)`
155
156

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Subversion Repositories lzrw1-compressor-core

[/] [lzrw1-compressor-core/] [trunk/] [hw/] [xst_14_2/] [iseconfig/] [LZRWcompressor.projectmgr] - Blame information for rev 2