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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity test_sim is
end test_sim;
 
architecture Behavioral of test_sim is
 
        COMPONENT singleDouble_original
        PORT(
    clk_i   :  in  std_logic;
    ce_i    :  in  std_logic;
    rst_i   :  in  std_logic;
    data_i  :  in  std_logic;
    q_o     :  out std_logic_vector(3 downto 0);
    ready_o :  out std_logic
                );
        END COMPONENT;
 
  COMPONENT singleDouble
        PORT(
    clk_i   :  in  std_logic;
    ce_i    :  in  std_logic;
    rst_i   :  in  std_logic;
    data_i  :  in  std_logic;
    q_o     :  out std_logic_vector(3 downto 0);
    ready_o :  out std_logic
                );
        END COMPONENT;
 
  signal clk : std_logic := '0';
  signal ce_i : std_logic := '0';
  signal mdi : std_logic := '0';
  signal q_orig : std_logic_vector(3 downto 0);
  signal nd_orig : std_logic;
  signal q_modified : std_logic_vector(3 downto 0);
  signal nd_modified : std_logic;
 
  constant period : time := 10 ns;
  constant md_period : time := period*16;
  signal reset : std_logic := '1';
begin
 
        Inst_orig: singleDouble_original PORT MAP(
    clk_i =>  clk,
    ce_i  =>  ce_i,
    rst_i  =>  reset,
    data_i   =>  mdi,
    q_o     =>  q_orig,
    ready_o    =>  nd_orig
        );
 
  Inst_modified: singleDouble PORT MAP(
    clk_i =>  clk,
    ce_i  =>  ce_i,
    rst_i  =>  reset,
    data_i   =>  mdi,
    q_o     =>  q_modified,
    ready_o    =>  nd_modified
  );
 
  process
  begin
    loop
      reset <= '1';
      ce_i <= '0';
 
      wait for (2*md_period);
 
      reset <= '0';
      ce_i <= '1';
 
      wait for 2*md_period;
 
      mdi <= not mdi;
      wait for 2*md_period;
 
      mdi <= not mdi;
      wait for md_period;
 
      mdi <= not mdi;
      wait for md_period;
 
      mdi <= not mdi;
      wait for md_period;
 
      mdi <= not mdi;
      wait for 2*md_period;
 
      mdi <= not mdi;
      wait for md_period;
 
      mdi <= not mdi;
      wait for 5*md_period;
    end loop;
  end process;
 
  process
  begin
    loop
      clk <= not clk;
      wait for period/2;
    end loop;
  end process;
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	7	kingmu	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6
7			`entity test_sim is`
8			`end test_sim;`
9
10			`architecture Behavioral of test_sim is`
11
12			`COMPONENT singleDouble_original`
13			`PORT(`
14			`clk_i : in std_logic;`
15			`ce_i : in std_logic;`
16			`rst_i : in std_logic;`
17			`data_i : in std_logic;`
18			`q_o : out std_logic_vector(3 downto 0);`
19			`ready_o : out std_logic`
20			`);`
21			`END COMPONENT;`
22
23			`COMPONENT singleDouble`
24			`PORT(`
25			`clk_i : in std_logic;`
26			`ce_i : in std_logic;`
27			`rst_i : in std_logic;`
28			`data_i : in std_logic;`
29			`q_o : out std_logic_vector(3 downto 0);`
30			`ready_o : out std_logic`
31			`);`
32			`END COMPONENT;`
33
34			`signal clk : std_logic := '0';`
35			`signal ce_i : std_logic := '0';`
36			`signal mdi : std_logic := '0';`
37			`signal q_orig : std_logic_vector(3 downto 0);`
38			`signal nd_orig : std_logic;`
39			`signal q_modified : std_logic_vector(3 downto 0);`
40			`signal nd_modified : std_logic;`
41
42			`constant period : time := 10 ns;`
43			`constant md_period : time := period*16;`
44			`signal reset : std_logic := '1';`
45			`begin`
46
47			`Inst_orig: singleDouble_original PORT MAP(`
48			`clk_i => clk,`
49			`ce_i => ce_i,`
50			`rst_i => reset,`
51			`data_i => mdi,`
52			`q_o => q_orig,`
53			`ready_o => nd_orig`
54			`);`
55
56			`Inst_modified: singleDouble PORT MAP(`
57			`clk_i => clk,`
58			`ce_i => ce_i,`
59			`rst_i => reset,`
60			`data_i => mdi,`
61			`q_o => q_modified,`
62			`ready_o => nd_modified`
63			`);`
64
65			`process`
66			`begin`
67			`loop`
68			`reset <= '1';`
69			`ce_i <= '0';`
70
71			`wait for (2*md_period);`
72
73			`reset <= '0';`
74			`ce_i <= '1';`
75
76			`wait for 2*md_period;`
77
78			`mdi <= not mdi;`
79			`wait for 2*md_period;`
80
81			`mdi <= not mdi;`
82			`wait for md_period;`
83
84			`mdi <= not mdi;`
85			`wait for md_period;`
86
87			`mdi <= not mdi;`
88			`wait for md_period;`
89
90			`mdi <= not mdi;`
91			`wait for 2*md_period;`
92
93			`mdi <= not mdi;`
94			`wait for md_period;`
95
96			`mdi <= not mdi;`
97			`wait for 5*md_period;`
98			`end loop;`
99			`end process;`
100
101			`process`
102			`begin`
103			`loop`
104			`clk <= not clk;`
105			`wait for period/2;`
106			`end loop;`
107			`end process;`
108
109			`end Behavioral;`
110

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[/] [manchesterwireless/] [branches/] [singledouble/] [singleDouble/] [simTest.vhd] - Blame information for rev 7