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`timescale 1ns / 1ps
`default_nettype none
////////////////////////////////////////////////////////////////////////
// 
// 4004 CPU Integration Module
// 
// This file is part of the MCS-4 project hosted at OpenCores:
//      http://www.opencores.org/cores/mcs-4/
// 
// Copyright � 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
// 
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
// 
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
 
module i4004(
    input  wire                 sysclk,
    input  wire                 clk1_pad,
    input  wire                 clk2_pad,
    input  wire                 poc_pad,
    input  wire                 test_pad,
    inout  wire [3:0]    data_pad,
    output wire                 cmrom_pad,
    output wire                 cmram0_pad,
    output wire                 cmram1_pad,
    output wire                 cmram2_pad,
    output wire                 cmram3_pad,
    output wire                 sync_pad
    );
 
        // Common BiDir data bus
        wire [3:0]               data;
 
        // Timing and I/O Board Outputs
        wire                    clk1;
        wire                    clk2;
        wire                    a12;
        wire                    a22;
        wire                    a32;
        wire                    m12;
        wire                    m22;
        wire                    x12;
        wire                    x22;
        wire                    x32;
        wire                    gate;
        wire                    poc;                    // Clean POC_PAD
        wire                    n0432;                  // Clean TEST_PAD
 
        // Outputs from the Instruction Decode board
        wire                    jcn_isz;
        wire                    jin_fin;
        wire                    jun_jms;
        wire                    cn_n;
        wire                    bbl;
        wire                    jms;
        wire                    sc;
        wire                    dc;
        wire                    n0636;
        wire                    sc_m22_clk2;
        wire                    fin_fim_src_jin;
        wire                    inc_isz_add_sub_xch_ld;
        wire                    inc_isz_xch;
        wire                    opa0_n;
        wire                    cma;
        wire                    write_acc_1;
        wire                    write_carry_2;
        wire                    read_acc_3;
        wire                    add_group_4;
        wire                    inc_group_5;
        wire                    sub_group_6;
        wire                    ior;
        wire                    iow;
        wire                    ral;
        wire                    rar;
        wire                    ope_n;
        wire                    daa;
        wire                    dcl;
        wire                    inc_isz;
        wire                    kbp;
        wire                    o_ib;
        wire                    tcs;
        wire                    xch;
        wire                    n0342;
        wire                    x21_clk2;
        wire                    x31_clk2;
        wire                    com_n;
 
        // Outputs from the ALU board
        wire                    acc_0;
        wire                    add_0;
        wire                    cy_1;
        wire                    cmram0;
        wire                    cmram1;
        wire                    cmram2;
        wire                    cmram3;
        wire                    cmrom;
 
        // Instantiate the Timing and I/O board
        timing_io tio_board (
                .sysclk(sysclk),
                .clk1_pad(clk1_pad),
                .clk2_pad(clk2_pad),
                .poc_pad(poc_pad),
                .ior(ior),
                .clk1(clk1),
                .clk2(clk2),
                .a12(a12),
                .a22(a22),
                .a32(a32),
                .m12(m12),
                .m22(m22),
                .x12(x12),
                .x22(x22),
                .x32(x32),
                .gate(gate),
                .poc(poc),
                .data(data),
                .data_pad(data_pad),
                .test_pad(test_pad),
                .n0432(n0432),
                .sync_pad(sync_pad),
                .cmrom(cmrom),
                .cmrom_pad(cmrom_pad),
                .cmram0(cmram0),
                .cmram0_pad(cmram0_pad),
                .cmram1(cmram1),
                .cmram1_pad(cmram1_pad),
                .cmram2(cmram2),
                .cmram2_pad(cmram2_pad),
                .cmram3(cmram3),
                .cmram3_pad(cmram3_pad)
        );
 
        // Instantiate the Instruction Decode board
        instruction_decode id_board (
                .sysclk(sysclk),
                .clk1(clk1),
                .clk2(clk2),
                .a22(a22),
                .m12(m12),
                .m22(m22),
                .x12(x12),
                .x22(x22),
                .x32(x32),
                .poc(poc),
                .n0432(n0432),
                .data(data),
                .jcn_isz(jcn_isz),
                .jin_fin(jin_fin),
                .jun_jms(jun_jms),
                .cn_n(cn_n),
                .bbl(bbl),
                .jms(jms),
                .sc(sc),
                .dc(dc),
                .n0636(n0636),
                .sc_m22_clk2(sc_m22_clk2),
                .fin_fim_src_jin(fin_fim_src_jin),
                .inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
                .inc_isz_xch(inc_isz_xch),
                .opa0_n(opa0_n),
                .acc_0(acc_0),
                .add_0(add_0),
                .cy_1(cy_1),
                .cma(cma),
                .write_acc_1(write_acc_1),
                .write_carry_2(write_carry_2),
                .read_acc_3(read_acc_3),
                .add_group_4(add_group_4),
                .inc_group_5(inc_group_5),
                .sub_group_6(sub_group_6),
                .ior(ior),
                .iow(iow),
                .ral(ral),
                .rar(rar),
                .ope_n(ope_n),
                .daa(daa),
                .dcl(dcl),
                .inc_isz(inc_isz),
                .kbp(kbp),
                .o_ib(o_ib),
                .tcs(tcs),
                .xch(xch),
                .n0342(n0342),
                .x21_clk2(x21_clk2),
                .x31_clk2(x31_clk2),
                .com_n(com_n)
        );
 
        // Instantiate the ALU board
        alu alu_board (
                .sysclk(sysclk),
                .a12(a12),
                .m12(m12),
                .x12(x12),
                .poc(poc),
                .data(data),
                .acc_0(acc_0),
                .add_0(add_0),
                .cy_1(cy_1),
                .cma(cma),
                .write_acc_1(write_acc_1),
                .write_carry_2(write_carry_2),
                .read_acc_3(read_acc_3),
                .add_group_4(add_group_4),
                .inc_group_5(inc_group_5),
                .sub_group_6(sub_group_6),
                .ior(ior),
                .iow(iow),
                .ral(ral),
                .rar(rar),
                .ope_n(ope_n),
                .daa(daa),
                .dcl(dcl),
                .inc_isz(inc_isz),
                .kbp(kbp),
                .o_ib(o_ib),
                .tcs(tcs),
                .xch(xch),
                .n0342(n0342),
                .x21_clk2(x21_clk2),
                .x31_clk2(x31_clk2),
                .com_n(com_n),
                .cmram0(cmram0),
                .cmram1(cmram1),
                .cmram2(cmram2),
                .cmram3(cmram3),
                .cmrom(cmrom)
        );
 
        // Instantiate the Instruction Pointer board
        instruction_pointer ip_board (
                .sysclk(sysclk),
                .clk1(clk1),
                .clk2(clk2),
                .a12(a12),
                .a22(a22),
                .a32(a32),
                .m12(m12),
                .m22(m22),
                .x12(x12),
                .x22(x22),
                .x32(x32),
                .poc(poc),
                .m12_m22_clk1_m11_m12(gate),
                .data(data),
                .jcn_isz(jcn_isz),
                .jin_fin(jin_fin),
                .jun_jms(jun_jms),
                .cn_n(cn_n),
                .bbl(bbl),
                .jms(jms),
                .sc(sc),
                .dc(dc)
        );
 
        // Instantiate the Scratchpad board
        scratchpad sp_board (
                .sysclk(sysclk),
                .clk1(clk1),
                .clk2(clk2),
                .a12(a12),
                .a22(a22),
                .a32(a32),
                .m12(m12),
                .m22(m22),
                .x12(x12),
                .x22(x22),
                .x32(x32),
                .poc(poc),
                .m12_m22_clk1_m11_m12(gate),
                .data(data),
                .n0636(n0636),
                .sc_m22_clk2(sc_m22_clk2),
                .fin_fim_src_jin(fin_fim_src_jin),
                .inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
                .inc_isz_xch(inc_isz_xch),
                .opa0_n(opa0_n),
                .sc(sc),
                .dc(dc)
        );
 
endmodule

Line No.	Rev	Author	Line
1	2	rrpollack	`timescale 1ns / 1ps
2			`default_nettype none
3			`////////////////////////////////////////////////////////////////////////`
4			`//`
5			`// 4004 CPU Integration Module`
6			`//`
7			`// This file is part of the MCS-4 project hosted at OpenCores:`
8			`// http://www.opencores.org/cores/mcs-4/`
9			`//`
10	4	rrpollack	`// Copyright � 2012, 2020 by Reece Pollack <rrpollack@opencores.org>`
11	2	rrpollack	`//`
12			`// These materials are provided under the Creative Commons`
13			`// "Attribution-NonCommercial-ShareAlike" Public License. They`
14			`// are NOT "public domain" and are protected by copyright.`
15			`//`
16			`// This work based on materials provided by Intel Corporation and`
17			`// others under the same license. See the file doc/License for`
18			`// details of this license.`
19			`//`
20			`////////////////////////////////////////////////////////////////////////`
21
22			`module i4004(`
23			`input wire sysclk,`
24			`input wire clk1_pad,`
25			`input wire clk2_pad,`
26			`input wire poc_pad,`
27			`input wire test_pad,`
28			`inout wire [3:0] data_pad,`
29			`output wire cmrom_pad,`
30			`output wire cmram0_pad,`
31			`output wire cmram1_pad,`
32			`output wire cmram2_pad,`
33			`output wire cmram3_pad,`
34			`output wire sync_pad`
35			`);`
36
37			`// Common BiDir data bus`
38			`wire [3:0] data;`
39
40			`// Timing and I/O Board Outputs`
41			`wire clk1;`
42			`wire clk2;`
43			`wire a12;`
44			`wire a22;`
45			`wire a32;`
46			`wire m12;`
47			`wire m22;`
48			`wire x12;`
49			`wire x22;`
50			`wire x32;`
51			`wire gate;`
52			`wire poc; // Clean POC_PAD`
53			`wire n0432; // Clean TEST_PAD`
54
55			`// Outputs from the Instruction Decode board`
56			`wire jcn_isz;`
57			`wire jin_fin;`
58			`wire jun_jms;`
59			`wire cn_n;`
60			`wire bbl;`
61			`wire jms;`
62			`wire sc;`
63			`wire dc;`
64	4	rrpollack	`wire n0636;`
65	2	rrpollack	`wire sc_m22_clk2;`
66			`wire fin_fim_src_jin;`
67			`wire inc_isz_add_sub_xch_ld;`
68			`wire inc_isz_xch;`
69			`wire opa0_n;`
70			`wire cma;`
71			`wire write_acc_1;`
72			`wire write_carry_2;`
73			`wire read_acc_3;`
74			`wire add_group_4;`
75			`wire inc_group_5;`
76			`wire sub_group_6;`
77			`wire ior;`
78			`wire iow;`
79			`wire ral;`
80			`wire rar;`
81			`wire ope_n;`
82			`wire daa;`
83			`wire dcl;`
84			`wire inc_isz;`
85			`wire kbp;`
86			`wire o_ib;`
87			`wire tcs;`
88			`wire xch;`
89			`wire n0342;`
90			`wire x21_clk2;`
91			`wire x31_clk2;`
92			`wire com_n;`
93
94			`// Outputs from the ALU board`
95			`wire acc_0;`
96			`wire add_0;`
97			`wire cy_1;`
98			`wire cmram0;`
99			`wire cmram1;`
100			`wire cmram2;`
101			`wire cmram3;`
102			`wire cmrom;`
103
104			`// Instantiate the Timing and I/O board`
105			`timing_io tio_board (`
106			`.sysclk(sysclk),`
107			`.clk1_pad(clk1_pad),`
108			`.clk2_pad(clk2_pad),`
109			`.poc_pad(poc_pad),`
110			`.ior(ior),`
111			`.clk1(clk1),`
112			`.clk2(clk2),`
113			`.a12(a12),`
114			`.a22(a22),`
115			`.a32(a32),`
116			`.m12(m12),`
117			`.m22(m22),`
118			`.x12(x12),`
119			`.x22(x22),`
120			`.x32(x32),`
121			`.gate(gate),`
122			`.poc(poc),`
123			`.data(data),`
124			`.data_pad(data_pad),`
125			`.test_pad(test_pad),`
126			`.n0432(n0432),`
127			`.sync_pad(sync_pad),`
128			`.cmrom(cmrom),`
129			`.cmrom_pad(cmrom_pad),`
130			`.cmram0(cmram0),`
131			`.cmram0_pad(cmram0_pad),`
132			`.cmram1(cmram1),`
133			`.cmram1_pad(cmram1_pad),`
134			`.cmram2(cmram2),`
135			`.cmram2_pad(cmram2_pad),`
136			`.cmram3(cmram3),`
137			`.cmram3_pad(cmram3_pad)`
138			`);`
139
140			`// Instantiate the Instruction Decode board`
141			`instruction_decode id_board (`
142			`.sysclk(sysclk),`
143			`.clk1(clk1),`
144			`.clk2(clk2),`
145			`.a22(a22),`
146			`.m12(m12),`
147			`.m22(m22),`
148			`.x12(x12),`
149			`.x22(x22),`
150			`.x32(x32),`
151			`.poc(poc),`
152			`.n0432(n0432),`
153			`.data(data),`
154			`.jcn_isz(jcn_isz),`
155			`.jin_fin(jin_fin),`
156			`.jun_jms(jun_jms),`
157			`.cn_n(cn_n),`
158			`.bbl(bbl),`
159			`.jms(jms),`
160			`.sc(sc),`
161			`.dc(dc),`
162	4	rrpollack	`.n0636(n0636),`
163	2	rrpollack	`.sc_m22_clk2(sc_m22_clk2),`
164			`.fin_fim_src_jin(fin_fim_src_jin),`
165			`.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),`
166			`.inc_isz_xch(inc_isz_xch),`
167			`.opa0_n(opa0_n),`
168			`.acc_0(acc_0),`
169			`.add_0(add_0),`
170			`.cy_1(cy_1),`
171			`.cma(cma),`
172			`.write_acc_1(write_acc_1),`
173			`.write_carry_2(write_carry_2),`
174			`.read_acc_3(read_acc_3),`
175			`.add_group_4(add_group_4),`
176			`.inc_group_5(inc_group_5),`
177			`.sub_group_6(sub_group_6),`
178			`.ior(ior),`
179			`.iow(iow),`
180			`.ral(ral),`
181			`.rar(rar),`
182			`.ope_n(ope_n),`
183			`.daa(daa),`
184			`.dcl(dcl),`
185			`.inc_isz(inc_isz),`
186			`.kbp(kbp),`
187			`.o_ib(o_ib),`
188			`.tcs(tcs),`
189			`.xch(xch),`
190			`.n0342(n0342),`
191			`.x21_clk2(x21_clk2),`
192			`.x31_clk2(x31_clk2),`
193			`.com_n(com_n)`
194			`);`
195
196			`// Instantiate the ALU board`
197			`alu alu_board (`
198			`.sysclk(sysclk),`
199			`.a12(a12),`
200			`.m12(m12),`
201			`.x12(x12),`
202			`.poc(poc),`
203			`.data(data),`
204			`.acc_0(acc_0),`
205			`.add_0(add_0),`
206			`.cy_1(cy_1),`
207			`.cma(cma),`
208			`.write_acc_1(write_acc_1),`
209			`.write_carry_2(write_carry_2),`
210			`.read_acc_3(read_acc_3),`
211			`.add_group_4(add_group_4),`
212			`.inc_group_5(inc_group_5),`
213			`.sub_group_6(sub_group_6),`
214			`.ior(ior),`
215			`.iow(iow),`
216			`.ral(ral),`
217			`.rar(rar),`
218			`.ope_n(ope_n),`
219			`.daa(daa),`
220			`.dcl(dcl),`
221			`.inc_isz(inc_isz),`
222			`.kbp(kbp),`
223			`.o_ib(o_ib),`
224			`.tcs(tcs),`
225			`.xch(xch),`
226			`.n0342(n0342),`
227			`.x21_clk2(x21_clk2),`
228			`.x31_clk2(x31_clk2),`
229			`.com_n(com_n),`
230			`.cmram0(cmram0),`
231			`.cmram1(cmram1),`
232			`.cmram2(cmram2),`
233			`.cmram3(cmram3),`
234			`.cmrom(cmrom)`
235			`);`
236
237			`// Instantiate the Instruction Pointer board`
238			`instruction_pointer ip_board (`
239			`.sysclk(sysclk),`
240			`.clk1(clk1),`
241			`.clk2(clk2),`
242			`.a12(a12),`
243			`.a22(a22),`
244			`.a32(a32),`
245			`.m12(m12),`
246			`.m22(m22),`
247			`.x12(x12),`
248			`.x22(x22),`
249			`.x32(x32),`
250			`.poc(poc),`
251			`.m12_m22_clk1_m11_m12(gate),`
252			`.data(data),`
253			`.jcn_isz(jcn_isz),`
254			`.jin_fin(jin_fin),`
255			`.jun_jms(jun_jms),`
256			`.cn_n(cn_n),`
257			`.bbl(bbl),`
258			`.jms(jms),`
259			`.sc(sc),`
260			`.dc(dc)`
261			`);`
262
263			`// Instantiate the Scratchpad board`
264			`scratchpad sp_board (`
265			`.sysclk(sysclk),`
266			`.clk1(clk1),`
267			`.clk2(clk2),`
268			`.a12(a12),`
269			`.a22(a22),`
270			`.a32(a32),`
271			`.m12(m12),`
272			`.m22(m22),`
273			`.x12(x12),`
274			`.x22(x22),`
275			`.x32(x32),`
276			`.poc(poc),`
277			`.m12_m22_clk1_m11_m12(gate),`
278			`.data(data),`
279	4	rrpollack	`.n0636(n0636),`
280	2	rrpollack	`.sc_m22_clk2(sc_m22_clk2),`
281			`.fin_fim_src_jin(fin_fim_src_jin),`
282			`.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),`
283			`.inc_isz_xch(inc_isz_xch),`
284			`.opa0_n(opa0_n),`
285			`.sc(sc),`
286			`.dc(dc)`
287			`);`
288
289			`endmodule`

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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [i4004/] [i4004.v] - Blame information for rev 5