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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [i4004/] [scratchpad.v] - Blame information for rev 5

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`timescale 1ns / 1ps
`default_nettype none
////////////////////////////////////////////////////////////////////////
// 
// 4004 Scratchpad Register Array
// 
// This file is part of the MCS-4 project hosted at OpenCores:
//      http://www.opencores.org/cores/mcs-4/
// 
// Copyright � 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
// 
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
// 
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
 
module scratchpad (
        input  wire                     sysclk,                                 // 50 MHz FPGA clock
 
        // Inputs from the Timing and I/O board
        input  wire                     clk1,
        input  wire                     clk2,
        input  wire                     a12,
        input  wire                     a22,
        input  wire                     a32,
        input  wire                     m12,
        input  wire                     m22,
        input  wire                     x12,
        input  wire                     x22,
        input  wire                     x32,
        input  wire                     poc,                                    // Power-On Clear (reset)
        input  wire                     m12_m22_clk1_m11_m12,   // M12+M22+CLK1~(M11+M12)
 
        // Common 4-bit data bus
        inout  wire     [3:0]    data,
 
        // Inputs from the Instruction Decode board
        input  wire                     n0636,                                  // JIN+FIN
        input  wire                     sc_m22_clk2,                    // SC&M22&CLK2 
        input  wire                     fin_fim_src_jin,                // FIN+FIM+SRC+JIN
        input  wire                     inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
        input  wire                     inc_isz_xch,                    // INC+ISZ+XCH
        input  wire                     opa0_n,                                 // ~OPA.0
        input  wire                     sc,                                             // SC (Single Cycle)
        input  wire                     dc                                              // DC (Double Cycle, ~SC)
        );
 
        reg  [7:0]       dram_array [0:7];
        reg  [7:0]       dram_temp;
        reg  [3:0]       din_n;
 
        // Refresh counter stuff
        wire [2:0]       reg_rfsh;                               // Row Refresh counter
        wire            reg_rfsh_step;                  // SC&A12&CLK2
 
        assign reg_rfsh_step = sc & a12 & clk2;
 
        counter reg_rfsh_0 (
                .sysclk(sysclk),
                .step_a(clk1),
                .step_b(reg_rfsh_step),
                .q(reg_rfsh[0])
        );
        counter reg_rfsh_1 (
                .sysclk(sysclk),
                .step_a( reg_rfsh[0]),
                .step_b(~reg_rfsh[0]),
                .q(reg_rfsh[1])
        );
        counter reg_rfsh_2 (
                .sysclk(sysclk),
                .step_a( reg_rfsh[1]),
                .step_b(~reg_rfsh[1]),
                .q(reg_rfsh[2])
        );
 
        // Row selection mux
        reg  [2:0]       row;                                    // {N0646, N0617, N0582}
        always @(posedge sysclk) begin
                if (sc & a22)
                        row <= reg_rfsh;
                if (sc_m22_clk2)
                        row <= data[3:1];
        end
 
 
        // Row Precharge/Read/Write stuff
        wire            precharge;                              // SC(A22+M22)CLK2
        wire            row_read;                               // (~POC)&CLK2&SC(A32+X12)
        wire            row_write;                              // CLK2&SC(A12+M12)
 
        assign precharge = sc & (a22 | m22) & clk2;
        assign row_read  = ~(poc | ~(clk2 & sc & (a32 | x12)));
        assign row_write = sc & (a12 | m12) & clk2;
 
 
        // Column Read selection stuff
        reg n0615;
        always @(posedge sysclk) begin
                if (clk2)
                        n0615 <= ~(x12 & (fin_fim_src_jin |
                                        (opa0_n & inc_isz_add_sub_xch_ld)));
        end
        wire rrab0 = ~(dc | n0615 | clk2);
 
        reg n0592;
        always @(posedge sysclk) begin
                if (clk2)
                        n0592 <= ~((x22 & fin_fim_src_jin) |
                                        (~opa0_n & x12 & inc_isz_add_sub_xch_ld));
        end
        wire rrab1 = ~(dc | n0592 | clk2);
 
 
        // Column Write selection stuff
        wire n0564 = opa0_n & fin_fim_src_jin & dc;
        wire n0568 = inc_isz_xch & x32 & sc;
        wire wrab0 = clk2 & ((m12 & n0564) | ( opa0_n & n0568));
        wire wrab1 = clk2 & ((m22 & n0564) | (~opa0_n & n0568));
 
 
        // Force row 0 if FIN&X12
        wire fin_x12 = (n0636 & opa0_n) & x12;
 
        // Manage the row data buffer
        always @(posedge sysclk) begin
                if (precharge)
                        dram_temp <= 8'b0;
 
                if (row_read)
                        dram_temp <= dram_array[fin_x12 ? 3'b000 : row];
 
                if (wrab0)
                        dram_temp[ 7:4] <= ~din_n;
                if (wrab1)
                        dram_temp[ 3:0] <= ~din_n;
        end
 
        // Handle row writes
        always @(posedge sysclk) begin
                if (row_write)
                        dram_array[row] <= dram_temp;
        end
 
        // Manage the data output mux
        reg   [3:0]      dout;
        always @* begin
                (* PARALLEL_CASE *)
                case (1'b1)
                        rrab0:          dout = dram_temp[ 7:4];
                        rrab1:          dout = dram_temp[ 3:0];
                        default:        dout = 4'bzzzz;
                endcase
        end
        assign data = dout;
 
        // Data In latch
        always @(posedge sysclk) begin
                if (m12_m22_clk1_m11_m12)
                        din_n <= ~data;
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	rrpollack	`timescale 1ns / 1ps
2			`default_nettype none
3			`////////////////////////////////////////////////////////////////////////`
4			`//`
5			`// 4004 Scratchpad Register Array`
6			`//`
7			`// This file is part of the MCS-4 project hosted at OpenCores:`
8			`// http://www.opencores.org/cores/mcs-4/`
9			`//`
10	4	rrpollack	`// Copyright � 2012, 2020 by Reece Pollack <rrpollack@opencores.org>`
11	2	rrpollack	`//`
12			`// These materials are provided under the Creative Commons`
13			`// "Attribution-NonCommercial-ShareAlike" Public License. They`
14			`// are NOT "public domain" and are protected by copyright.`
15			`//`
16			`// This work based on materials provided by Intel Corporation and`
17			`// others under the same license. See the file doc/License for`
18			`// details of this license.`
19			`//`
20			`////////////////////////////////////////////////////////////////////////`
21
22			`module scratchpad (`
23			`input wire sysclk, // 50 MHz FPGA clock`
24
25			`// Inputs from the Timing and I/O board`
26			`input wire clk1,`
27			`input wire clk2,`
28			`input wire a12,`
29			`input wire a22,`
30			`input wire a32,`
31			`input wire m12,`
32			`input wire m22,`
33			`input wire x12,`
34			`input wire x22,`
35			`input wire x32,`
36			`input wire poc, // Power-On Clear (reset)`
37			`input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)`
38
39			`// Common 4-bit data bus`
40			`inout wire [3:0] data,`
41
42			`// Inputs from the Instruction Decode board`
43	4	rrpollack	`input wire n0636, // JIN+FIN`
44	2	rrpollack	`input wire sc_m22_clk2, // SC&M22&CLK2`
45			`input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN`
46			`input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD`
47			`input wire inc_isz_xch, // INC+ISZ+XCH`
48			`input wire opa0_n, // ~OPA.0`
49			`input wire sc, // SC (Single Cycle)`
50			`input wire dc // DC (Double Cycle, ~SC)`
51			`);`
52
53			`reg [7:0] dram_array [0:7];`
54			`reg [7:0] dram_temp;`
55			`reg [3:0] din_n;`
56
57			`// Refresh counter stuff`
58			`wire [2:0] reg_rfsh; // Row Refresh counter`
59			`wire reg_rfsh_step; // SC&A12&CLK2`
60
61			`assign reg_rfsh_step = sc & a12 & clk2;`
62
63			`counter reg_rfsh_0 (`
64			`.sysclk(sysclk),`
65			`.step_a(clk1),`
66			`.step_b(reg_rfsh_step),`
67			`.q(reg_rfsh[0])`
68			`);`
69			`counter reg_rfsh_1 (`
70			`.sysclk(sysclk),`
71			`.step_a( reg_rfsh[0]),`
72			`.step_b(~reg_rfsh[0]),`
73			`.q(reg_rfsh[1])`
74			`);`
75			`counter reg_rfsh_2 (`
76			`.sysclk(sysclk),`
77			`.step_a( reg_rfsh[1]),`
78			`.step_b(~reg_rfsh[1]),`
79			`.q(reg_rfsh[2])`
80			`);`
81
82			`// Row selection mux`
83			`reg [2:0] row; // {N0646, N0617, N0582}`
84			`always @(posedge sysclk) begin`
85			`if (sc & a22)`
86			`row <= reg_rfsh;`
87			`if (sc_m22_clk2)`
88			`row <= data[3:1];`
89			`end`
90
91
92			`// Row Precharge/Read/Write stuff`
93			`wire precharge; // SC(A22+M22)CLK2`
94			`wire row_read; // (~POC)&CLK2&SC(A32+X12)`
95			`wire row_write; // CLK2&SC(A12+M12)`
96
97			`assign precharge = sc & (a22 \| m22) & clk2;`
98			`assign row_read = ~(poc \| ~(clk2 & sc & (a32 \| x12)));`
99			`assign row_write = sc & (a12 \| m12) & clk2;`
100
101
102			`// Column Read selection stuff`
103			`reg n0615;`
104			`always @(posedge sysclk) begin`
105			`if (clk2)`
106			`n0615 <= ~(x12 & (fin_fim_src_jin \|`
107			`(opa0_n & inc_isz_add_sub_xch_ld)));`
108			`end`
109			`wire rrab0 = ~(dc \| n0615 \| clk2);`
110
111			`reg n0592;`
112			`always @(posedge sysclk) begin`
113			`if (clk2)`
114			`n0592 <= ~((x22 & fin_fim_src_jin) \|`
115			`(~opa0_n & x12 & inc_isz_add_sub_xch_ld));`
116			`end`
117			`wire rrab1 = ~(dc \| n0592 \| clk2);`
118
119
120			`// Column Write selection stuff`
121			`wire n0564 = opa0_n & fin_fim_src_jin & dc;`
122			`wire n0568 = inc_isz_xch & x32 & sc;`
123			`wire wrab0 = clk2 & ((m12 & n0564) \| ( opa0_n & n0568));`
124			`wire wrab1 = clk2 & ((m22 & n0564) \| (~opa0_n & n0568));`
125
126
127	4	rrpollack	`// Force row 0 if FIN&X12`
128			`wire fin_x12 = (n0636 & opa0_n) & x12;`
129
130	2	rrpollack	`// Manage the row data buffer`
131			`always @(posedge sysclk) begin`
132			`if (precharge)`
133			`dram_temp <= 8'b0;`
134
135			`if (row_read)`
136	4	rrpollack	`dram_temp <= dram_array[fin_x12 ? 3'b000 : row];`
137	2	rrpollack
138			`if (wrab0)`
139	4	rrpollack	`dram_temp[ 7:4] <= ~din_n;`
140			`if (wrab1)`
141	2	rrpollack	`dram_temp[ 3:0] <= ~din_n;`
142			`end`
143
144			`// Handle row writes`
145			`always @(posedge sysclk) begin`
146			`if (row_write)`
147			`dram_array[row] <= dram_temp;`
148			`end`
149
150			`// Manage the data output mux`
151			`reg [3:0] dout;`
152			`always @* begin`
153			`(* PARALLEL_CASE *)`
154			`case (1'b1)`
155	4	rrpollack	`rrab0: dout = dram_temp[ 7:4];`
156			`rrab1: dout = dram_temp[ 3:0];`
157	2	rrpollack	`default: dout = 4'bzzzz;`
158			`endcase`
159			`end`
160			`assign data = dout;`
161
162			`// Data In latch`
163			`always @(posedge sysclk) begin`
164			`if (m12_m22_clk1_m11_m12)`
165			`din_n <= ~data;`
166			`end`
167
168			`endmodule`

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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [i4004/] [scratchpad.v] - Blame information for rev 5