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[/] [mdct/] [trunk/] [source/] [DCT1D.vhd] - Blame information for rev 27

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1 2 mikel262
--------------------------------------------------------------------------------
2
--                                                                            --
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--                          V H D L    F I L E                                --
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--                          COPYRIGHT (C) 2006                                --
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--                                                                            --
6
--------------------------------------------------------------------------------
7
--
8
-- Title       : DCT1D
9
-- Design      : MDCT Core
10
-- Author      : Michal Krepa
11
--
12
--------------------------------------------------------------------------------
13
--
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-- File        : DCT1D.VHD
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-- Created     : Sat Mar 5 7:37 2006
16
--
17
--------------------------------------------------------------------------------
18
--
19
--  Description : 1D Discrete Cosine Transform (1st stage)
20
--
21
--------------------------------------------------------------------------------
22
 
23
 
24
library IEEE;
25
  use IEEE.STD_LOGIC_1164.all;
26
  use IEEE.NUMERIC_STD.all;
27
 
28
library WORK;
29
  use WORK.MDCT_PKG.all;
30
 
31
--------------------------------------------------------------------------------
32
-- ENTITY
33
--------------------------------------------------------------------------------
34
entity DCT1D is
35
        port(
36
                  clk          : in STD_LOGIC;
37
                  rst          : in std_logic;
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      dcti         : in std_logic_vector(IP_W-1 downto 0);
39
      idv          : in STD_LOGIC;
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      romedatao    : in T_ROM1DATAO;
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      romodatao    : in T_ROM1DATAO;
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43
      odv          : out STD_LOGIC;
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      dcto         : out std_logic_vector(OP_W-1 downto 0);
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      romeaddro    : out T_ROM1ADDRO;
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      romoaddro    : out T_ROM1ADDRO;
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      ramwaddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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      ramdatai     : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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      ramwe        : out STD_LOGIC;
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      wmemsel      : out STD_LOGIC
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                );
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end DCT1D;
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--------------------------------------------------------------------------------
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-- ARCHITECTURE
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--------------------------------------------------------------------------------
57
architecture RTL of DCT1D is
58
 
59
  type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
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  signal databuf_reg     : INPUT_DATA;
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  signal latchbuf_reg    : INPUT_DATA;
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  signal col_reg         : UNSIGNED(RAMADRR_W/2-1 downto 0);
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  signal row_reg         : UNSIGNED(RAMADRR_W/2-1 downto 0);
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  signal rowr_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
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  signal inpcnt_reg      : UNSIGNED(RAMADRR_W/2-1 downto 0);
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  signal ramwe_s         : STD_LOGIC;
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  signal wmemsel_reg     : STD_LOGIC;
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  signal stage2_reg      : STD_LOGIC;
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  signal stage2_cnt_reg  : UNSIGNED(RAMADRR_W-1 downto 0);
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  signal col_2_reg       : UNSIGNED(RAMADRR_W/2-1 downto 0);
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  signal ramwaddro_s     : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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74 27 mikel262
  signal even_not_odd    : std_logic;
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  signal even_not_odd_d1 : std_logic;
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  signal even_not_odd_d2 : std_logic;
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  signal even_not_odd_d3 : std_logic;
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  signal ramwe_d1        : STD_LOGIC;
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  signal ramwe_d2        : STD_LOGIC;
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  signal ramwe_d3        : STD_LOGIC;
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  signal ramwe_d4        : STD_LOGIC;
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  signal ramwaddro_d1    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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  signal ramwaddro_d2    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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  signal ramwaddro_d3    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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  signal ramwaddro_d4    : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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  signal wmemsel_d1      : STD_LOGIC;
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  signal wmemsel_d2      : STD_LOGIC;
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  signal wmemsel_d3      : STD_LOGIC;
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  signal wmemsel_d4      : STD_LOGIC;
90
  signal romedatao_d1    : T_ROM1DATAO;
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  signal romodatao_d1    : T_ROM1DATAO;
92
  signal romedatao_d2    : T_ROM1DATAO;
93
  signal romodatao_d2    : T_ROM1DATAO;
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  signal romedatao_d3    : T_ROM1DATAO;
95
  signal romodatao_d3    : T_ROM1DATAO;
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  signal dcto_1          : STD_LOGIC_VECTOR(DA_W-1 downto 0);
97
  signal dcto_2          : STD_LOGIC_VECTOR(DA_W-1 downto 0);
98
  signal dcto_3          : STD_LOGIC_VECTOR(DA_W-1 downto 0);
99
  signal dcto_4          : STD_LOGIC_VECTOR(DA_W-1 downto 0);
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begin
102
 
103
  ramwaddro <= ramwaddro_d4;
104
  ramwe     <= ramwe_d4;
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  ramdatai  <= dcto_4(DA_W-1 downto 12);
106
  wmemsel   <= wmemsel_d4;
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108 27 mikel262
  process(clk,rst)
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  begin
110 27 mikel262
    if rst = '1' then
111
      inpcnt_reg      <= (others => '0');
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      latchbuf_reg    <= (others => (others => '0'));
113
      databuf_reg     <= (others => (others => '0'));
114
      stage2_reg      <= '0';
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      stage2_cnt_reg  <= (others => '1');
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      ramwe_s         <= '0';
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      ramwaddro_s     <= (others => '0');
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      col_reg         <= (others => '0');
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      row_reg         <= (others => '0');
120
      wmemsel_reg     <= '0';
121
      col_2_reg       <= (others => '0');
122
    elsif clk = '1' and clk'event then
123
      stage2_reg     <= '0';
124
      ramwe_s        <= '0';
125
 
126
      --------------------------------
127
      -- 1st stage
128
      --------------------------------
129
      if idv = '1' then
130
 
131
        inpcnt_reg    <= inpcnt_reg + 1;
132
 
133
        -- right shift input data
134
        latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
135
        latchbuf_reg(N-1)          <= SIGNED('0' & dcti) - LEVEL_SHIFT;
136
 
137
        if inpcnt_reg = N-1 then
138
          -- after this sum databuf_reg is in range of -256 to 254 (min to max) 
139
          databuf_reg(0)  <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
140
          databuf_reg(1)  <= latchbuf_reg(2)+latchbuf_reg(7);
141
          databuf_reg(2)  <= latchbuf_reg(3)+latchbuf_reg(6);
142
          databuf_reg(3)  <= latchbuf_reg(4)+latchbuf_reg(5);
143
          databuf_reg(4)  <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
144
          databuf_reg(5)  <= latchbuf_reg(2)-latchbuf_reg(7);
145
          databuf_reg(6)  <= latchbuf_reg(3)-latchbuf_reg(6);
146
          databuf_reg(7)  <= latchbuf_reg(4)-latchbuf_reg(5);
147
          stage2_reg      <= '1';
148 10 mikel262
        end if;
149 27 mikel262
      end if;
150
      --------------------------------
151
 
152
      --------------------------------
153
      -- 2nd stage
154
      --------------------------------
155
      if stage2_cnt_reg < N then
156 2 mikel262
 
157 27 mikel262
        stage2_cnt_reg <= stage2_cnt_reg + 1;
158
 
159
        -- write RAM
160
        ramwe_s   <= '1';
161
        -- reverse col/row order for transposition purpose
162
        ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
163
        -- increment column counter
164
        col_reg   <= col_reg + 1;
165
        col_2_reg <= col_2_reg + 1;
166
 
167
        -- finished processing one input row
168
        if col_reg = 0 then
169
          row_reg         <= row_reg + 1;
170
          -- switch to 2nd memory
171
          if row_reg = N - 1 then
172
            wmemsel_reg <= not wmemsel_reg;
173
            col_reg         <= (others => '0');
174 18 mikel262
          end if;
175 27 mikel262
        end if;
176
 
177 15 mikel262
      end if;
178 27 mikel262
 
179
      if stage2_reg = '1' then
180
        stage2_cnt_reg <= (others => '0');
181
        col_reg        <= (0=>'1',others => '0');
182
        col_2_reg      <= (others => '0');
183
      end if;
184
      ----------------------------------   
185
 
186
 
187 2 mikel262
    end if;
188
  end process;
189
 
190 27 mikel262
  -- output data pipeline
191
  p_data_out_pipe : process(CLK, RST)
192
  begin
193
    if RST = '1' then
194
      even_not_odd    <= '0';
195
      even_not_odd_d1 <= '0';
196
      even_not_odd_d2 <= '0';
197
      even_not_odd_d3 <= '0';
198
      ramwe_d1        <= '0';
199
      ramwe_d2        <= '0';
200
      ramwe_d3        <= '0';
201
      ramwe_d4        <= '0';
202
      ramwaddro_d1    <= (others => '0');
203
      ramwaddro_d2    <= (others => '0');
204
      ramwaddro_d3    <= (others => '0');
205
      ramwaddro_d4    <= (others => '0');
206
      wmemsel_d1      <= '0';
207
      wmemsel_d2      <= '0';
208
      wmemsel_d3      <= '0';
209
      wmemsel_d4      <= '0';
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      dcto_1          <= (others => '0');
211
      dcto_2          <= (others => '0');
212
      dcto_3          <= (others => '0');
213
      dcto_4          <= (others => '0');
214
    elsif CLK'event and CLK = '1' then
215
      even_not_odd    <= stage2_cnt_reg(0);
216
      even_not_odd_d1 <= even_not_odd;
217
      even_not_odd_d2 <= even_not_odd_d1;
218
      even_not_odd_d3 <= even_not_odd_d2;
219
      ramwe_d1        <= ramwe_s;
220
      ramwe_d2        <= ramwe_d1;
221
      ramwe_d3        <= ramwe_d2;
222
      ramwe_d4        <= ramwe_d3;
223
      ramwaddro_d1    <= ramwaddro_s;
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      ramwaddro_d2    <= ramwaddro_d1;
225
      ramwaddro_d3    <= ramwaddro_d2;
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      ramwaddro_d4    <= ramwaddro_d3;
227
      wmemsel_d1      <= wmemsel_reg;
228
      wmemsel_d2      <= wmemsel_d1;
229
      wmemsel_d3      <= wmemsel_d2;
230
      wmemsel_d4      <= wmemsel_d3;
231
 
232
      if even_not_odd = '0' then
233
        dcto_1 <= STD_LOGIC_VECTOR(RESIZE
234
          (RESIZE(SIGNED(romedatao(0)),DA_W) +
235
          (RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
236
          (RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
237
          DA_W));
238
      else
239
        dcto_1 <= STD_LOGIC_VECTOR(RESIZE
240
          (RESIZE(SIGNED(romodatao(0)),DA_W) +
241
          (RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
242
          (RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
243
          DA_W));
244
      end if;
245
 
246
      if even_not_odd_d1 = '0' then
247
        dcto_2 <= STD_LOGIC_VECTOR(RESIZE
248
          (signed(dcto_1) +
249
          (RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
250
          (RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
251
          DA_W));
252
      else
253
        dcto_2 <= STD_LOGIC_VECTOR(RESIZE
254
          (signed(dcto_1) +
255
          (RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
256
          (RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
257
          DA_W));
258
      end if;
259
 
260
      if even_not_odd_d2 = '0' then
261
        dcto_3 <= STD_LOGIC_VECTOR(RESIZE
262
          (signed(dcto_2) +
263
          (RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
264
          (RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
265
          DA_W));
266
      else
267
        dcto_3 <= STD_LOGIC_VECTOR(RESIZE
268
          (signed(dcto_2) +
269
          (RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
270
          (RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
271
          DA_W));
272
      end if;
273
 
274
      if even_not_odd_d3 = '0' then
275
        dcto_4 <= STD_LOGIC_VECTOR(RESIZE
276
          (signed(dcto_3) +
277
          (RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
278
          (RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
279
          DA_W));
280
      else
281
        dcto_4 <= STD_LOGIC_VECTOR(RESIZE
282
          (signed(dcto_3) +
283
          (RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
284
          (RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
285
          DA_W));
286
      end if;
287
    end if;
288
  end process;
289
 
290 4 mikel262
  -- read precomputed MAC results from LUT
291 27 mikel262
  p_romaddr : process(CLK, RST)
292
  begin
293
    if RST = '1' then
294
      romeaddro   <= (others => (others => '0'));
295
      romoaddro   <= (others => (others => '0'));
296
    elsif CLK'event and CLK = '1' then
297
      for i in 0 to 8 loop
298
        -- even
299
        romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
300
                 databuf_reg(0)(i) &
301
                 databuf_reg(1)(i) &
302
                 databuf_reg(2)(i) &
303
                 databuf_reg(3)(i);
304
        -- odd
305
        romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
306
                 databuf_reg(4)(i) &
307
                 databuf_reg(5)(i) &
308
                 databuf_reg(6)(i) &
309
                 databuf_reg(7)(i);
310
      end loop;
311
    end if;
312
  end process;
313 4 mikel262
 
314 27 mikel262
  p_romdatao_d1 : process(CLK, RST)
315
  begin
316
    if RST = '1' then
317
      romedatao_d1    <= (others => (others => '0'));
318
      romodatao_d1    <= (others => (others => '0'));
319
      romedatao_d2    <= (others => (others => '0'));
320
      romodatao_d2    <= (others => (others => '0'));
321
      romedatao_d3    <= (others => (others => '0'));
322
      romodatao_d3    <= (others => (others => '0'));
323
    elsif CLK'event and CLK = '1' then
324
      romedatao_d1   <= romedatao;
325
      romodatao_d1   <= romodatao;
326
      romedatao_d2   <= romedatao_d1;
327
      romodatao_d2   <= romodatao_d1;
328
      romedatao_d3   <= romedatao_d2;
329
      romodatao_d3   <= romodatao_d2;
330
    end if;
331
  end process;
332
 
333 2 mikel262
end RTL;
334
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