OpenCores
URL https://opencores.org/ocsvn/mini_aes/mini_aes/trunk

Subversion Repositories mini_aes

[/] [mini_aes/] [trunk/] [source/] [io_interface.vhdl] - Blame information for rev 21

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 21 arif_endro 
-- ------------------------------------------------------------------------
2 15 arif_endro 
-- Copyright (C) 2005 Arif Endro Nugroho
3 21 arif_endro 
-- All rights reserved.
4 4 arif_endro 
--
5 21 arif_endro 
-- Redistribution and use in source and binary forms, with or without
6 
-- modification, are permitted provided that the following conditions
7 
-- are met:
8 4 arif_endro 
--
9 21 arif_endro 
-- 1. Redistributions of source code must retain the above copyright
10 
--    notice, this list of conditions and the following disclaimer.
11 
-- 2. Redistributions in binary form must reproduce the above copyright
12 
--    notice, this list of conditions and the following disclaimer in the
13 
--    documentation and/or other materials provided with the distribution.
14 
-- 3. The name of Arif Endro Nugroho may not be used to endorse or promote
15 
--    products derived from this software without specific prior written
16 
--    permission.
17 4 arif_endro 
--
18 21 arif_endro 
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
19 
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
22 
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26 
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
27 
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 
-- POSSIBILITY OF SUCH DAMAGE.
29 4 arif_endro 
--
30 21 arif_endro 
-- End Of License.
31 
-- ------------------------------------------------------------------------
32 
 
33 4 arif_endro 
library ieee;
34 
use ieee.std_logic_1164.all;
35 
use ieee.std_logic_arith.all;
36 
use ieee.std_logic_unsigned.all;
37 
 
38 
entity io_interface is
39 
   port (
40 
      clock      : in  std_logic;
41 
      clear      : in  std_logic;
42 
      load_i     : in  std_logic;
43 
      load_i_int : out std_logic;
44 
      data_i     : in  std_logic_vector (7 downto 0);
45 
      key_i      : in  std_logic_vector (7 downto 0);
46 
      data_o     : out std_logic_vector (7 downto 0);
47 
      data_o_int : in  std_logic_vector (127 downto 000);
48 
      data_i_int : out std_logic_vector (127 downto 000);
49 
      key_i_int  : out std_logic_vector (127 downto 000);
50 
      done_o_int : in  std_logic;
51 
      done_o     : out std_logic
52 
      );
53 
end io_interface;
54 
 
55 
architecture data_flow of io_interface is
56 
 
57 
type fifo16x8 is array ( 0 to 15 ) of std_logic_vector (7 downto 0);
58 
 
59 
signal fifo_data : fifo16x8 :=
60 
(
61 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
62 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
63 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
64 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
65 
);
66 
 
67 
signal fifo_key : fifo16x8 :=
68 
(
69 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
70 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
71 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
72 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
73 
);
74 
 
75 
signal fifo_output : fifo16x8 :=
76 
(
77 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
78 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
79 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
80 
 B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
81 
);
82 
 
83 
signal load_core   : std_logic := '0';
84 
signal done_int    : std_logic := '0';
85 
signal up_counter  : integer range 0 to 15 := 0;
86 
-- signal data_o_int : std_logic_vector (127 downto 000) :=
87 
--   ( X"3925841D_02DC09FB_DC118597_196A0B32" );  -- CT 0
88 
 
89 
begin
90 
 
91 
load_i_int <= load_core;
92 
 
93 
process(clock, clear)
94 
begin
95 
if (clear = '1') then
96 
   done_o <= '0';
97 
elsif (clock = '1' and clock'event) then
98 
   done_o <= done_int;
99 
end if;
100 
end process;
101 
 
102 
process(clock, clear)
103 
begin
104 
if (clear = '1') then
105 
   up_counter <= 0;
106 
elsif (clock = '1' and clock'event) then
107 
   if (done_o_int = '1') then
108 
      up_counter <= 0;
109 
-- elsif ((up_counter = 0) and (done_o_int = '1')) then
110 
-- elsif (done_o_int = '0' and done_o_int'event) then
111 
-- 20051219 FIXME
112 
      done_int   <= '1';
113 
   elsif (up_counter < 15 ) then
114 
      up_counter <= up_counter + 1;
115 
   else
116 
--    up_counter <= 0;
117 
      done_int   <= '0';
118 
   end if;
119 
end if;
120 
end process;
121 
 
122 
process(clock, clear)
123 
begin
124 
if (clear = '1') then
125 
   fifo_output <= (others => (others => '0'));
126 
elsif (clock = '1' and clock'event) then
127 
   if (done_o_int = '1') then
128 
      fifo_output <= ( data_o_int (127 downto 120), data_o_int (119 downto 112), data_o_int (111 downto 104),
129 
                       data_o_int (103 downto 096), data_o_int (095 downto 088), data_o_int (087 downto 080),
130 
                       data_o_int (079 downto 072), data_o_int (071 downto 064), data_o_int (063 downto 056),
131 
                       data_o_int (055 downto 048), data_o_int (047 downto 040), data_o_int (039 downto 032),
132 
                       data_o_int (031 downto 024), data_o_int (023 downto 016), data_o_int (015 downto 008),
133 
                       data_o_int (007 downto 000));
134 
   end if;
135 
end if;
136 
end process;
137 
 
138 
process(clock, clear)
139 
begin
140 
if (clear = '1') then
141 
data_o <= (others => '0');
142 
elsif (clock = '1' and clock'event) then
143 
data_o <= fifo_output(up_counter);
144 
end if;
145 
end process;
146 
 
147 
process(clock, clear)
148 
begin
149 
   if (clear = '1') then
150 
      fifo_key     <= (others => (others => '0'));
151 
      fifo_data    <= (others => (others => '0'));
152 
      load_core    <= '1';
153 
   elsif (clock = '1' and clock'event) then
154 
      if (load_i  = '1') then
155 
         fifo_key     <= (fifo_key (1 to 15) & key_i);
156 
         fifo_data    <= (fifo_data (1 to 15) & data_i);
157 
      end if;
158 
         load_core    <= load_i;
159 
   end if;
160 
end process;
161 
 
162 
key_i_int<= ( fifo_key (00) & fifo_key (01) & fifo_key (02) & fifo_key (03) &
163 
              fifo_key (04) & fifo_key (05) & fifo_key (06) & fifo_key (07) &
164 
              fifo_key (08) & fifo_key (09) & fifo_key (10) & fifo_key (11) &
165 
              fifo_key (12) & fifo_key (13) & fifo_key (14) & fifo_key (15) );
166 
 
167 
data_i_int<= ( fifo_data (00) & fifo_data (01) & fifo_data (02) & fifo_data (03) &
168 
               fifo_data (04) & fifo_data (05) & fifo_data (06) & fifo_data (07) &
169 
               fifo_data (08) & fifo_data (09) & fifo_data (10) & fifo_data (11) &
170 
               fifo_data (12) & fifo_data (13) & fifo_data (14) & fifo_data (15) );
171 
 
172 
end data_flow;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.